Supercap Charger / Balancer for Short Hold-Up
← Back to: Battery Charging / Gauging / Protection / BMS
This page exists because supercapacitor charging is not the same as Li-ion CC/CV. With supercaps we must limit the initial large inrush, keep series-stacked caps balanced, and guarantee a short 3–10 s hold-up for the system. That’s why it needs its own subpage under the Battery Charging / Gauging / Protection / BMS hub.
1. What this page covers
- Charging path for supercaps (2–6S) with large-current limiting.
- SOC / SOE estimation for “can we still hold for a few seconds?”.
- Balancing hooks so per-cap overvoltage will not kill the bank.
- Target users: 12/24 V automotive subsystems, industrial gateways, comms/automation controllers, small ESS hold-up rails.
We explicitly do not cover
- Phone / handset Li-ion JEITA details.
- USB-C / PD negotiation flows.
- Full BMS daisy-chain / iso-SPI stacks.
2. Scenario & Boundaries
This subpage mainly targets 2–3S and 4–6S supercap banks used for 12/24 V systems to survive short bus interruptions. We must current-limit the initial charge because, in practice, we are “adding a big capacitor to an already running bus”.
① Single Cap
1 cell, low energy, often just keep-alive.
Balance: not required · Input: 5–12 V.
② 2–3S Bank
5–9 V equivalent, now series-stacked → needs per-cap monitor.
Balance: recommended · Input: 12–24 V.
③ 4–6S Hold-Up
12 V class hold-up, short 3–10 s, must current-limit.
Balance: required · Input: 12–24 V / DC bus.
Out of scope: braking-energy supercap systems, 2:1 / 4:1 high-voltage direct fast charge, and hour-level UPS use. Those should live in their own subpages to avoid intent overlap.
3. Supercap Charging Block Decomposition
The supercap charger for short hold-up (2–6S) is not a single IC. It is a left-to-right chain that starts from the DC bus, limits the initial inrush, runs a voltage/current-controlled charge into a stacked supercap bank, monitors each cap, offers balancing hooks, and then reports energy to the host. Below is the full chain.
Input / Source
DC bus / 12 V / 24 V / adapter / USB-C→DC.
Inrush / Large-Current Limiter
External FET + Rsense + programmable limit. Because supercap starts at 0 V.
Charge Controller for Supercap
Voltage loop, current loop, termination / recharge rules.
Supercap Bank (2–6S)
Stacked cells for 12 V class hold-up.
Per-Cap Sensing & OVP
Because in series, imbalance kills the pack — each cap must be watched.
Balancing Hooks
Passive / active / external board — this page only defines the hook, not the full algorithm.
SOC / SOE Estimator
Use E = 1/2·C·V², not battery OCV tables. Add temperature / aging correction.
System Report / Host I/F
I²C / SPI / ALERT lines → BMS / MCU.
Fault & Shutdown
Per-cap OVP, bus collapse, shorted cap → fast disconnect.
Out-of-scope for this subpage: USB-C/PD negotiation, pack-level balancing algorithms, long-duration UPS supercap systems, and full BMS daisy-chain stacks — those live in their own pages to avoid intent overlap.
4. Inrush / Soft-Start / dV/dt Control
Supercaps start at 0 V. If we connect them directly to a live 12/24 V bus, the bus can sag and reset the MCU, DC-DC or communications. Therefore, inrush control is a core part of the charger, not an optional add-on.
A. FET + Rsense + ILIM pin
Most ICs from the seven brands support this.
Pros: precise limiting, bus stays up. Watch FET thermal.
B. Staged / two-step charge
Pre-charge small, then main charge.
Best for bigger banks or limited bus capacity.
C. dV/dt limited ramp
Control the voltage rise slope, not only current.
Good for sensitive industrial / comms supplies.
For short hold-up use, we can set the current limit higher so the bank recovers quickly. For repetitive charge/discharge, limits must consider FET and Rsense heating, and a temperature derating path should be enabled.
Layout notes for engineers: use Kelvin sense around the current-sense resistor, pick FETs with reasonable gate charge / low gate resistance, and add temperature input for derating.
Out-of-scope here: power-path VIN↔VSYS management, ISO 7637 surge sequences, and multi-phase current sharing. Those belong to their dedicated subpages.
5. Supercap SOC / SOE Estimation Method
We estimate SOC / SOE for short hold-up supercap banks to answer just one question: “can we still support the target 3–10 s interruption?” Unlike Li-ion packs, supercapacitors do not follow an OCV→SOC curve. We must use the energy formula E = 1/2 · C · V² and normalize it to the rated maximum energy.
Why estimate?
Short hold-up must know “how many seconds are left” and must report to MCU / BMS.
Why not Li-ion OCV?
Supercaps start at 0 V, energy is V²-related, and series banks have per-cap variation.
Target users
Automotive 12/24 V subsystems, industrial/telecom hold-up, small ESS add-ons.
- Sample every cap → detect over-voltage first.
- Convert all Vᵢ to energy with
Eᵢ = 1/2 · Cᵢ · Vᵢ², sum to E_total, then divide by E_max. - Map to status → e.g. “Cap ready ≥ 90%” → send to MCU / BMS over I²C/SPI.
Correction factors to mention: capacitor tolerance (±10~20%), low-temperature derating, aging / ESR increase, and reduced effective C for series banks. That is why many designs let the MCU finish the estimation.
6. Supercap Balancing Strategies
Series-stacked supercaps will not charge identically. One cap hitting over-voltage first will age faster and reduce bank life. This subpage is in the Charging domain, so we only define where to sense, where to bleed, and where to connect an external balancer. The full BMS balancing algorithm is defined in the main BMS controller page.
1) Passive bleed / shunt
Simple resistor or MOS-controlled resistor across the cap.
Good for 2–3S, trimming role, watch heat.
2) Active transfer / cross-cap
Moves energy from higher to lower cells.
For 4–6S, 12 V hold-up, or wide temperature.
3) External balancer board
When the charger IC has no internal balancing.
Expose test pads / headers for later clamp-on.
Design hint: always bring out per-cap test points. This keeps the charging subpage simple and lets procurement / service teams attach an external balancer board when the charger IC does not integrate balancing.
7. Protection & Faults (Supercap Line)
This fault layer protects the DC bus from a misbehaving supercap bank and protects the supercaps from abusive charge conditions. It does not replace the main protection page in your BMS tree — it only defines supercap-specific faults.
Per-cap OVP
One cell exceeds Vcap,max → stop charge or enable bleed → alert MCU.
String / total OVP
Whole bank hits max working voltage → disconnect / hold / report.
Input reverse / bus sag
Protect the bus from being pulled down or back-fed by the supercap side.
Shorted cap / external short
Supercaps can short in the field → fast isolation is mandatory to avoid killing the bus.
NTC high / thermal derating
Inrush devices and passive balancing can heat up → limit time or derate current.
Recovery policy: soft faults (cap OVP, NTC high) → MCU may retry; hard faults (shorted cap, reverse) → require host decision. This keeps this charging subpage from overlapping with the main protection page.
8. Interface to Main BMS / Host MCU
The main BMS must know if the supercap bank can still deliver its designed hold-up window, so it can preemptively shed loads or finish critical writes. This section only defines the interface lines, not the BMS daisy-chain protocol, to avoid overlap with the BMS core page.
1) PGOOD / READY line
Single wire: CAP_READY / HOLDUP_OK → MCU. Easiest way for small systems.
2) I²C / SPI polling
BMS reads cap voltages, SOE, fault flags. Needs registers exposed.
3) Alert line into BMS
ALERT#/FAULT# shared with other sources, but tagged as “supercap”.
Out-of-scope here: BMS daisy-chain protocols, CAN message maps, and main pack charge/discharge strategies. This keeps the supercap charging subpage independent and non-overlapping.
9. Validation & Test Matrix
Below is a must-run test set for supercap charger / balancer in short hold-up applications. These are real validation cases, not optional suggestions. Each case should be recorded in the project log and can be mirrored in BOM / qualification notes.
Cold-start @ 0 V
Supercap fully discharged → 12/24 V bus must not brown-out the MCU.
High-temp limit
Current limiter and balancer must still hold the programmed current under thermal stress.
Per-cap OVP test
Force one cap high → charger must stop or bleed and raise ALERT.
Fast re-charge
After a hold-up event, limiter must run again, no second bus dip.
Interface in charge
I²C/SPI polling must work during charge / balance without bus lock.
EMI / surge
Inrush must not trip or reset the front DCDC when supercap engages.
BOM remark (ready to paste): “Tested supercap charge at 12 V bus with staged inrush; per-cap OVP verified; balancing MOSFETs reach <60°C at 25°C ambient.”
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10. Frequently Asked Questions
Only questions that this subpage can answer are listed here — charging, measuring, balancing, and interfacing the supercap branch. USB-C PD, main BMS daisy-chain and long-duration UPS use are intentionally excluded.
How do I limit the initial inrush so the 12 V / 24 V bus won’t brown-out?
Use staged inrush: turn on a small FET / small current path first, let the supercap climb, then enable the main FET. You can also do dV/dt control so the bus “sees” a slow rise instead of a step.
Can I reuse a Li-ion battery charger IC to charge a supercap bank?
Only if the IC has a supercap / EDLC mode. Supercaps use different voltage windows and termination logic; a Li-ion CC/CV charger may overcharge a cap string.
Do I really need V²-based SOC / SOE for supercaps?
Yes — energy in a capacitor is 1/2·C·V², so the useful state is proportional to V², not V. Without V² you will overestimate hold-up time.
Does a 2S supercap bank always need balancing?
Small matched banks can run with monitoring-only, but best practice is to reserve balancing hooks (pads or MOS) so you can add a board later if drift appears.
What should I do when one cap hits over-voltage first?
Stop or slow the global charge, enable bleed on that cell, and raise ALERT to the host. Do not keep charging the whole stack at full current.
How fast should I re-charge after a hold-up event?
Re-run the inrush / current limit sequence to protect the bus. Fast recovery is OK, but the bus must stay the priority supply.
Can the supercap bank stay permanently on the 12 V / 24 V line?
Yes, but check leakage and balancing thermal limits. Use a current limiter and temperature feedback to avoid long-term heating.
How do I route NTC / temperature into the charge control loop?
Tie NTC to the same limiter that controls inrush and balancing power. High temp → scale down ILIM or balance duty → optionally report to MCU.
Which vendors have multi-cell monitor / balance parts?
Common sources in this page’s scope: TI, ST, Renesas, onsemi, Microchip, Melexis. Pick by voltage per cell, temp sensing and I²C/SPI compatibility.
How do I report “cap ready / cap low” to the host?
Use a single READY line for simple systems; or expose SOC / fault bits via I²C / SPI; or OR the supercap ALERT# into the main BMS alert line.
Is passive balancing enough for automotive 12 V hold-up?
For 2–3S and short hold-up yes, if thermal is controlled. For 4–6S or wide-temp automotive designs, plan for active or external balancer.
What layout rules for high-current supercap charging?
Use Kelvin sense to the current shunt, keep charge loop short and wide, pick FETs with low gate resistance, and route balancing heat away from the caps.
