Parallel & Current Sharing: Interleaving, Balancing, and Fault Bypass
Parallel & Current Sharing
Multiple regulated rails drive the same VOUT while each rail’s current is controlled to match a target share.
What it is
Two or more identical/near-identical converters tied to one output node; control keeps Ii ≈ Iavg.
What it isn’t
Pure ORing for redundancy only—no regulation of current balance.
Targets
- Share skew ≤ 5% at rated load
- Rail-to-rail ΔT < 10 °C steady state
Working Principle
Sense current per rail → compare to a common reference (droop / share bus / average-current) → adjust duty/gate-slew so currents converge. Keep the share loop well below the voltage loop bandwidth.
Current measurement
- Shunt (Kelvin) — best linearity; check loss & layout
- Inductor DCR — no series loss; match RC within ±5%
- In-package sense — verify offset/scale alignment
Share law
- Droop (passive AVP): VOUT=VREF−k·IOUT
- Active share bus (master/slave): ISHARE sums currents; Ii → Iavg
- Average-current mode: inner current loop per rail
Loop placement
- fshare ≈ 0.1–0.2 × fc (avoid ping-pong)
- Align anti-alias RC & blanking/ILIM filters
- Kelvin sense; isolate from SW polygons
- Skew ≤ 5% (rated load)
- ΔT between rails < 10 °C
fshare ≈ 0.1–0.2 × fc (voltage-loop crossover)
- Kelvin both sides of shunts
- Anti-alias RC matched within ±5%
- Keep sense pairs away from SW polygons
Methods of Sharing
Choose the method by accuracy, dynamics, wiring simplicity, and redundancy needs.
Droop (passive AVP)
Simplest; tolerant to wiring mismatch. Trade-off: poorer load regulation.
Active share bus (master/slave)
Accurate and dynamic; requires matched controllers and a clean SHARE/ISHARE line.
Average-current mode
Best uniformity; stricter compensation and layout discipline.
ORing-only (no share)
Redundancy/hold-up only; currents may be uneven.
Cable/plane ΔR < 5–10% of droop slope target.
Prefer same series & compensation style; anti-alias RC/blanking/ILIM matched within ±5%.
Interleaving & Beat-Avoidance
Set phases → tune fc/fsw → enable spread-spectrum if needed. Goal: cancel ripple and suppress beat tones.
- 2-way: 0° / 180°
- 3-way: 0° / 120° / 240°
- 4-way: 0° / 90° / 180° / 270°
- 6-way: every 60°
Phases → fc/fsw → spread-spectrum.
- Keep share-loop BW ≪ voltage-loop BW
- Mixed parts: sync a leader clock
- Map input RMS & output ripple per N
Sensing & Routing
Use Kelvin shunts to an AGND star, match anti-alias RC (±5%), add CM choke for long harness, and pick up remote sense after ORing near the load.
- Kelvin both sides of shunts; tight differential pair
- AGND star at controller; single tie to PGND
- Anti-alias RC matched within ±5% across rails
- DCR sense: RC match to L/DCR; calibrate warm
- Long cables: CM choke + symmetric pair routing
- Remote sense after ORing, at load pads (10–100 Ω + 1–10 nF)
- No sense traces near/under SW polygons
- No AGND stubs that carry switching current
- No mismatched RC or ILIM filters across rails
Anti-alias RC & ILIM filters matched within ±5% across rails.
Pick up after ORing near the load; add 10–100 Ω + 1–10 nF.
Control/Compensation When Paralleling
Keep the share loop well below the voltage loop, align poles/zeros with the sensing law, split gate-R, unify blanking/ILIM, and synchronize soft-start & PG.
- fshare ≈ 0.1–0.2 × fc
- Voltage & share loops: GM ≥ 10 dB, PM ≥ 45–60°
- Droop: add zero near droop pole; set DC gain for target slope
- Active share bus: low-noise sum; small C on SHARE; limit bus length
- Average-current: match inner PI; identical slope comp/sense filters
- Split gate-R (Ron/Roff) to balance ringing
- Blanking/ILIM filters matched within ±5%
- Soft-start ramps aligned; PG/RESET orchestrated
fshare = 0.1–0.2 × fc; GM ≥ 10 dB; PM ≥ 45–60°.
Match PI/current-loop type, slope comp, ILIM/blanking & anti-alias RC across rails (±5%).
Thermal Balance & Layout
Keep copper, paths, inductor placement, and airflow symmetrical. If rail-to-rail ΔT > 10 °C, derate or rotate phases/mastership. Route the lowest-impedance thermal path to sinks; don’t let one phase “eat the wind.”
- Mirror copper area & via density; match path lengths
- Place inductors symmetrically; avoid wall-side recirculation
- Shroud/duct to distribute airflow across phases
- Enable scheduled phase/master rotation to spread heat
- 30–60 min soak, worst-case load → ΔT < 10 °C
- A/B airflow (with/without shroud), record hot-spot map
- Before/after rotation: compare ΔT and share skew
If rail-to-rail ΔT > 10 °C at soak → derate or enable phase/master rotation.
Mirror copper, path length, inductor location, and via density; distribute airflow.
Fault Bypass & Redundancy
Use back-to-back ideal-diode/ORing FETs, independent OCP/UVP/OTP per rail, and a PG/FAULT bus. Size bypass SOA for Ifault × tblank; set reverse-current thresholds so good rails stay up when one fails.
- Back-to-back ORing FETs block reverse conduction
- Per-rail OCP/UVP/OTP; same blanking/filter (±5%)
- PG/FAULT bus: wire-OR/open-drain; prioritized
- Bypass SOA ≥ worst-case Ifault, tblank
- Cable events: RC/TVS; debounce FAULT; open-wire sense
- One rail UV/OTP → others hold Vout
- Output short → fast OCP & coordinated retry
- Cable pull → no backfeed; clean disconnect
- Thermal shutdown → others derate within limits
Confirm SOA for Ifault during tblank; set reverse-current limit to prevent backfeed.
Per-rail OCP/UVP/OTP; matched blanking/filters (±5%); clean PG/FAULT prioritization.
Application Scenarios
Parallel rails enable higher current, lower ripple, graceful fail-over, and thermal sharing across diverse systems.
Multiphase parallel to cut ripple and support large transients; enable per-rail telemetry & skew logs.
Chassis airflow zoning; thermal balance; fail-over using ideal-diode ORing.
Two modules in parallel + ORing; survives hot-plug & connector jitter.
Long cables; use droop + Kelvin sense to neutralize line-loss mismatch.
Average-current mode + thermal splitting to avoid single-rail overheating.
Share skew ≤ 5%; ΔT < 10 °C; zero backfeed on fail-over.
Remote sense after ORing; cable/plane ΔR < 5–10% of droop slope.
Validation Playbook
Validate static share, dynamic settling, thermal ΔT, and fault ride-through. Acceptance: skew ≤ 5%, ΔT < 10 °C, no backfeed, no beat-tones.
0→100% sweep; record Ii & skew at each point; ≤ 5% at rated load.
Load steps; observe share-bus waveform & min/max latches; no hunting or beat tones.
30 min soak IR map; ΔT < 10 °C; rotate phases if needed.
Single-rail drop/short/hot-unplug; ORing transfer with zero backfeed.
CSV: load point, Ii, skew, Vout, share-bus peak, latch counts. Plots: skew vs load, ΔT histogram, Vout during faults.
Skew ≤ 5%; ΔT < 10 °C; no backfeed; settle < 2–3× τshare.
Mini IC-Selection Pointers
Parallel/share controllers, ideal-diode/ORing, and telemetry parts you can actually buy. Focus: SHARE/ISHARE, interleaving, telemetry/PMBus, gate-slew, blanking, ILIM filter, remote sense.
UCC29002 / UCC39002 — Analog load-share controller
Fast way to add current sharing across identical rails; minimal BOM.
TPS40140 — Dual synchronous buck controller
Simple two-phase/dual-rail parallel with consistent compensation.
TPS53667 — PMBus multiphase VR controller
FPGA/ASIC >60 A core rails with tight skew control and logging.
LM74700-Q1 / LM74800-Q1 — Ideal-diode / reverse-block
Automotive hot-plug & redundancy; keep good rails from backfeeding.
TPS25982 / TPS25961 — eFuse
Clean fault isolation per rail; pairs well with parallel controllers.
INA226 / INA228 — Shunt power monitors
Per-rail current logs to prove ≤5% skew across load range.
PM6686 / PM6688A — Multiphase VR controllers
Good fit for VRM assist / NVMe back-up rails inside airflow zones.
STEF12 / STEF05 — eFuse
Rail-level isolation; pair with ideal-diode or share controllers.
TSC2011 / TSC2020 — High-side current sense
Accurate per-rail I measurement without saturating on transients.
ISL68137 / ISL69138 — Digital multiphase VR
Tight dynamic match; software-tunable compensation per rail.
ISL6144A / ISL6145A — Ideal-diode / ORing
Fail-over without backfeed; cable pull tolerance.
ISL28023 / ISL28022 — Digital power monitors
Close loop between current, temperature and share control.
NCP81233 / NCP81239 — Multiphase buck controllers
Server/accelerator auxiliaries or parallel POLs.
NCP45520 / NCP45491 — eFuse / load-switch
Per-rail protection building block ahead of ORing.
NIS5021 — eFuse
Industrial 24 V front-ends and long harness lines.
MCP19124 / MCP19125 — Hybrid analog-PWM + MCU
Custom share laws & sequencing in space-constrained designs.
MIC24045 — Digital regulator (SuperSwitcher II)
Compact POLs that can be ganged for higher current.
MIC95410 / MIC94070 — High-side ideal-diode / switch
Lightweight bypass paths and fail-over switches.
PF8100 / PF8200 / PF5030 — System PMICs
SoC power trees with coordinated sequencing and supervision.
MC34VR500 family — Application PMIC
Use as supervisory/host PMIC in mixed parallel architectures.
MLX91220 / MLX91221 / MLX91230 — Hall current sensors
When shunts are impractical or you need galvanic isolation.
- Precise dynamic sharing → Digital multiphase (TI TPS53xxx, Renesas ISL68xxx, onsemi NCP8123x, Microchip MCP1912x)
- Simple parallel add-on → TI UCC29002 / UCC39002 (ISHARE bus)
- Fail-over & hot-plug → Ideal-diode/ORing (TI LM74700/LM74800; Renesas ISL6144A/6145A; ST STEFxx; onsemi NCP45520/NIS5021)
- Trust but verify → Telemetry (TI INA226/INA228; Renesas ISL28023; Melexis MLX9123x)
Frequently Asked Questions
Droop vs active share — when does cable ΔR break balance?
Cable or plane resistance upsets droop sharing when its ΔR exceeds about 5–10% of the designed droop-equivalent slope at the operating current. Keep sense Kelvin, pick up remote sense at the load, and, if needed, raise intentional droop slightly so ΔR is a small perturbation, not the dominant term.
Can rails with different fsw mix stably? Who is the reference phase?
Yes, if you first place phases to avoid near-harmonics, then set voltage-loop crossover and finally tune the share loop. Choose a timing or telemetry master (reference rail) so transient tracking is deterministic. If beat-tones appear, adjust phases or fc before enabling any spread-spectrum feature.
Average-current mode near valley current-limit boundaries?
Valley limiting biases the inner loop; the average-current controller must include matched slope compensation and ILIM filters across rails. Keep share-loop bandwidth at ~0.1–0.2× the voltage-loop crossover, and verify no integrator wind-up when the limiter engages. Check small-signal gain/phase with limiter just active.
Why did beat-tones appear after adding a second rail? How to coordinate phase and fc?
New ripple vectors can land near existing harmonics. Set interleave phases first (e.g., 0/180°, 0/120/240°), then move voltage-loop crossover away from those humps, and place zeros accordingly. Enable spread-spectrum last. Recheck share-loop stability; it should remain a decade below voltage crossover to avoid ping-pong.
Remote sense and ORing — which side should sense live on?
Pick up the remote-sense pair after the ORing elements, directly at the load pads, so regulation ignores diode/FET drops and cable wiggle. Insert a small series resistor (10–100 Ω) plus a small capacitor (1–10 nF) at the controller to prevent noise pickup and oscillation on long runs.
Kelvin routing crosses strong noise and spams min/max latches — how to suppress?
Increase spacing or shielding from SW polygons, keep the pair tightly coupled, and match anti-alias RC within ±5% across rails. Add a small capacitor on the SHARE node or use digital deglitch/windowing on telemetry. Relocate the trace exit so it never passes under the switch node or boot loop.
At what ΔT should we derate or rotate phases?
After a 30–60 minute thermal soak at worst-case load, if rail-to-rail ΔT exceeds 10 °C, reduce current or enable scheduled phase/master rotation. Correlate ΔT with share skew; a rising ΔT often predicts drift. Ensure airflow is balanced and inductors are mirrored before relying solely on rotation.
One rail shuts down or shorts — how do ORing parts avoid backfeed and UV glitches?
Use back-to-back ideal-diode FETs sized for the fault plateau and blanking window. Set reverse-current threshold below worst backfeed. Coordinate PG/FAULT so surviving rails remain valid and no UV pulse trips downstream. Validate with asymmetrical ramps, hot-unplug, and node shorts; Vout should remain within tolerance.
How to calibrate DCR-sense temperature drift to keep share accuracy?
Match RC to the inductor L/DCR, warm-soak, then zero the offset at several current points. Store per-rail temperature coefficients and apply a small correction versus board temperature. Re-verify slope at high current where copper heating dominates. Keep sense capacitor and resistor tolerances tight across all parallel rails.
Share-loop bandwidth versus voltage-loop crossover — what ratio is safe?
Set the share-loop bandwidth at approximately 0.1–0.2 times the voltage-loop crossover so they remain decoupled. Confirm gain margin ≥ 10 dB and phase margin ≥ 45–60°. Use identical inner-loop types and slope compensation across rails so the share controller does not fight mismatched current dynamics.
Interleaving rules for 2/3/4/6 rails — any caveats with spread-spectrum?
Use 0/180° for two, 0/120/240° for three, 0/90/180/270° for four, and 60° steps for six. Place phases first, adjust voltage-loop crossover next, then consider spread-spectrum if needed. Verify that dither does not cross-share-loop bandwidth or create beat-tones with sensitive downstream ADC or clock domains.
Soft-start alignment and PG/RESET — how to avoid inrush skew grabbing the load?
Match soft-start ramps and blanking/ILIM filters across rails so no unit reaches regulation much earlier. Sequence PG/RESET so downstream loads wait for all rails to be ready. If necessary, slow the fastest rail slightly with gate-slew or ramp timing to prevent it from monopolizing early current.
What noise and aliasing limits apply to ADC telemetry of share measurements?
Choose anti-alias time constants at least five to ten times the ADC sample period and place RC close to the controller. Use shielded or tightly coupled differential pairs and avoid routes under the switch or boot nodes. Verify min/max latches with injected noise so windows and deglitching are adequate.
Reverse-current limit — how should it be set and verified?
Set the reverse-current threshold below the worst predicted backfeed during cable pulls, asymmetrical ramps, or a rail collapse. Validate with deliberate Vout mismatches and hot-unplug while watching the FAULT/PG lines. Scope current through the back-to-back FETs; the reverse pulse should clamp cleanly without chatter.
