Synchronous Buck Controller ICs | HS/LS Drive & Current-Mode Control
This page delivers a practical, vendor-neutral guide to external-MOSFET synchronous buck controllers. We concentrate on HS/LS gate driving, peak vs valley current-mode control, and reliable protection (hiccup/latch/auto-retry). You’ll size the inductor for target ripple, select MOSFETs by RDS(on) vs Qg, and tune compensation for stable bandwidth—then lock EMI/layout details (hot loop, bootstrap, snubber). Use the brand matrix, application cards, and FAQ to turn specs into a validated design path.
Introduction & Architecture Fundamentals
A synchronous buck controller uses external high-side (HS) and low-side (LS) MOSFETs to step down voltage with high efficiency. Compared with monolithic buck regulators, the external power stage offers freedom to scale MOSFET RDS(on), package, and inductor to meet thermal limits, transient targets, and cost goals in demanding automotive, telecom, and industrial rails.
- Power & thermal headroom — select lower RDS(on)/larger packages or parallel FETs for higher current and cooler operation.
- Control flexibility — wider options for compensation, frequency, current limit, soft-start, and fault behavior.
- Scalable BOM — tune MOSFET/inductor choices to application current and efficiency targets without changing the controller IC.
Automotive ECUs
Wide VIN, cold-crank, surge survival; thermal derating and PG/RESET timing. AEC-Q100 devices preferred.
Telecom Power Modules
48→12 V PoL with strict transient specs; room for parallel FETs and higher switching frequency.
Industrial 24 V Systems
EMI compliance, surge/OV design, robust start-up and fault handling for factory rails.
HS/LS MOSFET Drive Techniques
Gate switching speed is largely bounded by Qgd and driver current. Correct dead-time placement prevents shoot-through while minimizing diode conduction and reverse-recovery loss. Choose the gate-driver voltage to balance conduction vs gate-drive losses and ensure bootstrap/U VLO margins.
- Rule-D1: Use split gate resistors (Rg_on/Rg_off) to tailor turn-on/turn-off independently and reduce dv/dt-induced coupling.
- Rule-D2: Start dead-time from reverse-recovery estimate, then trim on the scope so shoot-through is zero and diode conduction window is minimal.
- Rule-D3: Verify bootstrap ripple and gate UVLO headroom at high duty cycle; add bleed or adjust frequency if needed.
- Rule-D4: For battery systems, avoid excessive VDRIVE; gate losses grow with swing × frequency.
- Rule-D5: Keep gate/sense loops very short; use LS Kelvin source if the controller supports it.
Gate-Driver Voltage Levels
- 10–12 V (Si MOSFET): lower conduction loss; verify abs. max VGS and use proper dead-time.
- 6–8 V (logic-level Si): useful for battery systems to reduce gate-drive loss; check RDS(on) rise.
- Adaptive dead-time: preferred when available; always confirm on scope with Vgs_HS / Vgs_LS / Vsw alignment.
Peak vs Valley Current-Mode Control (CMC)
Peak CMC triggers on the inductor rising current, yielding fast transient response and natural cycle-by-cycle current limiting. Valley CMC triggers on the falling current, improving noise immunity at low duty ratios and high dv/dt layouts. Slope compensation and ripple targets shape stability and subharmonic behavior.
- Peak CMC: Fast load-step control; simple cycle-by-cycle limit. Needs adequate slope compensation when D > 0.5.
- Valley CMC: Better at high Vin→low Vout or noisy boards; naturally mitigates subharmonics at low duty ratios.
- Slope compensation: Tune ramp vs down-slope; aim ΔIL ≈ 20–40%·Iout for a practical transient/EMI trade-off.
- Verification: Observe Vout overshoot/undershoot, duty jitter, and SW ringing; confirm PM 45°–60° via Bode injection.
Copy-Ready Design Rules
- Rule-C1: For peak CMC with D>0.5, start with mcomp ≥ 0.5·mdown and increase if duty jitter remains.
- Rule-C2: Target ΔIL=20–40%·Iout; higher ripple speeds transients, lower ripple eases EMI.
- Rule-C3: Prefer valley CMC at high Vin→low Vout or noisy layouts; keep sense lines differential and short.
- Rule-C4: Measure Vout, Vsw, and Isense simultaneously; tune ramp until subharmonics vanish with PM 45°–60°.
External MOSFET Selection
Balance conduction, switching, and gate-drive losses while meeting thermal limits and EMI goals. Use package-level thermal data and realistic PCB copper to predict hot-case RDS(on)(T). Tune dead-time to reduce diode conduction and reverse-recovery penalties.
Quick Loss Framework
- Conduction: Pcond ≈ Irms2 · RDS(on)(T)
- Switching: Psw ≈ 0.5 · V · I · (tr+tf) · fsw
- Gate drive: Pg ≈ Qg · Vdrive · fsw
Copy-Ready Selection Rules
- Rule-M1: Size RDS(on) from conduction budget at Thot; verify with realistic copper.
- Rule-M2: Limit Qg by Pg=Qg·Vdrive·fsw; if the driver is warm, trade some RDS(on) for lower Qg.
- Rule-M3: Use devices with lower Qrr and calibrate dead-time to curb reverse recovery.
- Rule-M4: Prefer Kelvin-source packages; keep gate/sense loops shortest before adding heatsinks.
Si vs GaN vs SiC (only when directly relevant)
Si: Mainstream, cost-effective, broad selection; watch Qrr in dead-time.
GaN: Low charge, no reverse recovery; requires tight loops, possible Miller clamp/negative turn-off.
SiC: Suits higher voltage/temperature; for this page’s typical mid-voltage buck, only consider in wide-VIN harsh environments.
Inductor Selection & Current Ripple Design
The inductor sets ripple, transient speed, thermal behavior, and EMI. Target a practical ripple window and back-solve L, then verify saturation and AC loss at hot conditions. Choose shielded types near sensitive circuits; open-core only where EMI is tolerant.
- Ripple target: ΔIL ≈ 20–40% · IOUT (15% for low noise, 50% for fast transient).
- Saturation check: IL,pk = IOUT + ΔIL/2; require Isat ≥ 1.2–1.5× IL,pk at hot.
- AC loss & EMI: Rac(f) > Rdc from skin/proximity; higher ΔI raises SW noise and Cout stress.
- Shielding: Use shielded parts near analog/RF; keep SW loop short regardless of type.
Copy-Ready Inductor Rules
- Rule-L1: Start with ΔIL=20–40%·IOUT; use 15% for low-noise rails or 50% for faster transient.
- Rule-L2: Ensure Isat ≥ 1.2–1.5× (IOUT+ΔIL/2) at hot-case.
- Rule-L3: Check Rac/Rdc at fsw; litz or thinner wires help above a few hundred kHz.
- Rule-L4: Prefer shielded parts near analog/RF; always keep SW loop compact.
Control Loop & Compensation
In current-mode buck converters, the inner current loop simplifies the power plant, enabling higher bandwidth with Type-II or Type-III compensation. Place zeros against the plant poles and confirm stability by Bode injection under worst-case VIN/IOUT corners.
- Type-II: Easier tuning; suits moderate bandwidth. Align the zero near the dominant plant pole.
- Type-III: Adds phase for higher crossover; two zeros near the double pole, HF pole before fsw/2.
- CMC stability: Keep fc ≤ 0.2–0.3·fsw; ensure adequate slope comp at high duty.
- Targets: PM 45°–60°, GM ≥ 6 dB, −20 dB/dec roll-off at fc.
Copy-Ready Compensation Rules
- Rule-CMP1: Start with fc ≈ fsw/10; trim for PM 45°–60°.
- Rule-CMP2: Align zeros to plant poles; add an HF pole below fsw/2.
- Rule-CMP3: Keep fc ≤ 0.3·fsw to limit sampling/PWM delay effects.
- Rule-CMP4: Validate at (VINmax, Imin) and (VINmin, Imax); lock values only after both pass.
Protection & Fault Management
Choose an appropriate fault mode for thermal safety and system policy, set short-circuit thresholds with blanking to avoid false trips, and align soft-start, pre-bias behavior, and PG/RESET timing for predictable bring-up.
- Hiccup: Disable after fault → cool down → retry periodically; lowest thermal stress.
- Latch-off: Fault latches until power-cycle/reset; ideal for safety-critical rails.
- Auto-retry: Immediate cyclic re-attempts; fastest self-recovery, watch average dissipation.
Short-Circuit Thresholds & Start-Up
- Thresholds: Set OCP above worst-case transient yet within MOSFET/inductor SOA. Add leading/trailing-edge blanking to ignore spikes.
- Soft-start: Ramp SS to limit inrush/overshoot; tie SS to fault logic so UVP does not false-trigger during ramp.
- Pre-bias: Disable forced LS conduction at start; allow monotonic rise without draining existing Vout.
Copy-Ready Protection Rules
- Rule-P1: Pick hiccup for thermal safety, latch-off for safety-critical, auto-retry for availability.
- Rule-P2: OCP above transient but within SOA; add edge-blanking to suppress false triggers.
- Rule-P3: Soft-start time from inrush limits; enable pre-bias safe start to avoid discharge.
- Rule-P4: PG thresholds and debounce aligned to regulation window; verify timing at VIN corners.
EMI & Layout Guidelines
Minimize the switching hot loop, keep the bootstrap loop compact, and add RC snubbers only after layout is optimized. Validate by near-field probing and pre-compliance scans around the switching frequency and harmonics.
- Hot loop: VIN → HS → SW → Cout → GND → VIN must be the smallest triangle with tight ceramics.
- Bootstrap: Place BOOT cap/diode next to HS source and driver; verify Vboot and gate UVLO at high duty.
- Snubber: Tune RC for critical damping of SW ringing; start small C (tens–hundreds pF) and refine on scope/spectrum.
Copy-Ready EMI/Layout Rules
- Rule-E1: Shrink the VIN–HS–SW–Cout loop; place input ceramics within millimeters.
- Rule-E2: Keep BOOT cap/diode adjacent to HS source/driver; verify Vboot at high duty.
- Rule-E3: Add RC snubber only after layout optimization; tune for near-critical damping.
- Rule-E4: Separate gate/sense from SW copper; join power/signal grounds at a single star point.
IC Selection: Brand Comparison (External-MOSFET Synchronous Buck Controllers)
This matrix lists representative synchronous buck controllers that drive external HS/LS MOSFETs. Series that are monolithic regulators (integrated power FET) are flagged “Out of scope (see Monolithic page)” to avoid cross-page duplication.
Tip: Table scrolls horizontally on small screens. First column stays visible.
| Brand / Device (Family) | VIN Range | Gate Driver | Control Mode | Sense Method | fSW / Sync | Min On/Off | Protections | SS / Pre-bias / PG | AEC-Q / Notes |
|---|---|---|---|---|---|---|---|---|---|
| TI LM514x (e.g., LM5141/LM5143) | Up to ~65V (family-dep.) | Dual N-MOS, HV bias, ext. BOOT | Peak CMC (ramp comp.) | CS amp / RDS(on) options (fam.) | Few 100 kHz; Ext Sync: Yes | Short min-on for high ratio (fam.) | UVLO/OVP/OCP, hiccup/latch (fam.) | SS pin, pre-bias safe start, PG | Q-grades available; Wide-VIN telecom/auto |
| TI TPS54x (e.g., TPS54x38) | Monolithic buck regulator (integrated FET) — Out of scope for this page. See the Monolithic Buck Regulator sibling page. | ||||||||
| ST L6983 | Monolithic synchronous buck (integrated FET) — Out of scope here. Covered in the Monolithic subpage. | ||||||||
| ST (External-MOS Controllers) | Wide-VIN families (various) | Dual N-MOS; adaptive dead-time (fam.) | Peak/Valley CMC per device | CS amp / Rdson sensing (fam.) | Sync options vary | Spec-dependent | Hiccup/Latch/Auto-retry (fam.) | SS/PG typical | AEC-Q options |
| Renesas ISL8117(A) | Wide-VIN telecom/auto range | Dual N-MOS, robust drivers | Valley current modulation (family) | CS amp / Rdson (device-dep.) | Ext Sync: Yes (fam.) | Short min-on for high step-down (fam.) | UVLO/OVP/OCP, hiccup options | SS pin, PG typical | Industrial/auto ready |
| onsemi NCV8856A / NCP1034 | Up to ~100V (NCP1034) | Dual N-MOS; ~1.5 A drv (auto variant) | PWM CMC; ext sync (NCP1034) | CS amp / Rdson (device-dep.) | 25–500 kHz; Sync: Yes (NCP1034) | Spec-dependent | UVLO/OVP/OCP; hiccup (NCP1034) | SS/PG typical | AEC-Q versions (NCV) |
| Microchip MIC2128 | 4.5–75V (controller) | Dual N-MOS; adaptive on-time ctrl | Constant-frequency / AOT (device) | CS amp (device) | 270–800 kHz; Sync: (see DS) | Spec-dependent | UVLO/OVP/OCP; SS pin | SS/PG typical | Wide-VIN industrial |
| NXP VR5510 / FS84/FS85 (VPRE) | Up to ~60V (12/24V systems) | VPRE: ext. MOSFET controller | Peak CMC (external FET) | Current sense per device | Programmable; Sync (PMIC-dep.) | Spec-dependent | UV/OV/OCP; safety hooks (ASIL) | Sequencing / PG integrated | AEC-Q100; PMIC with ext-FET buck |
Copy-Ready Selection Rules
- Rule-S1: Match min on/off to duty extremes at VINmax/VOUTmin.
- Rule-S2: Constrain gate-loss by Qg·Vdrive·fsw; size RDS(on) from conduction budget.
- Rule-S3: Pick Hiccup/Latch/Auto-retry per safety/thermal policy; add edge blanking.
- Rule-S4: Confirm slope-comp & dead-time at target ΔIL; verify across VIN/IOUT corners.
Use Cases & Application Notes
Automotive (48→12 V, 12→5 V)
Constraints
- Cold-crank/load-dump, surge survival; thermal/EMI; sequencing & ASIL hooks.
Design slice
- Wide-VIN controller; verify min on-time for high ratio.
- 10–12 V gate drive; trim dead-time for minimal diode window.
- ΔIL 20–30%; Isat ≥ 1.5× hot-case.
- Hiccup preferred; PG debounce; SS > upstream delay.
- Low RθJC packages + copper spreading.
Pitfalls
- VBOOT ripple→gate UVLO; UVP false during SS; RDS(on)(T) drift vs OCP.
Server / FPGA Rails
Constraints
- Large di/dt load steps, tight droop & ripple limits.
Design slice
- ΔIL 35–40% for speed; Type-III compensation.
- Valley CMC for low duty/high dv/dt robustness.
- Split Rg(on/off); optional Miller clamp; RC snubber on SW.
- OCP budget & parallel FET current sharing.
Pitfalls
- Subharmonics from noisy sense; narrow PG window; driver heating from gate loss.
CMC · Compensation · MOSFET
Industrial 24 V (Wide Input)
Constraints
- EN/IEC surge, conducted/radiated limits; 24 V ± tolerance or wider.
Design slice
- Wide-VIN controller; strong blanking & UV/OV windows.
- ΔIL 20–30%; shielded inductor; tight Chot triangle.
- Snubber: start small C then tune R for damping.
- Latch-off allowed for manual recovery; PG to downstream logic.
Pitfalls
- Chot too far; sense crossing SW copper; ESR zero unmanaged.
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FAQs: Synchronous Buck Controller (External MOSFET)
Answers focus on HS/LS MOSFET drive, peak/valley CMC, protection, inductor ripple, EMI/layout, and IC selection. Each item is concise and actionable for practical design.
1) Why choose an external-MOSFET synchronous buck controller over a monolithic regulator?
External-MOS controllers let you scale MOSFET RDS(on), package, and inductor for higher current, lower thermal rise, and better transient tuning. You can set dead-time, slope compensation, and current limits more freely, improving robustness across wide VIN ranges. See Introduction and MOSFET Selection.
2) How do I set dead-time to avoid shoot-through but minimize diode conduction?
Start with controller’s adaptive dead-time if available, then trim using scope traces of Vgs_HS, Vgs_LS, and Vsw. Increase Rg(off) relative to Rg(on) to curb dv/dt-induced turn-on. Target zero overlap and the shortest observable diode conduction window. See HS/LS MOSFET Drive.
3) When should I prefer valley current-mode over peak current-mode control?
Valley CMC is favored at low duty ratios and high dv/dt boards, where noise immunity and reduced subharmonic risk matter. It can be more stable for high VIN→low VOUT designs. Peak CMC still excels for fast cycle-by-cycle limiting. Match to layout noise and duty extremes. See CMC.
4) How much inductor ripple (ΔIL) should I target?
Use ΔIL ≈ 20–40%·IOUT as a practical starting point. Lower ripple (≈15%) reduces EMI and output ripple but increases L size and slows transients. Higher ripple (≈50%) speeds response and may shrink L, but raises switch-node noise and peak current. See Inductor Selection.
5) What’s a good starting point for slope compensation above 50% duty?
Begin with mcomp ≈ 0.5–1.0 × mdown for peak CMC. Increase if you observe duty jitter or subharmonics near crossover. Tune with simultaneous Vout, Vsw, and Isense captures and verify phase margin stays 45–60°. See CMC and Compensation.
6) How do I balance RDS(on) versus Qg/Qgd when picking MOSFETs?
Size RDS(on) from conduction budget at hot conditions, then constrain gate loss by Pg=Qg·Vdrive·fsw. If the driver runs warm, accept slightly higher RDS(on) for lower Qg. Always re-tune dead-time and snubber after swapping parts. See MOSFET Selection.
7) What scope signatures indicate marginal loop stability?
Look for duty jitter, repetitive bursty pulses near load steps, prolonged settling, or peaking in Vout. In frequency response, a shallow gain slope at crossover and phase dipping below ~45° warn of risk. Re-place zeros/poles and check ESR zero alignment. See Compensation.
8) Which fault policy fits batteries vs safety-critical rails?
Choose hiccup for battery or thermally constrained systems—average power stays low during faults. Latch-off suits safety-critical rails requiring manual recovery. Auto-retry restores availability fastest but raises thermal stress during persistent faults. Verify blanking and OCP trip levels. See Protection.
9) How do I guarantee pre-bias startup without discharging an existing output?
Use the controller’s pre-bias safe start: prevent forced LS conduction during ramp and keep the COMP/SS slope monotonic. Confirm PG asserts only after regulation window is met. Probe Vout, Vgs_HS/LS, and inductor current to verify there’s no sink. See Protection.
10) Where must input ceramics (Chot) sit to minimize the switching hot loop?
Place multiple MLCCs directly between VIN and power ground near HS/LS FETs, forming the smallest triangle with HS, SW, and Cout. Keep gate and sense paths away from SW copper. This reduces di/dt loop area, spikes, and EMI. See EMI & Layout.
11) How do I tune an RC snubber without excessive loss?
After minimizing layout, start with a small C (tens–hundreds of pF) and moderate R. Observe Vsw ringing amplitude and frequency; increase C or adjust R toward critical damping. Confirm temperature rise and spectral peaks near harmonics drop acceptably. See EMI & Layout.
12) What limits very high step-down ratios in synchronous bucks?
Minimum on-time, sense noise, and bootstrap headroom constrain extreme ratios. Ensure min on/off times cover the duty extremes, verify adequate slope compensation, and check VBOOT ripple so gate UVLO never triggers at high duty. Consider higher switching frequency or two-stage conversion if needed. See Gate Drive.
13) Which lab corners should I always verify before release?
Test (VINmax, Imin) and (VINmin, Imax) for stability, transient, and thermal limits. Sweep temperature, component tolerances, and worst-case ESR. Confirm PG timing, OCP/UVP behavior, and snubber effectiveness with spectrum checks. See Compensation and Protection.
14) How do I shortlist controller ICs across brands efficiently?
Filter by VIN range, min on/off, gate-driver strength/voltage, CMC flavor, protections, and sync capability. Cross-check dead-time control, SS/pre-bias, and PG implementation. Use a normalized matrix to compare only external-FET controllers. See IC Selection and submit your BOM below.
