When VHYS is smaller than the combined disturbance, the input can re-cross the active threshold and create extra edges. When VHYS is excessively large, effective switching points shift and can reduce noise margin in low-voltage systems.

• Purpose: reduce narrow spikes and reduce time spent in the threshold zone so VHYS can enforce one transition.
• Main risk: too much C makes the edge slow; slow edges can cause missed pulses and phase distortion at f_max.
• Rise-time budget: treat the edge as a simple RC limit (especially for open-drain with pull-up):
  t_r ≈ 2.2 · R_pullup · (C_cable + C_in + C_protect + C_rc)

  Keep t_r comfortably below t_{real_min} so legitimate pulses remain distinct at f_max.
• Layout rule: match A and B conditioning (same R/C class and placement) to preserve phase relationship.

• Blanking logic: after a valid edge, ignore re-triggers for t_blank.
• First constraint: t_blank ≥ t_{noise_max} (must cover the bounce/glitch window).
• Second constraint: t_blank < T_min (must not block real pulses at maximum speed).
• Counter note: fixed pulse-width stretching can distort A/B duty; use blanking-first behavior when phase integrity matters.

• Structure: Schmitt edge shaping → two-flop synchronizer → N-sample qualify (or majority).
• Delay budget: detection delay grows with N and clock period:
  t_detect ≈ (N · T_clk) + t_sync

  Ensure t_detect < t_{delay_max} and T_clk is short enough to “see” t_{real_min}.
• Counter note: qualification must happen before the counting edge is consumed (avoid filtering only after counting).

• Connector side: TVS to GND (primary surge energy path).
• Limit current: series-R (controls clamp/injection current and damps ringing).
• Rail clamps: diode clamp to rails (protects the receiver input, but can inject into VDD/GND).
• Optional RC: small RC for EFT/ringing, sized using the rise-time budget.
• Receiver: Schmitt input / receiver stage (enforces clean edges at the counter interface).

Use the receiver datasheet fields such as maximum injection current or input clamp current as a hard constraint. Series resistance is the primary control knob.

• Total capacitance: C_total = C_cable + C_tvs + C_in + C_rc.
• OD edges: t_r ≈ 2.2 · R_pullup · C_total (dominant first-order limit).
• Constraint: keep t_r well below t_{real_min} so pulses remain distinct at f_max.

• Rule of thumb: V_shift ≈ I_leak · R_source. High impedance nodes magnify leakage effects.
• Temperature note: leakage typically increases with temperature, making thresholds appear “floaty.”
• Mitigation: lower impedance, pick low-leakage clamps, and keep clamp current paths short and controlled.

• Low-frequency dominated: avoid ground loops; single-end shield bonding reduces 50/60 Hz and large-current return coupling.
• High-frequency dominated: give ESD/EFT a short, wide return path; chassis bonding at the connector is the primary mechanism.
• Practical goal: shield currents should return through chassis, while signal return stays on PCB ground.

• TVS: place near the connector to divert surge/ESD energy before it enters long PCB traces.
• CMC: place near the connector to block common-mode current at the injection point (most effective where current first enters).
• RC: place near the receiver when the purpose is to prevent ringing/glitches from entering the threshold zone.
• Series-R: position to control clamp/injection current and damp cable/connector ringing without breaking rise-time budget.

• Upgrade to differential receive: common-mode noise is visible, ground reference is not stable, or phase integrity must be kept at high speed.
• Upgrade to isolation: strong ground potential differences or fast common-mode transients exist and return paths cannot be controlled.
• Design intent: differential reduces common-mode sensitivity; isolation breaks the disturbance return path altogether.

• ESD: ultra-fast current; connector return path and TVS loop quality dominate.
• EFT: burst-like coupling; small ringing/glitches can repeatedly cross thresholds unless shaped.
• Surge: energy-driven; clamp current and supply/ground lifting can corrupt thresholds and create false edges.

• Edge order: direction is decided by which channel leads (A then B, or B then A).
• Relative delay: anything that changes A vs B delay changes the edge order risk.
• Z importance: Z is often narrower and more critical; missed or false Z edges have outsized impact.

• Asymmetric paths: A/B use different protection/RC/debounce → make A/B fully matched.
• Mismatched delay: RC / one-shot / N-sample adds unequal delay → budget and match A/B delay.
• Asynchronous sampling: no synchronizer into the clock domain → synchronize before counting.

• Matched path: same conditioning chain for A and B (same parts, same placement class).
• Matched delay: identical debounce windows and filtering parameters for A and B.
• Sync before count: synchronize A/B decisions into the counting clock domain before edge consumption.
• Z strategy: Z may use a different window, but the delay must remain deterministic.

• Miss risk: overly strong filtering can remove a legitimate narrow Z pulse.
• False risk: EMI spikes can create a fake Z edge; windowing reduces one-off triggers.
• Rule: Z filtering can differ, but A/B path symmetry should remain strict.

• Metastability: when an edge arrives near the sampling instant, the first flip-flop can resolve late.
• Count impact: late resolution can look like a delayed edge (miss) or a short internal glitch (extra edge).
• Quadrature impact: unequal sampling delay on A vs B can change the perceived edge order.
• Primary fix: use a 2-FF synchronizer before counting or qualification logic.

Express maximum speed as a pulse-width and latency budget. A pulse must remain valid long enough to survive debounce/qualification and synchronization, with margin.

• t_pulse_min: shortest legitimate high/low time at maximum speed.
• t_debounce: RC/one-shot/N-sample qualification time.
• t_sync: 2-FF synchronizer and downstream sampling latency.

• Count only: feed synchronized edges into a hardware counter.
• Speed measurement: use timer capture timestamps (avoid interrupt-induced jitter).
• Highest robustness: synchronize first, then qualify/window, then count/capture.

• Long ground lead: adds loop area and can create/boost ringing.
• Probe capacitance: slows edges on high-impedance nodes (open-drain pull-ups are sensitive).
• Bandwidth limits: filtering can hide narrow glitches that still cross thresholds.
• Wrong reference point: ground bounce can be misread as signal glitches.

• Use width/runt/glitch triggering: target narrow pulses that cross the input threshold.
• Use persistence/sequence capture: turn rare events into observable statistics.
• Change one variable at a time: shield bond, CMC position, RC value, or series-R placement.

• Preferred: use compliant ESD/EFT/surge equipment in a controlled environment.
• Goal: reproduce the same failure signature (false edges, direction errors, missed counts).
• Mapping: verify whether the disturbance enters at the connector, after the clamp, or at the Schmitt output.

• Bounce/slow ramp: repeated threshold crossings near VTH → increase VHYS or adjust debounce.
• EMI injection: disturbances appear at the connector and follow cable movement → fix shielding/CMC/entry protection.
• Clamp injection: clamp node or rails lift during events → limit injection current and control return paths.
• Ground bounce: reference moves with load switching → fix grounding/return continuity and reduce shared impedance.

• Zoning: Connector → Protection island → Shaping → MCU/FPGA (keep protection at the entry).
• Return paths: clamp currents return on short, wide loops; avoid shared impedance with input reference.
• A/B symmetry: mirror routing and components; keep parasitics and delays matched.
• Short sensitive nodes: keep Schmitt inputs compact; avoid crossing plane splits.

• Max speed sweep: verify no missed counts and no direction errors at the highest edge rate.
• Minimum pulse-width: confirm t_{pulse_min} survives debounce + sync latency.
• ESD/EFT functional: post-event counting still meets the max-speed criterion.
• Thermal/leakage boundary: verify thresholds and false-trigger rate across temperature and humidity extremes.

• VHYS margin: worst-case noise + ground bounce stays below the hysteresis window.
• Timing margin: debounce + sync leave margin against the shortest legitimate pulse.
• Injection margin: clamp currents and return paths do not lift rails/references into the threshold zone.
• Repeatability: failures are not probability-driven under cable movement and nearby switching loads.

• Use when: open-drain outputs with moderate speed and a cost-focused chain.
• Trade-off: pull-up power vs rise-time budget (slow edges must not linger near thresholds).
• Rule: confirm t_{pulse_min} survives RC and debounce/qualification latency.

• Use when: 24V wiring and strong IEC stress are expected.
• Priority: control clamp injection current with series resistance and intentional return paths.
• Rule: divider impedance must not allow leakage to shift thresholds across temperature/humidity.

• Use when: common-mode noise and unstable ground references dominate.
• Rule: keep A/B paths matched and synchronize before counting.
• Boundary: receiver/isolation device selection details belong on dedicated sibling pages.

• Use when: Z is narrow or critical and false Z triggers are costly.
• Rule: A/B must stay symmetric; Z may differ but timing must remain deterministic.
• Check: filtering must not remove legitimate Z pulses at maximum speed.

• Field: VTH+ / VTH− (min/max), VHYS (min/max).
• Risk: double counts from repeated threshold crossings; missed pulses if thresholds shift too far.
• Request: min/max across VDD and temperature, with input edge condition (slow ramp / source impedance).

• Field: input leakage / bias current (worst-case at high temperature).
• Risk: divider and pull-up networks shift thresholds; humidity/contamination amplifies drift and false triggers.
• Request: worst-case leakage across temperature and input voltage; note any post-ESD parameter shift.

• Field: max clamp current / injection current (to VDD and to GND), absolute max input rules.
• Risk: rail lift and reference bounce create fake edges; post-event misbehavior from overstress.
• Request: allowable injection current with conditions (pulse width, repetition, temperature) and recommended protection topology.

• Field: tPD with specified overdrive; worst-case delay under small overdrive and slow edges.
• Risk: A/B unequal delay causes wrong direction; excess latency shrinks the no-lost-count timing margin.
• Request: worst-case tPD at small overdrive (mV-level) plus the test conditions (VDD, load, temperature).

• Field: open-drain vs push-pull; drive strength; logic thresholds; 5V tolerant / over-voltage tolerant conditions.
• Risk: OD rise-time budget failure; unintended clamp injection into MCU rails; marginal VIH/VIL at low VDD.
• Request: IO compatibility statement with conditions (VDD=3.3V, input=5V, allowed current and duration).

• Field: ESD rating (HBM/CDM or IEC claims), EFT survivability claims, temperature range, industrial/automotive grade, package.
• Risk: post-event leakage drift; threshold drift across temperature; field-only intermittent failures.
• Request: clarified test standard and conditions; verify whether “IEC” results are system-level or component-level.

Schmitt-trigger buffers / gates

Comparators (for programmable thresholds / external hysteresis)

One-shot / monostable (debounce windows / pulse shaping)

Dedicated debouncer (qualification IC option)

Differential line receiver (block-level long-cable upgrade starting point)

ESD / input protection (entry protection starting points)

1) Under VDD=XX, T=XX…XX, and input edge=XX V/µs (or source impedance=XX), what are VTH+ / VTH− min/max? 2) Is VHYS guaranteed (min/max)? Provide the test conditions (VDD, temperature, input waveform). 3) What is the worst-case input leakage / bias current at T=XX°C across the full input voltage range? Does leakage change after ESD exposure or in high-humidity conditions? 4) What is the allowable input clamp / injection current (to VDD and to GND)? Provide limits with conditions (pulse width, repetition rate, temperature). 5) What is the worst-case propagation delay at small overdrive=XX mV and under slow edges? Provide the overdrive definition and load conditions. 6) Is the input 5V tolerant / over-voltage tolerant when VDD=3.3V? Provide the allowed input voltage, allowable current, and duration limits. 7) For open-drain or push-pull outputs, what are the guaranteed source/sink capabilities and recommended load limits? Provide guidance for pull-up range and maximum capacitance. 8) What ESD ratings are guaranteed (HBM/CDM and any IEC claims)? Clarify whether IEC results are component-level or system-level. 9) What temperature grades are available (-40…85 / -40…105 / -40…125), and which parameters drift the most across temperature? 10) For A/B/Z encoder use, is there any guidance or data on matched delay / symmetry requirements to preserve direction integrity?