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General-Purpose Low-Power Comparator: Practical Guide

General-Purpose Low-Power Comparator: Practical Guide

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Low-power comparators trade speed for battery life—real behavior is set by overdrive, pull-up RC, and leakage on high-impedance thresholds.

This page shows how to design and validate slow-threshold and wake-up trips so they switch once, at the right point, across temperature, humidity, and real wiring—not just on the datasheet bench.

What this page solves (scope + when to use)

This page focuses on general-purpose low-power comparators used for battery thresholds, slow ramps, and wake-up decisions. The goal is to help designs stay low-leakage, low-false-trigger, and predictable in timing when quiescent current targets are in the nA–µA range.

Typical “low-power threshold” scenarios
  • Battery UV/OV, Power-Good, brown-in/brown-out style decisions (especially with large divider resistors).
  • Slow-changing sensor thresholds (NTC, resistive sensors, RC-time ramps) where inputs cross threshold gradually.
  • Energy-harvesting / deep-sleep wake-up chains where the comparator runs while the MCU sleeps.
  • Low-frequency alarms (voltage, temperature, level) that must not chatter under noise and interference.
Low power is not free — four engineering truths
  1. Delay is condition-dependent: small overdrive (a few mV) can push response from µs into ms. Plan timing at the actual overdrive, not a single datasheet headline number.
  2. Threshold accuracy becomes “micro-currents × mega-ohms”: input bias, protection leakage, and board contamination can shift VTH by mV–10s of mV when dividers are in the MΩ range.
  3. Output edges are often dominated by external networks: open-drain + Rpull + Cload decides rise-time, noise immunity, and even effective power in wake-up paths.
  4. Start-up / sleep behavior matters: nano-power parts may require stabilization time or recover slowly after deep sleep, which directly affects “first decision” correctness.
Scope boundary (to avoid topic overlap)
  • Need ns delay / edge jitter / latching? Use the High-Speed / Latched Comparator topic page.
  • Need ultra-low offset/drift for absolute thresholds? Use the Precision Comparator topic page.
  • Need clocked dynamic front-ends (StrongARM-type)? Use the Regenerative Comparator topic page.
  • Need window / zero-cross / one-shot functions? Use the dedicated Window / Zero-Cross / Timer pages.
What a reader should be able to do after this page
  • Pick a low-power comparator family for battery/wake thresholds without underestimating delay at small overdrive.
  • Budget threshold error when divider resistors are large (bias + leakage + tolerance + temperature).
  • Select output style and pull-up to meet both rise-time and power goals.
  • Define a practical validation plan for Iq, threshold stability, and “no-chatter” behavior on slow ramps.
Low-power threshold application map Block diagram showing battery or sensor feeding divider and filter into a low-power comparator, then through a pull-up to MCU wake/IRQ. Corner tags highlight Iq, delay vs overdrive, leakage-limited threshold, and pull-up RC. Battery / Sensor Slow threshold Divider + RC Filter Low-Power Comparator nA–µA Iq + − Pull-up → MCU Wake/IRQ Iq budget Delay vs Overdrive Leakage-limited VTH Pull-up RC edge

Architecture cheatsheet: why low Iq costs speed

Low-power comparators reach nA–µA quiescent current by reducing continuous analog bias. That choice changes what “fast” and “accurate” mean in practice: delay becomes strongly overdrive-dependent, small leakage currents matter, and external loading can dominate output edges.

Common ways low Iq is achieved (and what each implies)
  • Reduced continuous bias (weak bias): lower input-stage gm and bandwidth, making small-overdrive events slow.
  • Dynamic / duty-cycled bias: average Iq drops, but start-up and recovery time become system variables.
  • Weak output drive: output transitions depend on pull-up and load capacitance, not only on internal switching.
  • Optional offset trimming / auto-zero (part-dependent): can improve threshold repeatability, but may add timing constraints; treat as a feature with conditions, not a guarantee.
Direct consequences that shape real designs
  • Propagation delay scales with overdrive: datasheet delay at large overdrive can be misleading when the real signal crosses threshold slowly.
  • “Threshold” is an error budget, not a single number: VOS, input bias/leakage, divider tolerance, and temperature all combine.
  • Output timing depends on the load network: open-drain outputs can look “slow” because Rpull·Cload dominates rise-time.
  • Noise immunity needs explicit design: slow ramps tend to chatter without hysteresis or filtering, especially at small overdrive.
How to read low-power comparator datasheets without surprises
  1. Always capture the delay condition: record the stated overdrive (mV), input edge rate, and load/pull-up used for the spec. If the working overdrive is smaller, assume delay can expand dramatically.
  2. Separate “internal decision” from “output edge”: verify whether the spec defines output crossing at 50% VDD or another threshold. External RC can dominate what the scope shows.
  3. Budget leakage in the complete front end: include ESD clamps, TVS parts, PCB contamination, and connector leakage—especially with MΩ dividers.
  4. Check start-up behavior: confirm if a stabilization time or recovery time is specified for power-up or deep-sleep operation.
Directional comparison (for selection routing)
Family focus Best at Watch-outs
Low-power (this page) Battery life, always-on thresholds, wake-up Delay vs overdrive, leakage-sensitive thresholds, pull-up RC edges
Precision Absolute threshold accuracy over temperature Higher power or added constraints; requires careful drift budgeting
High-speed / regenerative ns-class timing, sampling, low edge jitter Different architectures and constraints; not optimized for nA–µA always-on budgets
Bias to bandwidth to delay: low-power comparator cause chain Causal block diagram linking lower bias current to lower gm and bandwidth, producing higher delay at small overdrive. Includes a simplified delay versus overdrive curve with small and large overdrive points. Lower Bias / Iq nA–µA gm ↓ / BW ↓ internal pole lowers Delay ↑ small overdrive Propagation Delay vs Overdrive (concept) Overdrive Delay Small OD Large OD Small overdrive can expand delay by orders of magnitude.

DC threshold accuracy in real life: offset + bias + leakage

In low-power threshold designs, “accuracy” is rarely limited by a single comparator number. The practical threshold error is usually set by micro-currents flowing through mega-ohms and by environment-driven leakage (PCB surface, protection parts, connectors). This section turns threshold accuracy into a system error budget that can be measured and controlled.

Threshold error sources (organized by ownership)
Comparator-owned
  • VOS (input offset) and its distribution across units.
  • Drift vs temperature (offset drift and threshold stability over time).
Front-end-owned
  • Input bias × source impedance: IBIAS · RSRC turns pA–nA into mV–10s of mV when dividers are in the MΩ range.
  • Leakage × equivalent resistance: protection reverse leakage, PCB surface leakage, and connector leakage often dominate in humidity.
  • Divider tolerance / tempco: ratio error and drift shift the effective trip point.
System-owned
  • VDD variation: if the threshold is ratiometric to supply, supply ripple becomes threshold ripple.
  • Reference tolerance (if used): external VREF adds its own tolerance and drift into the threshold.
  • Environment: humidity and contamination can create leakage paths comparable to (or larger than) IBIAS.
Magnitude intuition (why MΩ dividers change the game)
  • Bias amplification: 1 nA through 10 MΩ produces 10 mV of threshold shift. With slow ramps and small overdrive, that can be the difference between a clean decision and repeated toggling.
  • Humidity leakage: a few nA of unintended leakage (PCB surface, connector, protection parts) can create tens of mV of drift when the threshold node impedance is high.
  • Typical vs worst-case: “typical bias/leakage” is not a design guarantee; for threshold accuracy, use upper-bound values across temperature.
Practical threshold error budget template (use as a checklist)
Budget framework

ΔVTH ≈ VOS + (IBIAS · RSRC) + (ILEAK · REQ) + DividerTol + Drift

  • RSRC: effective source impedance seen at the threshold node (divider Thevenin + sensor/source resistance).
  • REQ: effective resistance that leakage “sees” at the threshold node (often near the node’s Thevenin resistance).
  • IBIAS, ILEAK: use worst-case / max across temperature, including leakage from clamps, TVS parts, and connectors.
  • DividerTol + Drift: include both tolerance and temperature drift of the divider ratio.
Practical actions (avoid threshold surprises)
  • If divider total resistance is ≥ 1 MΩ: treat bias and leakage as primary risks; validate across humidity and contamination.
  • If required threshold error is < 10 mV: do not rely on typical bias/leakage; reduce node impedance or add buffering/controlled referencing.
  • If protection parts are required: check their reverse leakage vs temperature; leakage often dominates before VOS does.
  • Validate with a slow ramp test: confirm the trip point and ensure single-transition behavior at the real ramp rate and noise environment.
Threshold error budget bars for low-power comparator thresholds A conceptual bar chart showing threshold error contributors: offset, bias times resistance, leakage, divider tolerance, and temperature drift, with a note that mega-ohm dividers make bias and leakage dominate. Threshold Error Budget (concept) Contributors Error VOS IBIAS×R Leakage Divider Drift MΩ dividers make bias & leakage dominate.

Input common-mode & rail-to-rail reality (VICR corners)

“Rail-to-rail input” does not mean “no corner cases.” In low-VDD systems (1.x–3.3 V), trip points near the rails can behave differently due to common-mode crossover, input clamp currents, and recovery behavior. A reliable design starts by mapping the real input trajectory against the comparator’s VICR limits.

Three common rail-to-rail corner cases (in low-power thresholds)
  • Crossover near the rails: near-GND or near-VDD inputs can show different trip behavior compared to mid-supply operation.
  • Clamp current when input goes beyond rails: transients from cables, ESD events, or sensor overshoot can inject current and disturb the threshold node or supply.
  • Headroom and recovery behavior: some devices need margin to the rails under overdrive; slow recovery can appear as “sticky” outputs.
Decision action (simple workflow)
  1. Plot the real input trajectory: include slow ramps, expected noise, and worst-case transients.
  2. Overlay VICR and the rails: mark any time the input approaches a rail or enters the crossover region.
  3. Decide the interface: if the input touches VICR corners, add front-end scaling, controlled clamping, or buffering.
Common mistakes (why “RR input” still fails in the field)
  • Assuming RR means linear behavior at any rail-adjacent voltage: always check VICR conditions and crossover notes.
  • Checking abs-max only: survivability does not guarantee correct trip behavior or fast recovery.
  • Testing only with clean lab ramps: cable plug-in, ESD events, and supply bounce often create rail crossings and clamp currents.
  • Blaming noise first: rail-corner behavior can look like noise/chatter but has different fixes (mapping VICR first avoids misdiagnosis).
Input range versus rails with VICR and a slow-ramp trajectory Diagram showing GND and VDD rails, the valid input common-mode range (VICR) band, and a slow-ramp input trajectory approaching the rails. Highlights crossover risk near rails and clamp current beyond rails. Input Range vs Rails (concept) VDD rail GND rail Valid VICR band Crossover risk Near rail Clamp current beyond rails

Propagation delay vs overdrive (the #1 selection trap)

Comparator propagation delay (tpLH/tpHL) is not a single constant. Datasheet values are typically measured at a fixed overdrive (ΔVIN) and under a specific output load (pull-up and capacitance). In low-power families, a small overdrive (few mV) can expand delay from µs into ms, especially with slow ramps and noisy threshold crossings.

What the datasheet delay number actually depends on
  • Overdrive (ΔVIN): delay can change by orders of magnitude between a few mV and tens of mV.
  • Input edge rate: slow ramps keep the input near threshold longer, effectively operating at “small overdrive” for longer.
  • Output load: open-drain delay at the scope often includes pull-up and CLOAD rise-time, not only the internal decision time.
  • Definition of timing point: output threshold (50% VDD vs logic threshold) changes measured tp.
Why low-power comparators slow down at small overdrive
  • Weak bias reduces gm and bandwidth: small differential inputs take longer to move internal nodes past switching thresholds.
  • Recovery effects can dominate: under certain conditions, internal nodes may recover slowly, stretching apparent delay.
  • External pull-up RC adds “visible delay”: the internal decision may be faster than what the output edge shows.
Selection & measurement actions (use this workflow)
  1. Define the real overdrive at the decision moment: ΔVIN is the instantaneous amount beyond the trip point, not the full signal swing.
  2. Re-check delay under matching output conditions: use the same pull-up, CLOAD, and timing definition as the intended system.
  3. Validate two operating points: measure delay at a small and a large overdrive to bound worst-case timing.
  4. If noise causes repeated crossings near threshold: add hysteresis and/or input filtering so the decision does not re-trigger.
Propagation delay versus overdrive with a marked working point Concept curve of propagation delay versus input overdrive, with small and large overdrive points and a highlighted system working point on the curve. Delay vs Overdrive (concept) Overdrive Delay Small OD Delay inflates Large OD Delay stable Your ΔVin Small OD can push µs → ms.

Output stage in low-power designs: pull-up dominates everything

In low-power comparator systems, the “output behavior” is often set by external components rather than the silicon itself. For open-drain outputs, Rpull · CLOAD dominates the rise-time, while the low-level duty determines the pull-up’s static loss. Push-pull outputs provide cleaner edges but must be budgeted for dynamic current and fault/short scenarios in battery systems.

Open-drain + pull-up (low-power viewpoint)
  • Rise-time is external: trise is primarily set by Rpull · CLOAD.
  • Static loss is duty-dependent: when the output is LOW, the pull-up burns current; the average depends on low-level duty cycle.
  • Noise immunity links to edge speed: slow edges linger near digital thresholds longer, increasing susceptibility to interference.
Push-pull output (low-power viewpoint)
  • Cleaner edges: no external pull-up required for fast transitions in many cases.
  • Dynamic current still matters: edge charging/discharging and transient current peaks should be included in battery budgets.
  • Fault cases must be checked: shorts, back-drive, and multi-domain interactions can create unintended current paths.
Engineering workflow (design the output like a power component)
  1. Set a rise-time target: based on interrupt capture, sampling window, and noise margin needs.
  2. Estimate CLOAD: include MCU input capacitance, trace/cable capacitance, and any protection capacitance.
  3. Back-calculate Rpull: meet rise-time while respecting static loss at the expected LOW duty.
  4. Verify output limits: check IOL/VOL for open-drain and drive limits for push-pull; then review EMI for overly fast edges.
Open-drain comparator output with pull-up and load capacitance Block diagram showing an open-drain comparator output node pulled up by Rpull to Vpull with a load capacitor to ground, plus a simplified RC rise waveform labeled tau equals Rpull times Cload. Comparator Open-Drain (OD) OD sink Rpull Vpull Cload Rise edge τ = Rpull × Cload Rpull trades edge speed vs average loss.

Hysteresis for slow thresholds: stop chatter without killing accuracy

Low-power threshold systems are especially prone to chatter: the input often crosses the trip region slowly, the effective overdrive stays small, and noise repeatedly pushes the signal back and forth across the switching point. Hysteresis turns a single trip point into a two-threshold window (VTH+/VTH−) so the output can switch once and stay stable.

Why low-power thresholds need hysteresis more than “fast” systems
  • Slow ramps: the input dwells near the trip region, increasing the chance of multiple crossings.
  • Small overdrive: near-threshold operation is where low-power comparators are most delay- and noise-sensitive.
  • Real-world noise: supply ripple, sensor noise, and EMI can nudge the input across the boundary repeatedly.
Low-power trade-offs (what hysteresis changes)
  • Chatter stops, but the window widens: larger VHYS improves stability but increases the effective threshold band.
  • High-impedance nodes distort VHYS: bias and leakage currents can shift the effective thresholds when divider impedance is large.
  • Accuracy budget must include hysteresis: the system spec should explicitly accept the VTH+/VTH− window.
Executable rules (use these to size hysteresis without full derivations)
  • Chatter suppression target: choose VHYS such that VHYS ≥ 6 × VIN,noise,rms near the trip region (conservative rule-of-thumb).
  • If divider resistance > 1 MΩ: prioritize leakage and board contamination as the dominant error sources before fine-tuning calculations.
  • Validate on the real ramp: the final check is a slow-ramp test with realistic noise and worst-case conditions, confirming a single clean transition.
Slow ramp with noise: output chatter without hysteresis versus single switch with hysteresis Side-by-side conceptual plots showing an input slow ramp with noise and the resulting output: multiple toggles without hysteresis, and a single stable transition with hysteresis. Includes a small rule label for hysteresis sizing. Slow Ramp + Noise → Output Behavior Rule: VHYS ≥ 6×Vrms No Hysteresis Chatter Vin VTH Vout With Hysteresis Single switch Vin VTH+ VTH− Vout

Nano-power start-up & wake-up chains (harvesting / sleep modes)

Ultra-low-power comparators are often used as always-on sentries in harvesting and deep-sleep systems. Practical behavior depends on start-up and recovery: low start voltage, dynamic bias modes, internal reference settling, and post-wake threshold drift can all affect the first decision. A robust wake-up chain treats the comparator as a first-stage detector, then uses the MCU to confirm and decide.

Start-up behaviors that matter in nano-power systems
  • Low start voltage: enables harvesting chains but can increase sensitivity to conditions near the minimum operating point.
  • Dynamic or duty-cycled bias: reduces average current but introduces detection cadence and recovery constraints.
  • Reference settling time: after power-up or wake, internal thresholds may drift before stabilizing.
  • “Output stable” is not always “threshold stable”: define stability criteria for the decision, not only the logic state.
Wake-up chain pattern (avoid false wakes)
  • Comparator detects: early threshold crossing with nA–µA standby power.
  • MCU wakes: IRQ triggers a short active window.
  • MCU re-checks: confirm using a more accurate measurement (ADC / time window / multiple samples).
  • System decides: latch into a protected state, or return to sleep with a holdoff to prevent repeated wake-ups.
Executable stability definition (set warm-up time using measurable criteria)
  • Warm-up time: require the decision to remain stable before acting on it.
  • Example criterion: output stable and |ΔVTH| < X mV for Y ms (choose X from the threshold error budget, Y from system timing needs).
  • Confirm window: re-check with multiple samples to avoid reacting to a single transient crossing.
Energy-harvesting wake-up chain state machine using a nano-power comparator State machine diagram with states Sleep, Comparator detect, Wake MCU, Recheck, and Latch/Return. Includes a small signal chain from harvester or battery through divider to comparator, IRQ, and MCU/ADC confirmation with a warm-up stability criterion tag. Warm-up: |ΔVth| < X mV for Y ms Sleep nA standby Detect threshold Wake MCU IRQ Recheck confirm Latch / Return protect / sleep Signal chain: Harvester / Battery Divider Comparator MCU / ADC IRQ

Robustness: ESD/EMI/long wires without ruining nA budgets

Robust field behavior requires protection and filtering, but nanoamp-class threshold networks are extremely sensitive to leakage. In low-power comparator inputs, a “small” reverse leakage that is harmless in kΩ designs can shift thresholds by millivolts to tens of millivolts when the divider and source impedance are in the MΩ range. The goal is to block ESD/EMI and long-wire injection while preserving the threshold budget.

What low-power inputs are most sensitive to
  • Protection-device leakage: reverse leakage rises with temperature and can dominate the threshold node error.
  • RC side-effects: series R converts bias/leakage into DC shift; large C increases response time and can mask real events.
  • Long-wire injection: common-mode disturbances and ground transients couple into the trip region and cause false triggers.
Design actions (leakage-first protection strategy)
  1. Choose a low-leakage path: require leakage specs at temperature and include leakage × REQ in the threshold error budget.
  2. Pick series R with a DC budget: ensure bias/leakage currents across R stay below the allowed threshold shift.
  3. Pick C with a timing budget: filter the disturbance band while meeting the required detection response time.
  4. Manage long-wire coupling: route disturbance return paths away from the threshold reference; keep the trip node low-area and well-referenced.
Long-wire handling (principles only)
  • Control the return path: ensure surge/ESD currents return through a low-impedance path that does not lift the comparator reference.
  • Keep the trip node quiet: avoid exposing high-impedance nodes to cable-coupled fields; isolate with series impedance before clamps.
  • Verify by injection tests: the final pass condition is “no false trip” under realistic disturbance and temperature.
Low-power comparator input protection network with leakage and injected-noise paths Block diagram showing a cable feeding a series resistor into a threshold node with a filter capacitor and clamp/TVS devices. Two highlighted arrows indicate injected noise coupling from the cable and leakage paths from protection components into the threshold node. Input Protection Network (Leakage-first) Cable Connector R Trip node C Clamp TVS / Diodes Comparator IN Injected noise path Leakage path

Validation & measurement: how to test Iq, threshold, and delay correctly

Low-power comparator evaluations frequently fail due to measurement artifacts: meter burden voltage changes VDD, range switching hides peaks, output pull-up RC is mistakenly counted as propagation delay, and high-impedance nodes drift with humidity and contamination. A correct validation plan fixes definitions and conditions before collecting numbers.

Measuring Iq (nA–µA) without being fooled
  • Control burden voltage: verify the DUT VDD during measurement so the meter does not change the operating point.
  • Separate average vs peak: record a long-window average and a short-window peak if the device uses duty-cycled bias modes.
  • Check supply ripple sensitivity: compare low-ripple vs high-ripple supply conditions to avoid ripple-driven current drift.
  • Watch fixture leakage: in nA tests, probes, sockets, and contamination can create parallel leakage paths that corrupt the result.
Measuring propagation delay (define conditions first)
  1. Fix overdrive: test at two points (small and large ΔVIN) to bound worst-case behavior near threshold.
  2. Fix stimulus edge: ensure the input step/ramp is fast enough for the intended definition, or the source becomes the limit.
  3. Fix output load: match Rpull and CLOAD to the real system, or RC dominates the observed edge.
  4. Fix timing thresholds: document the input and output crossing points used for tpLH/tpHL.
Measuring threshold and hysteresis (make drift sources visible)
  • Use slow sweeps: identify VTH+ and VTH− and confirm single-switch behavior on slow ramps.
  • Use steps: isolate repeatability and noise effects under controlled overdrive and timing definitions.
  • Record temperature drift: log VTH and VHYS versus temperature for worst-case thresholds.
  • Separate humidity/contamination effects: compare dry vs stressed conditions to detect leakage-dominated drift in high-impedance networks.
Recommended test bench for low-power comparator Iq, threshold and delay Block diagram showing programmable supply and current meter feeding the DUT, an AWG or step source driving a divider into the comparator input, and an oscilloscope with two probes measuring input and output nodes. Includes a pull-up resistor and load capacitance on the output. Recommended Test Bench (Definitions Fixed) Supply VDD monitor Current Meter Low burden Scope 2 probes AWG / Step step / ramp Divider DUT Comparator Rpull Cload VDD Probe A (Vin) Probe B (Vout)

Engineering checklist + IC selection logic (what to ask vendors)

Low-power comparator selection fails most often when “typical Iq” is treated as the deciding factor. In battery thresholds, wake-up chains, and slow sensor trip points, leakage, overdrive-dependent delay, rail-corner input behavior, and output pull-up RC can dominate the outcome. This checklist turns those traps into actionable questions, pass/fail gates, and a copy-paste inquiry template.

Must-ask fields (low-power essentials)

Priority Spec / Field Why it matters What to ask Pass / Fail gate
P0 Iq (typ & max, over temperature) Battery life is set by worst-case and operating mode, not typical. Provide Iq(max) vs temperature and test conditions (output state, switching activity, load). Fail if only typical is provided or test conditions do not match the use case.
P0 Start voltage / start-up behavior Harvesting and deep-sleep chains often operate near minimum VDD and during recovery windows. Minimum start voltage, behavior during ramp, and warm-up/stabilization time for thresholds. Fail if first-decision stability cannot be specified or verified.
P0 Input bias & leakage (over temperature) At MΩ impedance, pA–nA currents translate into mV–tens of mV threshold shifts. Ibias and input leakage (min/typ/max) vs temperature and recommended impedance limits. Fail if leakage is not bounded across temperature for high-impedance dividers.
P0 VICR rail-corner behavior “Rail-to-rail input” still has corners: crossover, headroom needs, and recovery effects. Input range near GND/VDD at operating temperature and behavior when input approaches/exceeds rails. Fail if the threshold operates in an undefined rail corner region.
P1 Propagation delay vs overdrive Delay can explode at small overdrive (near threshold), which is common in slow-ramp designs. Provide tp vs overdrive curves or specify tp at the exact overdrive of the use case. Fail if only a single tp number is shown without overdrive and load conditions.
P1 Output structure & drive (OD/PP, IOL/IOH) Open-drain rise time and power are set by pull-up and Cload; push-pull has different transient behavior. IOL/VO(L) and IOH/VO(H) (or OD sink limits), allowable pull-up voltage, and recommended Rpull range. Fail if the output cannot meet required edge timing under system Rpull/Cload.
P1 Internal reference / warm-up stability (if applicable) Wake decisions can be wrong if thresholds drift immediately after start-up. Stabilization time and post-wake threshold drift bounds under VDD and temperature corners. Fail if no measurable stability criterion can be supported in validation.
P2 Clamp current / fault tolerance Long wires and hot-plug can force current into input clamps and shift the trip node. Allowable input current, recovery behavior, and recommended series resistance for protection. Fail if clamp behavior is undefined for expected line transients.
P2 Package / board leakage sensitivity Humidity and contamination can create parallel leakage paths that dominate high-Z nodes. Package options, recommended cleaning/guarding guidance, and validation suggestions for high-Z operation. Fail if field conditions include humidity and no mitigation plan exists.

Notes: Priorities are for general-purpose low-power threshold chains (battery/PG/wake/slow sensors). For ns-class timing, latched sampling, precision windows, or zero-crossing, use the dedicated comparator family pages instead.

Risk → Action mapping (field-ready triage)

Risk symptom Likely bucket Immediate action
Threshold shifts with humidity / handling Board leakage dominates high-Z node Run dry vs stressed comparison; clean/coat/guard; reduce impedance if the budget allows.
False triggers on long wires / outdoor noise Injected noise path + reference bounce Review injection and return paths; use leakage-aware RC and clamp placement; validate with disturbance injection.
Delay is far slower than datasheet number Overdrive mismatch (too small) Measure tp at the real overdrive; request tp-vs-OD data; increase effective overdrive or add hysteresis if acceptable.
Output edge is slow / timing fails intermittently Pull-up RC dominates (open-drain) Back-solve Rpull from required rise time and Cload; confirm IOL/VOL; confirm power vs duty cycle.
Chatter near threshold on slow ramps Noise + slow ramp + small overdrive Add hysteresis sized to noise; verify single-switch behavior on worst-case ramp and temperature.

Vendor inquiry template (copy-paste)

Replace bracketed values with the real operating point. The goal is to lock test conditions so the response is comparable across vendors. 

Application: [battery UV/OV] / [power-good] / [wake-up] / [slow sensor threshold]

Operating conditions:
- VDD: [min / typ / max] V
- Temperature: [min .. max] °C
- Threshold target: VTH = [value] V (allowed error = ±[mV])
- Divider / source impedance: Rtop=[ ], Rbot=[ ], Rsource≈[ ] (note if > 1 MΩ)
- Input behavior: [slow ramp dV/dt = ] / [step] / [noisy threshold region]
- Minimum overdrive near trip: ΔVIN(min) = [mV], ΔVIN(typ) = [mV]

Output / load:
- Output type required: [open-drain] / [push-pull]
- Pull-up voltage (if OD): VPU=[ ] V, Rpull=[ ] Ω, Cload=[ ] pF
- Required edge / timing: rise time < [ ] ns/us, delay budget at ΔVIN(min) < [ ] us/ms

Protection / robustness:
- Cable / environment: [long wire length], [outdoor], [ESD/EMI exposure]
- Input network: series R=[ ], C=[ ], clamp/TVS=[low-leakage requirement]

Please provide (must match conditions above):
1) Iq: typical and maximum over temperature, including test conditions (output state, switching activity, load)
2) Input bias and input leakage (min/typ/max) over temperature
3) Propagation delay at ΔVIN(min) and ΔVIN(typ), or tp vs overdrive curves with the load specified
4) VICR behavior near rails at VDD(min) and temperature corners (including any crossover / recovery behavior)
5) Startup/warm-up stability: time until threshold is within ±[mV] and remains stable for [ms]
6) Output drive limits (IOL/VO(L), IOH/VO(H) or OD sink capability), and allowed pull-up voltage range
7) Clamp current / fault tolerance guidance and recommended series resistance for input protection

Example part numbers (starting points; verify latest datasheets)

Shortlists below match the “general-purpose low-power” scope (battery thresholds, wake-up, power-good, slow ramps). Final selection must be validated at the real overdrive, load, temperature, and leakage conditions.
Bucket A — Always-on / ultra-low standby (nanoamp-class)
  • TI: TLV3691 (low-power, battery/wake-up style comparator family)
  • ST: TS880 / TS883 (low-power threshold and wake-up type options)
  • Analog Devices / Linear: LTC1540 (low-power reference/comparator-style building block for threshold functions)
Bucket B — µA-class “balanced” low-power general purpose
  • TI: TLV7011 / TLV7021 (push-pull / open-drain variants; common in low-power threshold chains)
  • Microchip: MCP6541 (general low-power comparator option; confirm tp vs OD and output loading)
  • Microchip: MCP6546 / MCP6547 / MCP6548 / MCP6549 (open-drain family style options; verify pull-up domain requirements)
Bucket C — If the design needs supervisor-like “threshold + stability” behavior
  • Consider comparator families with integrated reference / programmable threshold features (verify warm-up stability and leakage impact).
  • Use the inquiry template above to lock conditions; avoid selecting purely by typical reference accuracy numbers.
Three-step selection flow for general-purpose low-power comparators Flowchart showing Step 1 accuracy and leakage budget, Step 2 overdrive-dependent delay and chatter control, and Step 3 output load and robustness validation. Includes three stop-sign tags for common traps: megaohm dividers with humidity, small overdrive, and large output capacitance. 3-Step Selection Flow (Low-Power Threshold Chains) MΩ divider + humidity Small overdrive Large Cload / slow edges Step 1 Accuracy budget Ibias / leakage VICR corners Step 2 Overdrive Delay vs OD Chatter control Step 3 Output load Pull-up RC Validation Validation plan (must match the inquiry conditions) Iq (avg + peak) VTH / VHYS vs T tp at real overdrive

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FAQs (low-power comparators): quick fixes, gates, and traps

These FAQs close long-tail issues without expanding scope: overdrive-dependent delay, pull-up RC, high-impedance leakage, slow-ramp chatter, rail-corner VICR behavior, start-up stability, protection leakage, and measurement traps.

Why does the datasheet say µs delay, but the board behaves like ms? OD / RC
Symptom
The output transition occurs much later than expected, especially near the trip threshold.
Likely causes (Top 3)
  • Overdrive mismatch: datasheet tp is specified at a larger ΔVIN than the real trip region.
  • Open-drain rise-time counted as delay: Rpull × Cload dominates the observed edge.
  • Input ramp too slow / noisy: the input spends a long time hovering near threshold (effective ΔVIN is tiny).
Quick checks
  1. Probe Vin at the comparator pin and Vout simultaneously (two probes).
  2. Increase ΔVIN temporarily (or apply a faster step) and confirm tp collapses from ms → µs.
  3. For open-drain, reduce Rpull (or reduce Cload) and confirm the edge speed improves.
Threshold
  • Small overdrive warning: if ΔVIN(min) is in the single-digit mV range, expect delay to expand dramatically unless tp-vs-OD data supports it.
  • RC rise-time estimate (open-drain): trise(10–90%) ≈ 2.2 × Rpull × Cload.
Action
  1. Re-evaluate delay at the real ΔVIN near trip; request or measure tp vs overdrive.
  2. If open-drain, design Rpull from the edge-time budget first, then check power vs duty cycle.
  3. Add minimal hysteresis or input RC to avoid hovering around the threshold region.
Avoid
  • Do not compare datasheet tp numbers unless overdrive and output load conditions match the system.
Why does the threshold drift wildly when the divider is several MΩ? Leakage
Symptom
The measured trip point shifts by mV–tens of mV between boards, humidity levels, or temperature.
Likely causes (Top 3)
  • Input bias / leakage × high impedance: pA–nA currents become large DC shifts at MΩ nodes.
  • Board surface leakage: contamination and humidity create parallel leakage paths that rival the IC.
  • Protection leakage: TVS/clamps can leak more than the comparator input at temperature.
Quick checks
  1. Reduce divider impedance by 10× (temporary) and see if the threshold stabilizes.
  2. Compare dry vs stressed conditions (warm air / humidity exposure) and log ΔVth.
  3. Remove/replace the clamp/TVS (temporary) and check if ΔVth disappears.
Threshold
  • Leakage-dominant gate: if (Ileak × REQ) is a meaningful fraction of the allowed threshold error, the design is leakage-limited.
  • Practical warning: once divider impedance is in the multi-MΩ range, board leakage often dominates unless cleanliness and guarding are controlled.
Action
  1. Budget threshold error as: ΔVth ≈ Vos + Ibias·Rsrc + Ileak·REQ + divider tolerances + temp drift (use as a framework).
  2. Lower impedance (or buffer the node) if the leakage budget cannot be met.
  3. Use low-leakage protection choices and validate leakage across temperature and humidity.
Avoid
  • Avoid assuming “pA bias” remains pA on real boards; surface leakage can exceed IC leakage in the field.
Why does a slow-ramp input toggle repeatedly, and how much hysteresis is “enough”? Hysteresis
Symptom
The output chatters near the trip point during slow threshold crossings or noisy signals.
Likely causes (Top 3)
  • Noise near threshold: Vin repeatedly crosses the effective trip point when dV/dt is small.
  • Too little hysteresis: internal hysteresis may be insufficient for the real noise/ramp conditions.
  • High impedance + leakage: the “effective” hysteresis shifts due to bias/leakage at MΩ nodes.
Quick checks
  1. Measure Vin noise at the comparator pin (same bandwidth each time) and estimate RMS.
  2. Add temporary hysteresis (or increase existing hysteresis) and confirm chatter disappears.
  3. Reduce divider impedance (temporary) to see if leakage-driven drift is contributing.
Threshold
  • Chatter stop rule: VHYS ≥ 6 × Vnoise,rms (measured at the comparator pin).
  • Example: if Vnoise,rms ≈ 2 mV, target VHYS ≥ 12 mV.
Action
  1. Set hysteresis to exceed the noise band, then re-check threshold accuracy under worst-case leakage and temperature.
  2. Use a small input RC to limit bandwidth if noise is wideband and the application is slow-threshold.
  3. Validate “single-switch” behavior with the slowest expected ramp and highest expected noise.
Avoid
  • Avoid increasing VHYS blindly without re-checking the allowed threshold error budget.
With open-drain output, Rpull saves power but edges are too slow—what now? Output
Symptom
The rising edge is slow, timing margins fail, or the MCU misses/late-detects the transition.
Likely causes (Top 3)
  • Rpull × Cload dominates: edge speed is set by the external RC time constant.
  • Hidden Cload: long traces, ESD networks, connectors, and input pins add capacitance.
  • Incorrect pull-up domain: pull-up voltage or level shifting increases capacitance or slows the node.
Quick checks
  1. Measure Cload (estimate from rise time) by observing the 10–90% edge and back-solving.
  2. Temporarily reduce Rpull by 2–5× and confirm the rise time improves accordingly.
  3. Disconnect non-essential loads (test points, long cable input, extra IC pins) and compare edges.
Threshold
  • trise(10–90%) ≈ 2.2 × Rpull × Cload → choose Rpull ≤ trise,target / (2.2 × Cload).
  • Ensure IOL at low level meets the sink requirement at the chosen Rpull and pull-up voltage.
Action
  1. Pick Rpull from the edge-time budget, then compute power from duty cycle and VO(L).
  2. Reduce Cload (shorter trace, fewer loads, smaller ESD capacitance) if power cannot increase.
  3. If edges must be fast at low power, consider a push-pull comparator (verify transient current constraints).
Avoid
  • Avoid selecting Rpull by “power only”; OD edges are an RC design problem first.
“Rail-to-rail input” still misbehaves near GND or VDD—why? VICR
Symptom
Threshold shifts, delayed recovery, or unexpected behavior occurs when Vin is very close to rails.
Likely causes (Top 3)
  • VICR corner/crossover: internal input stage transitions near rails can change behavior.
  • Headroom needs under overdrive: “RR” may not be identical under all dynamic conditions.
  • Input clamp currents: brief excursions beyond rails inject current and distort the trip region.
Quick checks
  1. Overlay Vin(min/max) across temperature against datasheet VICR(min/max) margins.
  2. Move the threshold away from the rail (temporary) by adjusting the divider and observe stability.
  3. Add series resistance to limit clamp currents if Vin can exceed rails during events.
Threshold
  • Margin gate: if the trip region touches a VICR boundary at VDD(min) or temperature corners, behavior risk is high.
  • Clamp gate: if Vin can exceed rails, ensure series R limits clamp current to within the device guidance.
Action
  1. Redesign the threshold so normal operation stays comfortably inside the guaranteed VICR across corners.
  2. Use a front-end divider/clamp strategy that keeps the comparator pins within safe and defined regions.
  3. Validate rail-corner behavior with the same overdrive and output load used in the system.
Avoid
  • Avoid placing trip thresholds “right on the rail” unless VICR corner behavior is validated.
After power-up, the threshold is unstable for seconds—how to define soak time? Startup
Symptom
Early decisions after power-up are inconsistent; wake-up triggers happen too early or vary by unit.
Likely causes (Top 3)
  • Internal bias/reference settling: low-power bias circuits can need time to stabilize.
  • Supply ramp effects: the comparator behaves differently during ramp vs steady state.
  • Threshold network charging/leakage: high impedance nodes can take time to reach a stable operating point.
Quick checks
  1. Log Vth (or the trip decision) vs time after power-up across temperature corners.
  2. Repeat with a faster/slower VDD ramp to see if behavior depends on ramp rate.
  3. Repeat with divider impedance reduced 10× (temporary) to identify high-Z settling/leakage sensitivity.
Threshold
  • Stability criterion: define soak time as the earliest time when |ΔVth| < X mV for a continuous window of Y ms.
  • Practical start point: choose X based on the allowed threshold error and choose Y long enough to exclude slow drift (then tighten if needed).
Action
  1. Implement a wake chain: comparator detect → MCU wake → MCU re-check after soak → latch/return to sleep.
  2. Use the stability criterion above to set the MCU re-check time under worst-case corners.
  3. If soak time is unacceptable, reduce node impedance or select a comparator with defined start-up stability.
Avoid
  • Avoid making final decisions from the first transition after power-up without a stability gate.
After adding TVS/clamps, the threshold changed—who is leaking, and how to find it fast? Protection
Symptom
The trip point shifts after adding a clamp/TVS network, especially at high temperature.
Likely causes (Top 3)
  • TVS reverse leakage: often rises sharply with temperature.
  • Clamp diode leakage: protection to rails injects or steals current from the high-Z trip node.
  • Board leakage around protection footprint: contamination creates a parallel leakage path.
Quick checks
  1. Measure trip node voltage shift while locally heating the TVS/clamp area (hot air, controlled) and look for correlation.
  2. Temporarily remove/replace the TVS or clamp with a known low-leakage option and compare ΔVth.
  3. Reduce divider impedance 10× (temporary) and see whether the “TVS effect” disappears (leakage-limited confirmation).
Threshold
  • If removing the protection restores the original Vth, the shift is protection/footprint leakage-dominated.
  • Leakage risk is high when the trip network is multi-MΩ and protection leakage is not bounded across temperature.
Action
  1. Choose protection with a leakage spec across the full temperature range and include it in the threshold budget.
  2. Use series resistance to isolate the trip node from clamp leakage while meeting fault-current requirements.
  3. Validate with a temperature sweep: record ΔVth with and without the protection network populated.
Avoid
  • Avoid “generic TVS” choices on high-Z trip nodes without leakage validation across temperature.
Can a low-power comparator be used for zero-cross detection? Boundary
Symptom
The design attempts AC zero-cross timing, but timing jitter or missed crossings appear in noise.
Likely causes (Top 3)
  • Small overdrive at crossing: near zero, ΔVIN is tiny and low-power delay/jitter increases.
  • Noise and common-mode injection: long wires and mains environments inject disturbances near the crossing.
  • Inappropriate family choice: zero-cross timing often needs dedicated zero-cross comparators or hysteresis shaping.
Quick checks
  1. Estimate ΔVIN at the crossing and compare it to the noise level at the comparator pin.
  2. Add controlled hysteresis and confirm whether jitter reduces without unacceptable phase shift.
  3. Compare against a dedicated zero-cross / Schmitt-trigger approach if timing precision is required.
Threshold
  • If ΔVIN near the crossing is comparable to noise, low-power comparators will show timing uncertainty unless hysteresis and filtering are engineered.
Action
  1. Use low-power comparators for “presence/phase window” detection only if timing tolerance is loose and noise is controlled.
  2. For precise zero-cross timing, select a comparator family intended for zero-cross/phase detection (and validate jitter and noise immunity).
Avoid
  • Avoid using a nanoamp-class comparator as a drop-in “timing zero-cross” element without overdrive and noise validation.
How to measure nanoamp Iq without being misled by meter burden and range behavior? Measurement
Symptom
Measured Iq changes with meter range, wiring, or supply settings; numbers do not repeat.
Likely causes (Top 3)
  • Burden voltage: the meter drops voltage that changes the DUT operating point.
  • Range switching / sampling window: peaks and averages are mixed or missed.
  • Fixture leakage / supply ripple: nA measurements are corrupted by leakage paths and ripple-driven current changes.
Quick checks
  1. Measure VDD at the DUT while measuring current; confirm the meter is not shifting VDD.
  2. Record both a long-window average (seconds) and a short-window peak (ms) if duty-cycling is possible.
  3. Repeat with a low-ripple supply (or extra filtering) to see if Iq tracks ripple.
Threshold
  • Measurement gate: if VDD at the DUT changes when inserting the meter, the Iq number is not representative.
Action
  1. Use a low-burden measurement method and always log the DUT VDD simultaneously.
  2. Define the reporting number: “steady-state average Iq” and, if needed, “wake peak current”.
  3. Clean the fixture and minimize exposed high-impedance nodes during measurement.
Avoid
  • Avoid quoting Iq without the measurement conditions and the DUT VDD verification.
Output jitter / false triggers: input noise or ground bounce—how to tell quickly? Debug
Symptom
The comparator output toggles unexpectedly when other circuits switch, cables move, or loads change.
Likely causes (Top 3)
  • True input noise: disturbances appear directly on Vin at the comparator pin.
  • Reference/ground bounce: comparator “sees” a moving reference due to return currents.
  • Probe/measurement artifact: ground leads and probe placement create false coupling.
Quick checks
  1. Probe Vin at the comparator pin and probe a local reference point; move the probe ground to confirm artifacts.
  2. Short Vin to a stable DC source (temporary). If toggling remains, suspect reference bounce or output coupling.
  3. Change the return current path (temporary wiring/ground strap) and see whether false triggers track return routing.
Threshold
  • If Vin at the pin stays quiet while output toggles, the dominant issue is likely reference/ground movement or measurement artifact.
Action
  1. First eliminate measurement artifacts (short ground leads, consistent probe points).
  2. Add hysteresis and/or bandwidth limiting (RC) if the issue is true input noise.
  3. If ground bounce is dominant, isolate comparator reference and keep disturbance return currents away from the trip reference.
Avoid
  • Avoid debugging with long probe ground leads; they can create false “noise” that disappears in real operation.
Same comparator, different boards: thresholds differ a lot—what three things to check first? Variance
Symptom
One board trips “early,” another “late,” even with the same BOM and firmware.
Likely causes (Top 3)
  • Cleanliness/humidity differences: surface leakage around the trip node varies between builds.
  • High-Z node layout exposure: routing and proximity to noisy nets changes coupling and leakage paths.
  • Source impedance and protection variation: small differences in divider, clamps, or input RC alter the effective threshold.
Quick checks
  1. Perform a dry vs stressed comparison (heat/humidity exposure) and log ΔVth per board.
  2. Reduce divider impedance 10× (temporary) and check if board-to-board spread shrinks.
  3. Remove/replace input protection (temporary) and check if the spread follows protection leakage.
Threshold
  • If board-to-board spread shrinks strongly when impedance is reduced, the system is leakage-limited, not offset-limited.
Action
  1. Control and validate cleanliness (cleaning process, coating/guarding if required) for high-Z trip nodes.
  2. Reduce impedance or buffer the threshold node if the field environment is humidity-variable.
  3. Standardize the protection network and verify leakage across temperature with incoming inspection tests.
Avoid
  • Avoid treating “same schematic” as “same leakage.” Process and environment control are part of the design.
False triggers increase at low/high temperature—what temperature-linked items to check first? Temperature
Symptom
Trips become noisy or inconsistent at cold/hot corners even when the nominal threshold is correct at room temperature.
Likely causes (Top 3)
  • Protection leakage vs temperature: TVS/clamps often leak more at hot, shifting the trip node.
  • Input bias/leakage vs temperature: comparator input currents change across corners, amplified by high impedance.
  • VICR and recovery corners: rail-corner behavior can degrade at temperature and low VDD.
Quick checks
  1. Log Vth and false-trigger rate vs temperature with the protection network installed and then removed (temporary A/B).
  2. Repeat with divider impedance reduced 10× (temporary) to isolate leakage-limited behavior.
  3. Move the operating threshold away from rails (temporary) and see if corner behavior improves.
Threshold
  • If false triggers correlate strongly with temperature and vanish when impedance is reduced, the dominant issue is leakage/bias vs temperature.
Action
  1. Choose and validate low-leakage protection across temperature; include it explicitly in the threshold budget.
  2. Increase hysteresis or limit bandwidth if noise grows at corners and causes repeated crossings.
  3. Ensure the trip region stays inside the guaranteed VICR and away from rail-corner uncertainties.
Avoid
  • Avoid validating only at room temperature; leakage-limited designs must be corner-tested.

Tip: For fastest debug, start with two-probe visibility (Vin at the pin + Vout) and a 10× impedance A/B test. These two checks usually separate “leakage-limited,” “RC-limited,” and “overdrive-limited” failure modes within minutes.

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