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Input Common-Mode Range (VICR) in Comparators

Input Common-Mode Range (VICR) in Comparators

← Back to:Comparators & Schmitt Triggers

This page helps ensure comparator inputs stay inside the valid common-mode range (VICR) across real-world rails, ripple, and spikes, so thresholds do not drift, mis-trigger, or recover slowly near the rails. It turns VICR and rail-to-rail crossover behavior into a practical workflow: define the input envelope, spot risky zones, verify on the bench, and guardband with confidence.

What VICR really means in comparators (not op-amps)

VICR (input common-mode range) is the guaranteed common-mode window where a comparator’s input stage stays in its intended operating region. Outside that window, a comparator may still toggle, but threshold accuracy, propagation delay, and recovery behavior are no longer assured.

Practical interpretation (use this every time)
  • Absolute limits protect the pins; they do not mean the comparator will behave correctly.
  • VICR (guaranteed) is where key metrics and correct polarity are specified under stated test conditions.
  • Functional-but-not-guaranteed is the risky gray zone: toggling may happen, but offset/delay/recovery can shift unpredictably.
  • Near the rails, comparators are more prone to visible failures (wrong polarity, slow recovery) because the input stage can saturate or switch regimes.
Terms that often get mixed up
VCM is the common-mode level of the two inputs (approximately the average). VICR is the allowed VCM window where the input stage is specified to operate properly. Some datasheets also list “input voltage range” or show typical curves that look wider than the guaranteed VICR—treat those as typical/functional unless explicitly guaranteed.
Why comparators fail earlier at the boundary
  • Headroom loss: input devices lose operating margin near a rail → gain drops → effective offset shifts.
  • Clamp onset: protection paths start to conduct → injected current moves the input node, especially with high source resistance.
  • Saturation & recovery: internal nodes saturate or switch regimes → delay and recovery time can jump, causing wrong-polarity blips or late edges.
Standard sentence template for reading VICR (copy/paste)
Under VDD = ___, TA = ___, output/load = ___, and input overdrive = ___, the guaranteed VICR is [___, ___]. If the design VCM enters a near-rail / crossover region, expect step-changes in offset, delay, or recovery. If VCM goes beyond VICR, output toggling may still occur, but threshold accuracy and timing must be validated with a VCM sweep and stress waveforms, with guardband.
Actions to avoid VICR surprises
  1. Define the full VCM envelope (including start-up and transients) at VDD(min/max) and temperature corners.
  2. Design to the guaranteed VICR (not typical curves) and add a guardband for near-rail/crossover behavior.
  3. Assume any clamp conduction or high source resistance can shift the effective threshold; verify with VCM sweep measurements.
Comparator VICR: guaranteed range, gray functional zone, and rail limits Vertical voltage ruler showing VDD and VSS rails, a green guaranteed VICR band, a gray functional-but-not-guaranteed zone, and a near-rail risk band with a VCM sweep arrow. VDD VSS Guaranteed VICR Near-rail / crossover risk Functional (not guaranteed) Absolute-risk edge VCM sweep Comparator input stage VICR defines its safe VCM

Datasheet decoding: where VICR hides and what conditions matter

VICR is rarely a single number. Its usable boundary depends on test conditions (VDD, temperature, input overdrive, output state, pull-up/load, and input bias/leakage). The goal is to separate guaranteed operating range from typical curves and to identify near-rail or crossover regions that can cause step-changes in threshold or timing.

Fast reading path (in order)
  1. Absolute Maximum Ratings: beyond-the-rails allowance and any input current limit requirement.
  2. Recommended Operating Conditions: the range that is most likely to be guaranteed for correct behavior.
  3. Electrical Characteristics (tables): VICR min/max and related metrics (offset, bias/leakage, delay).
  4. Typical Curves: VICR/offset/delay vs VCM, VDD, temperature; look for crossover “knees”.
  5. Notes / Test Conditions: hidden assumptions (overdrive, output saturation, pull-up/load, measurement circuit).
Conditions that can move the boundary
  • VDD and temperature: headroom changes → near-rail margin shrinks or shifts.
  • Input overdrive: large swings can trigger clamp paths or saturation recovery → timing/threshold become non-ideal.
  • Output state & load: saturation and pull-up choices can change internal operating points, affecting recovery.
  • Bias/leakage + source resistance: Ib × Rs converts into threshold error, often worse near the rails.
What to treat as “guaranteed” vs “typical”
  • Guaranteed: table limits under explicit test conditions (often tied to Recommended Operating Conditions).
  • Typical: curves without min/max bounds; useful to spot crossover trends but not safe as a design limit.
  • Gray-zone warning sign: any note like “output may toggle” or “performance not guaranteed” outside VICR.
VICR reading checklist (field → meaning → trap → verification)
Datasheet field
What it really means
Common trap
Verification action
VICR (min/max)
Guaranteed VCM window under stated VDD/TA/overdrive/load.
Using typical curves as limits.
Sweep VCM at VDD corners; log wrong toggles or delay jumps.
Input voltage range / beyond-rail note
Whether inputs may go past rails, and under what current limit.
Assuming “not damaged” means “works correctly”.
Inject controlled over/under-rail events; check recovery time.
Input bias / leakage vs VCM
Bias/leakage may change near rails → threshold shifts with Rs.
Ignoring Rs in divider or sensor sources.
Sweep Rs (or add series R) and measure trip point drift.
Offset / delay vs VCM curve
Crossover “knee” indicates regime switching; expect step-changes.
Designing VCM right on the knee.
Place operating VCM away from knees; validate across corners.
Guardband rule: treat any near-rail or crossover region as a design risk zone unless the datasheet provides worst-case limits and conditions that match the application.
Where VICR hides in a datasheet and the recommended reading order Block diagram of a datasheet with five labeled sections and arrows showing the recommended reading order to decode VICR conditions. Datasheet map for VICR 1) Abs Max Beyond-rail? 2) Rec Ops Guaranteed region 3) Tables VICR / Ib / delay 4) Curves Crossover knees 5) Notes Overdrive / load Use tables for guaranteed VICR; use curves to spot crossover; confirm hidden conditions in notes.

Inside the input stage: why VICR has headroom and why RR has crossover

VICR is fundamentally a headroom story. Comparator input devices and internal nodes need voltage margin to stay in their intended region. When common-mode approaches a rail, the input pair (or internal bias nodes) can leave that region, and the comparator’s effective behavior changes. Rail-to-rail (RR) inputs extend coverage by using two input stages, which introduces a crossover region where performance can step or bend.

What changes first (and why it matters)
  • Non-RR input: as VCM approaches a rail, device headroom shrinks → effective input gain drops → offset grows and delay slows.
  • RR input: two input stages share the job (PMOS-side and NMOS-side coverage) → mid-range handoff creates a crossover knee.
  • Crossover is not “failure”, but it is a design risk zone: offset, bias/leakage, and delay can change faster than expected.
Non-RR input stage: “margin runs out” near a rail
A non-RR comparator typically uses one input pair and bias network that require voltage headroom. Near a rail, internal devices can lose operating margin (reduced VDS/VGS room), which reduces effective transconductance and changes bias currents. The result is a predictable pattern: trip threshold drifts, delay increases, and recovery can slow even if inputs never exceed absolute limits.
RR input stage: “coverage expands” but a crossover knee appears
RR-input comparators often combine two input stages (commonly PMOS-dominant at low VCM and NMOS-dominant at high VCM). The handoff between stages is the crossover region. In that region, effective gain, input bias/leakage, noise, and delay can change more abruptly. Any application that sits on the knee (or sweeps through it) should treat it as a measured-and-guardbanded region.
Input stage type → typical VICR shape → what to watch
Input stage type
Typical VICR shape
Bench symptoms & de-risk action
Single (non-RR) input pair
Clear headroom margins from rails; usable VCM window is narrower than supply span.
Symptoms: smooth drift in trip point near a rail; delay slows as VCM approaches boundary.
Action: keep operating VCM inside guaranteed VICR with guardband; validate with VCM sweep at corners.
RR (dual input stages)
Wider VCM coverage, but a mid-range crossover knee (handoff zone) appears.
Symptoms: step/knee in offset, bias/leakage, or delay vs VCM.
Action: do not place VCM on the knee; sweep VCM and record trip & delay at VDD/TA corners.
Clocked dynamic front-end (regenerative class)
Strongly condition-dependent; common-mode and clocking can dominate behavior.
Symptoms: sensitivity to clock phase, kickback, and input source impedance.
Action: treat as a dedicated architecture topic; verify with clocked test conditions (details belong in the regenerative front-end page).
Fast checks that prevent crossover surprises
  1. Find any knee in offset/delay/bias vs VCM; assume it shifts with VDD and temperature.
  2. Keep the operating VCM away from near-rail and crossover zones; reserve margin for ripple and transients.
  3. Validate with a VCM sweep at VDD(min/max) and temperature corners; log trip point and delay changes.
RR input crossover: two stages overlap and create a knee region Plot-style diagram with two curves labeled Stage A and Stage B versus VCM, with a highlighted crossover region and short callouts for offset step, Ib change, and delay knee. VCM (from VSS to VDD) Effective input dominance Crossover Stage A active Stage B active Knee effects offset step Ib change delay knee VSS VDD

Near-rail behavior: threshold accuracy collapse mechanisms

“Near-rail drift” is rarely random. It usually comes from a small set of mechanisms that become dominant when common-mode headroom is limited (especially at low supplies such as 1.8 V). Splitting the problem into the right bucket makes debugging fast and repeatable.

Three dominant mechanisms near the rails
  • Input-stage nonlinearity: headroom loss changes effective input gain → offset shifts and timing slows.
  • Bias/leakage jump: bias or leakage changes with VCM → Ib × Rs becomes a threshold error amplifier.
  • Clamp injection: protection paths start conducting → injected current disturbs the input node → step errors and slow recovery.
1) Input-stage nonlinearity (headroom loss)
As VCM approaches a rail, internal nodes lose margin and the input pair no longer behaves linearly. The comparator still toggles, but the effective offset becomes condition-dependent, and propagation delay typically increases. Bench clue: trip point drift is often smooth and monotonic as VCM moves toward the boundary.
2) Bias/leakage jump (Ib × Rs threshold shift)
Input bias/leakage can change significantly near the rails or near crossover. When the source is high impedance (divider, sensor, long line), that current creates a voltage drop: ΔV ≈ Ib × Rs. Even if Ib is small, large Rs turns it into a visible threshold error. Bench clue: changing divider values or adding series resistance changes the trip point noticeably.
3) Clamp injection (protection conduction and recovery)
Near a rail, protection paths can begin to conduct (even before absolute limits are violated if fast transients or overshoot exist). That conduction injects current into the input node, which can create step-like threshold errors and slow recovery. Bench clue: a sudden trip-point step, occasional wrong polarity, or an output that “comes back late” after a transient.
Symptom → likely cause → first checks (triage table)
Symptom
Most likely cause
First checks
Trip point drifts smoothly near a rail
Input-stage nonlinearity
Sweep VCM; compare VDD corners; avoid operating too close to the boundary.
Trip point changes when divider values change
Ib × Rs error
Reduce Rs or buffer the source; check bias/leakage vs VCM notes/curves.
Sudden step errors, wrong blips, slow recovery after transients
Clamp injection / crossover knee
Look for input overshoot and clamp conduction; add/adjust current limiting; move VCM away from knees.
Minimal debug sequence (fast and repeatable)
  1. Check whether the input waveform shows overshoot/undershoot that could start clamp conduction.
  2. Estimate whether Ib × Rs can explain the observed trip shift (repeat with a different divider value or added series R).
  3. Sweep VCM across the operating range and record trip point and delay; mark any knee/step as a risk zone.
Threshold error budget near rails: offset shift, Ib×Rs, and clamp injection Stacked bar diagram showing three contributors to threshold error near rails: offset shift, Ib×Rs, and clamp injection, with short action hints for each. Near-rail threshold error budget (conceptual) Offset shift Ib × Rs Clamp inj. move VCM avoid knees reduce Rs buffer source limit current avoid clamp If behavior shows step errors or slow recovery, prioritize clamp injection and crossover knees first.

Overdrive meets VICR: when “it should be fast” becomes “it becomes wrong”

Large overdrive can reduce delay, but it can also push one input (or the input common-mode) into a region where behavior is no longer guaranteed. The most common failure mode is not “slow” — it is wrong: brief wrong polarity, double toggles, or long recovery after a transient. Treat overshoot/undershoot as part of the VICR budget, not as a harmless detail.

What overdrive can trigger at the VICR boundary
  • VICR exit: one input is forced near/over a rail → input stage leaves its guaranteed region.
  • Clamp conduction: protection paths conduct → injected current disturbs the input node.
  • Saturation & recovery: internal nodes saturate → output recovers late even after the input returns.
Typical consequences on real waveforms
  • Wrong polarity blip: output briefly moves in the opposite direction before settling.
  • Short “invalid” window: output toggles twice (or produces a runt pulse) around the crossing.
  • Delay becomes longer: despite larger overdrive, internal recovery dominates timing.
  • Recovery tail: after a transient, the next switching event is late or inconsistent.
Scope-level verdicts (symptom → likely VICR/clamp trigger)
What appears on the scope
Likely cause
First action
VIN shows overshoot/undershoot near a rail; waveform looks “clipped”
Clamp conduction / injection
Add/adjust current limiting and damping; reduce overshoot before blaming noise.
Output shows a short wrong-direction blip or double toggle
VICR exit or saturation recovery
Move operating VCM away from near-rail/crossover; verify with VCM sweep at corners.
Larger overdrive makes timing worse (delay grows or spreads)
Internal recovery dominates
Reduce rail hits and clamp conduction; confirm recovery by repeating after a controlled transient.
Minimal fixes (VICR-focused)
  1. Control overshoot/undershoot so neither input is forced into rail-hit conditions.
  2. Limit clamp current and reduce source impedance sensitivity (avoid turning injection into a threshold shift).
  3. Keep operating VCM away from near-rail and crossover knees; validate with a VCM sweep at corners.
Overdrive and overshoot can trigger clamp current and create invalid output behavior Waveform diagram showing VIN with an overshoot spike near a rail, a clamp current arrow, and VOUT with an invalid highlighted region indicating wrong polarity or double toggles. VIN (overshoot) Clamp current VOUT overshoot Clamp current invalid

Crossover under overdrive: what changes (offset/noise/delay) and how to de-risk

RR-input crossover is where two input stages share (or hand off) control. Under large swings and real-world noise, the crossover zone can amplify condition-dependence: offset may step, noise/jitter may rise, and delay may show a knee. Treat crossover as a region to avoid, or to measure and guardband.

What can jump in the crossover zone
  • Offset step: trip point vs VCM shows a knee or a small step.
  • Noise / edge jitter rise: repeated toggles become easier on slow or noisy crossings.
  • Delay knee: delay vs VCM becomes slower or more variable in a narrow band.
Risk amplifiers (why the same part behaves “fine” on one board and not another)
  • Slow input slope: the input spends longer near threshold → noise and crossover variation matter more.
  • High source impedance: bias/leakage changes become Ib × Rs threshold shifts.
  • Noisy common-mode: ripple pushes the operating point through the knee repeatedly.
  • Open-drain pull-up too large: output edges become slow → timing becomes more condition-dependent.
De-risk priority list (do these in order)
Level 1 — move the operating point
Move the nominal VCM away from the crossover knee and near-rail margins; include ripple and transient peaks in the VCM envelope.
Level 2 — fix the front-end conditions
Lower source impedance or buffer the source; control slope and ringing; limit rail-hit events and clamp current.
Level 3 — adjust the device choice
Choose a comparator with smoother crossover behavior or different input architecture when the operating VCM must live near the knee.
VCM vs performance regions: safe, crossover risk, and undefined Heat-zone diagram with VCM on the horizontal axis and three colored regions labeled Safe, Crossover risk, and Undefined, plus an operating point marker and minimal labels for offset, noise, and delay. Undefined Safe Crossover risk Undefined offset noise delay Operating VCM move away from knees VCM (VSS → VDD) VSS VDD

Design patterns to keep inputs inside VICR

Keeping inputs inside VICR is about managing the VCM envelope (including ripple and spikes), not just the average value. The most reliable approach is to use simple, repeatable front-end patterns that keep the common-mode away from near-rail and crossover knees, and that prevent clamp injection from turning transients into threshold errors.

Practical principles (VICR-focused)
  • Budget VCM envelope: include ripple, ringing, and probe-induced overshoot.
  • Reduce sensitivity to bias/leakage and injection: avoid turning small currents into large threshold shifts.
  • Prefer move VCM and limit spikes before changing devices.
Divider
Divider (+ optional buffer)
What it solves: compresses high input levels into a VICR-safe window. Hidden failure mode: high divider impedance turns bias/leakage or injection into a threshold shift. Fast check: keep the same ratio but change total resistance; a trip shift indicates sensitivity. Best-practice knob: lower source impedance or buffer the divider node when thresholds must be stable.
Bias
Mid-supply common-mode bias
What it solves: shifts AC or floating signals into a stable VCM zone away from rails and crossover. Hidden failure mode: bias node rides supply ripple and repeatedly crosses a knee. Fast check: observe the bias node under load and ripple; large movement indicates risk. Best-practice knob: make the bias source low-impedance and filterable; reserve margin for peaks.
Clamp + R
Current-limited clamp (series R first)
What it solves: prevents rail-hit transients from creating long recovery and wrong toggles. Hidden failure mode: clamp conduction injects current and disturbs the threshold when current is not limited. Fast check: clipped VIN and an “invalid” output window strongly suggest clamp/injection. Best-practice knob: limit current with series R; treat spikes as part of the VICR envelope.
Three design patterns to keep comparator inputs inside VICR Three-column block diagram showing divider, mid-supply bias network, and current-limited clamp with series resistor, each with minimal labels and arrows to the comparator input. Divider Bias network Clamp + R VIN R1 R2 to IN AC to IN Vmid bias VIN Rs clamp to IN

Bench verification: how to measure VICR and catch crossover issues fast

VICR verification becomes repeatable when it is treated as a scripted sweep: hold ΔVIN, sweep VCM, and log trip point, delay, and any “invalid” behavior. Add a controlled transient to reveal clamp conduction and recovery issues.

Minimal sweep script (repeatable)
  1. Fix ΔVIN (small and stable), then sweep VCM across the intended envelope.
  2. At each VCM point, log trip point, tdelay, and anomalies (double toggles, wrong blips, slow recovery).
  3. Repeat at VDD corners and key temperatures; repeat for different pull-up and source impedance values.
  4. Inject a controlled spike/step to check clamp conduction and recovery.
Minimal test log schema (copyable checklist)
Settings
VDD, temperature, pull-up value, load, source impedance, probe type/grounding, bandwidth limits
Sweep plan
VCM start/stop/step, sweep rate, samples per point, ΔVIN level, injection type (step/spike)
Measurements
Trip point vs VCM, tdelay (min/typ/max or distribution), anomaly counts, VIN clipping/rail-hit evidence
Notes
Any knee/step region, recovery tails, correlation with probe changes, correlation with pull-up or Rs changes
Bench setup to sweep VCM, inject transients, and log trip point and delay Test bench block diagram showing signal source, VCM bias/sweep block, comparator DUT, pull-up/load, power supply, and oscilloscope, with arrows indicating sweep and logging paths. Signal source VCM / Bias Comparator DUT IN+, IN− OUT Pull-up / Load Oscilloscope Power supply sweep VCM inject step/spike log trip & tdelay

Layout & grounding for VICR integrity

VICR violations can be created by the PCB even when the source signal is “in range”. Ground bounce and return-path mistakes shift the local reference of the input pins, creating an effective common-mode jump that can push operation into a crossover knee or an undefined near-rail region. Keep input symmetry, return paths, and clamp loops clean and local.

What matters most (VICR-focused)
  • Input symmetry: keep IN+ / IN− (or IN and its reference) matched and close.
  • Short loops: define a short, quiet return path so the input reference does not jump.
  • Pull-up return: route open-drain pull-up current without sharing impedance with the input reference.
  • Clamp loop placement: place series-R and clamps so transient current does not inject into the input reference.
Layout review checklist (10 items; VICR-only)
  1. Keep input paths symmetric and tightly coupled (avoid one input “seeing” a different environment).
  2. Keep the input loop short: signal + return path must be close and predictable.
  3. Avoid high di/dt return current crossing near the input reference region (prevent effective VCM jumps).
  4. Define open-drain pull-up return paths; do not let pull-up current share impedance with input ground/reference.
  5. Prevent output switching currents from flowing through the same necks/vias used by input reference.
  6. Place decoupling close to VDD pins and connect to a quiet return (reduce supply-driven common-mode motion).
  7. Place series-R close to the comparator input (limit spike current at the sensitive node).
  8. Route clamp/TVS current loops away from the input reference; keep the clamp loop local to its entry point.
  9. Keep bias (Vmid) networks low-impedance and locally referenced; avoid long “antenna” bias returns.
  10. Use measurement-friendly test points: minimize probe ground lead inductance to avoid creating ringing.
PCB routing sketch: input symmetry, return paths, pull-up loop, and clamp loop risk zones Top-down PCB-style block diagram showing input routing to a comparator, pull-up loop, and clamp loop with highlighted risk zones where ground bounce or injection can create effective common-mode jumps. Input region Comparator DUT Pull-up R + VDD Clamp Rs + TVS IN+ IN− Return bad return ground bounce risk zone clamp loop injection zone

Engineering checklist (requirements → risk → test)

Turn VICR into an engineering object: define requirements as envelopes, map them to concrete failure risks, and verify with scripted tests. This checklist is designed to be copied into a project template so VICR is not left as an assumption.

Workflow in one line
Requirements → VICR budget → Choose topology → Bench verify → Guardband
Field → risk → verification (project template table)
Requirement field
Risk if wrong
Verification
VDD min / max
VICR boundary shifts; knee moves
VCM sweep at VDD corners; log trip & tdelay
Input range (DC + peaks)
Near-rail exit; clamp conduction
Spike/step injection; check VIN clipping and recovery
VCM nominal + ripple
Repeated knee crossings; jitter rise
VCM sweep with ripple present; count anomalies
Source impedance (Rs / divider R)
Ib×R and injection sensitivity; trip shifts
Ratio-fixed R sweep; observe trip movement
Input slope / bandwidth
Slow-crossing chatter; multi-toggles
Slow-slope test; measure toggle count statistics
Output type & pull-up
Edge slows; timing becomes condition-dependent
Pull-up sweep; log rise time and tdelay distribution
Temperature range
Knee moves; offset/drift changes
Temp sweep in/around knee region; compare trip stability
Clamp strategy (internal/external)
Injection and recovery tails; wrong blips
Injection test; compare with/without series-R; confirm recovery
Layout return constraints
Effective VCM jump; anomalies appear only on board
A/B test return paths; correlate anomalies with pull-up/di/dt changes
Guardband policy
Marginal operation at corners
Add margin to VCM envelope; re-test at corners and with spikes
Engineering workflow from requirements to guardband for VICR Flowchart showing five steps: Requirements, VICR budget, Choose topology, Bench verify, and Guardband, connected by arrows with minimal labels. Requirements corners VICR budget envelope Choose topology Bench VCM sweep Guard band Key idea Treat VICR as an envelope problem: include ripple and spikes, verify knees, then add margin.

Applications (VICR lens only)

These scenarios fail in predictable ways under a VICR lens: near-rail headroom loss, RR crossover knees, slow edges under pull-ups, and clamp/injection during transients. Each item below maps an application to a common VICR pitfall and one avoidance move.

Low-VDD
1.8V / 3.3V battery thresholds (near-rail)
VICR pitfall: the threshold sits close to a rail at low VDD; input-stage headroom collapses and the effective knee shifts with VDD/temperature.
What to watch: guaranteed VICR vs typical curves; any near-rail notes/conditions.
One avoidance move: keep the threshold’s VCM envelope away from rails (bias/divider margin), or choose a device whose VICR includes small beyond-rail margin.
AC
Zero-cross (with bias) and crossover avoidance
VICR pitfall: the bias point drifts or rides ripple and repeatedly crosses an RR crossover knee; jitter/delay can jump in a narrow VCM band.
What to watch: offset/tdelay vs VCM behavior around crossover; knee width and conditions.
One avoidance move: move VCM away from the knee and add small hysteresis to prevent slow-slope chatter through the knee.
Long line
Open-drain sensors / long cables (slow edge + VCM drift)
VICR pitfall: pull-up + cable capacitance slows edges; return-path noise and ground bounce create an effective VCM jump.
What to watch: OD pull-up conditions, logic-level compatibility, and board-level reference stability.
One avoidance move: control pull-up return paths and shape slow edges (Schmitt cleanup) while keeping inputs inside the VICR envelope.
HV sense
High-voltage divider detection (clamp current effects)
VICR pitfall: high impedance dividers make clamp/injection currents translate into large threshold shifts; recovery can stretch after transients.
What to watch: allowed over/under-rail voltage and input current limits; recovery conditions.
One avoidance move: limit clamp current (series R near the input) and keep nominal operation away from near-rail undefined zones.
Applications likely to hit VICR limits: four-card overview A four-quadrant grid of application cards: low-voltage threshold, zero-cross with bias, open-drain long cable, and high-voltage divider with clamp current, each shown as a small block diagram with minimal labels. Low-VDD threshold Zero-cross + bias Open-drain long line HV divider + clamp Battery Divider Comp Near-rail AC Vmid bias Comp Crossover Sensor OD Pull-up Schmitt Slow edge HV Divider Clamp+R Clamp current

IC selection logic (VICR-focused) + vendor questions

VICR selection is an envelope-and-corners problem. Start from the input envelope (including ripple and spikes), verify worst-case VICR, characterize RR crossover behavior, then check over/under-rail events and recovery. Only after VICR risks are closed should delay, power, and output style dominate.

VICR-first selection flow (short)
  1. Define the envelope: VDD corners, VCM nominal + ripple, peak/spike levels, source impedance, temperature range, and output pull-up conditions.
  2. Match guaranteed VICR: confirm worst-case VICR under stated conditions (not only typical curves).
  3. RR needs crossover proof: identify the crossover region and confirm offset/tdelay behavior is acceptable through the envelope.
  4. Over/under-rail events: check allowed input voltage/current during transients, and confirm recovery behavior after clamp/saturation.
  5. Finalize: choose output type (OD vs push-pull), then budget delay and power with the VICR risks already closed.
Vendor question template (copy/paste fields)
Field to confirm
Required detail (conditions / worst-case)
Guaranteed VICR range
Provide min/max VICR with VDD, temperature, ΔVIN/overdrive, output state/load, and notes that change limits.
Crossover characterization (RR)
Provide the crossover region width and worst-case offset/tdelay behavior vs VCM through that region.
Over/under-rail tolerance
Provide allowed input voltage range beyond rails and the maximum input current during those events; include any “no phase inversion” conditions.
Recovery time
Provide recovery time from saturation/clamp back to valid decisions, with test stimulus, source impedance, and pull-up/load conditions.
Input bias/leakage vs VCM
Provide worst-case bias/leakage in the operating VCM window, especially near rails and around crossover (critical for high-impedance dividers).
Output constraints (OD / push-pull)
Provide output swing, pull-up voltage limits (OD), drive limits, and any conditions that change delay/jitter behavior.

Reference examples (starting points; verify VICR conditions)

These part numbers are provided to speed up datasheet lookup and lab verification. Selection should follow the VICR-first flow above, using worst-case conditions and guardband for the specific envelope.

Low-power / near-rail margin
TI TLV3691 (nano-power class; VICR may extend slightly beyond rails — confirm conditions), Microchip MCP6541 (low-power RR input family), TI TLV3011B / TLV3012B (integrated reference; useful for power-on thresholds — confirm VICR notes).
Wide-supply + OD output (field wiring / dividers)
TI TLV1701 (wide supply; OD output; check near-rail and over/under-rail behavior for the envelope).
High-speed / timing-sensitive
ADI LTC6752 (high-speed family; verify RR crossover and overdrive conditions in the target VCM envelope).
Schmitt cleanup (slow edges / noisy lines)
TI SN74LVC1G17 (Schmitt buffer), TI SN74LVC1G14 (Schmitt inverter), Nexperia 74LVC1G14 (Schmitt inverter). Confirm input voltage limits and ensure the input node remains within allowed ranges under spikes.
Counterexample (do not assume RR / near-rail safety)
ADI LTC1440 — a useful reminder that many low-power comparators do not accept full near-rail common-mode. Always confirm VICR limits and conditions.
VICR-focused selection decision tree Vertical decision flow: define input envelope, verify worst-case VICR, decide if rail-to-rail is needed, evaluate crossover acceptability, check over/under-rail events and recovery, select output type, then guardband and bench verify. Input envelope defined Worst-case VICR OK Need rail-to-rail input Crossover acceptable knee Over/under-rail & recovery Select output + guardband

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FAQs (VICR / near-rail / crossover)

Short, actionable answers only. Each item is structured as: Likely cause → Check → Quick bench test → Fix → Guardband. No new theory is introduced beyond VICR, near-rail behavior, RR crossover, overdrive/clamp effects, and measurement traps.

Why does the same comparator look “more threshold-drifty” at 1.8V? Which two VICR conditions should be checked first?
Likely cause (ranked): (1) VICR headroom shrinks at low VDD; (2) RR crossover knee moves into the operating VCM; (3) output/load state changes internal bias.
Check (2 items): (a) Guaranteed VICR limits at VDD(min) + temperature corners; (b) notes/curves for VICR or tdelay/offset vs VCM near rails.
Quick bench test: run a VCM sweep at 1.8V and 3.3V with the same ΔVIN; log trip point and tdelay vs VCM.
Fix (1–2 actions): move the operating VCM away from rails (bias/divider margin), or choose a part with a wider guaranteed VICR at low VDD.
Guardband note: define the VCM envelope including ripple and keep it inside the guaranteed VICR with margin at corners.
When VIN approaches VDD and occasional “wrong polarity / false decision” appears, is it VICR exit or clamp current? How to tell quickly?
Likely cause (ranked): (1) clamp/injection current distorts the input node; (2) input stage saturates outside VICR; (3) ground bounce creates an effective VCM jump.
Check (2 items): (a) input over/under-rail allowance and max input current; (b) any “undefined” near-rail region notes and recovery behavior conditions.
Quick bench test: add a small series resistor near the input and repeat the event; if behavior improves strongly, clamp/injection is likely dominant. Then repeat with a VCM sweep to see if a hard “dead zone” exists.
Fix (1–2 actions): limit clamp current (series-R at the pin, controlled clamp loop), and/or keep the nominal VCM farther from the rail.
Guardband note: treat spikes as part of the envelope; validate recovery time under the worst spike + source impedance.
Does an RR input always have a crossover region? Where is it most likely to be revealed in a datasheet?
Likely cause (ranked): (1) dual input-pair handoff creates a knee; (2) internal bias transitions change offset/noise/delay; (3) knee width shifts with VDD/temperature.
Check (2 items): (a) typical curves for VOS/tdelay vs VCM or “input stage transition”; (b) notes mentioning “crossover”, “transition region”, or conditions that change VICR behavior.
Quick bench test: sweep VCM with fixed ΔVIN and plot trip point + tdelay; a knee shows up as a localized jump.
Fix (1–2 actions): place nominal VCM away from the knee; add small hysteresis to avoid repeated knee crossings under noise/slow slopes.
Guardband note: guardband must cover knee drift across VDD/temperature corners, not just typical room data.
Slow input slopes cause multiple toggles. Is it insufficient hysteresis or entering crossover?
Likely cause (ranked): (1) hysteresis too small for the noise at the input; (2) slow slope crosses a knee repeatedly under ripple; (3) reference/ground bounce modulates VCM.
Check (2 items): (a) hysteresis value vs expected input noise; (b) whether the operating VCM sits near a crossover/near-rail region in curves/notes.
Quick bench test: repeat with a slightly faster slope and again with a slightly shifted VCM; if toggles vanish mainly with VCM shift, crossover/knee is likely involved.
Fix (1–2 actions): increase hysteresis modestly and/or move VCM away from knee; reduce source impedance if the input node is sensitive.
Guardband note: validate the worst-case slope + noise combination over temperature and VDD(min).
A large open-drain pull-up resistor causes mis-triggers. How is that related to VICR?
Likely cause (ranked): (1) slow output edge increases time in the transition zone (system-level chatter); (2) pull-up return path injects ground bounce; (3) VCM envelope is widened by noise coupling.
Check (2 items): (a) pull-up conditions used for timing specs; (b) board return path for pull-up current relative to the input reference region.
Quick bench test: reduce pull-up (faster edge) and compare mis-trigger probability; then move the pull-up return to a cleaner point and re-test.
Fix (1–2 actions): choose pull-up for edge-rate needs, and control return paths so effective VCM does not jump into knee/near-rail regions.
Guardband note: include pull-up tolerance and cable capacitance as part of the envelope and validate at extremes.
After increasing divider resistors, the threshold drifts. Is it input bias current or VICR headroom?
Likely cause (ranked): (1) Ib/leakage × R creates a DC shift; (2) near-rail headroom or knee changes the effective input behavior; (3) clamp/injection currents during small transients create additional error.
Check (2 items): (a) worst-case input bias/leakage vs VCM/temperature; (b) VICR guarantee limits and near-rail notes in the operating envelope.
Quick bench test: keep the same ratio but scale divider resistors down (e.g., ×0.1) and compare trip shift; strong scaling indicates Ib×R dominance.
Fix (1–2 actions): lower divider impedance or buffer the divider; also keep nominal VCM away from near-rail/knee regions.
Guardband note: use worst-case Ib/leakage and temperature corners, not typical room values.
VIN goes a few hundred millivolts beyond a rail and nothing breaks. Why can recovery still be very slow?
Likely cause (ranked): (1) input clamp/injection charges internal nodes; (2) input stage saturates and needs time to re-bias; (3) external clamp loop stores charge and releases slowly through high impedance.
Check (2 items): (a) max allowed input current during over/under-rail; (b) recovery time spec/notes and the stated stimulus/source impedance.
Quick bench test: repeat with controlled series-R and different source impedance; recovery that scales with current/impedance indicates injection/saturation recovery.
Fix (1–2 actions): limit over-rail current (series-R near pin) and reduce high-impedance paths that stretch discharge; keep nominal operation away from rails.
Guardband note: validate recovery at the worst spike amplitude and repetition rate that can occur in the system.
How does a VCM sweep quickly locate an “unusable common-mode zone”?
Likely cause (ranked): (1) VICR exits near rails; (2) RR crossover knee creates localized instability; (3) board reference motion creates apparent dead zones.
Check (2 items): (a) test conditions for tdelay/offset specs (ΔVIN, load, VDD, temperature); (b) whether datasheet provides VCM-related curves or notes.
Quick bench test: fix ΔVIN (small but stable), ramp VCM slowly across the expected envelope, and log: trip point, tdelay, anomalies (wrong pulse, missing toggle, extra toggles).
Fix (1–2 actions): choose an operating VCM window that avoids the bad region; if needed, re-center VCM (bias) or select a part with a wider guaranteed VICR.
Guardband note: repeat at VDD(min) and hot/cold corners; the bad region can move significantly.
Can probes/fixtures push common-mode into crossover? How to avoid measurement false positives?
Likely cause (ranked): (1) probe ground lead inductance creates ringing; (2) fixture capacitance changes edge shape and shifts effective VCM; (3) ground reference is taken from a noisy point.
Check (2 items): (a) probe connection method (spring ground vs long lead); (b) whether anomalies correlate with probe placement or ground point.
Quick bench test: repeat the same capture using a short ground spring and a different ground reference point; if the anomaly moves/disappears, it is measurement-induced.
Fix (1–2 actions): minimize loop area in probing, use differential probing when possible, and keep fixture capacitance predictable.
Guardband note: confirm results with at least two probing methods before labeling a VICR failure.
Datasheet says VICR reaches the negative rail, but the low end is still abnormal. What are common reasons?
Likely cause (ranked): (1) the spec is conditional (ΔVIN, load, output state) and conditions are not met; (2) ground bounce shifts the local “negative rail”; (3) input protection/injection near ground distorts the node.
Check (2 items): (a) the exact test conditions/notes for the VICR statement; (b) layout/return path for input reference and pull-up/load currents.
Quick bench test: verify with a VCM sweep at the same conditions as the datasheet (or as close as possible), then repeat with a cleaner ground reference and shorter return paths.
Fix (1–2 actions): meet the stated conditions (source impedance/load), improve return paths to reduce local reference shift, and avoid clamp current injection at the input pin.
Guardband note: treat the negative-rail claim as conditional unless guaranteed across corners with explicit conditions.
Datasheet says “rail-to-rail input”. Why can crossover risk still exist?
Likely cause (ranked): (1) RR often means coverage by two input pairs; (2) the handoff region can change offset/noise/tdelay; (3) knee drift with VDD/temperature makes a “safe” bias become marginal.
Check (2 items): (a) any VOS/tdelay vs VCM curves; (b) notes describing transition/crossover behavior.
Quick bench test: sweep VCM through the intended envelope and look for localized jumps in trip/tdelay spread.
Fix (1–2 actions): avoid biasing the signal around the knee; add small hysteresis if the envelope must pass nearby.
Guardband note: validate knee location at VDD(min) and temperature extremes, not only at nominal room.
How much VICR margin is “enough” and how should guardband be defined?
Likely cause (ranked): margin is consumed by (1) VDD tolerance and ripple, (2) VCM ripple/ground bounce, (3) spike events and clamp/injection, (4) knee drift across temperature.
Check (2 items): (a) guaranteed VICR across VDD/temperature corners; (b) worst-case knee/near-rail behavior from curves or characterization data.
Quick bench test: build an envelope test: VCM sweep at VDD(min/max) + hot/cold and add representative spikes; measure the boundary where anomalies start.
Fix (1–2 actions): re-center VCM (bias/divider), reduce reference motion (return paths), and limit spike current (series-R) until the measured boundary is comfortably outside the operating envelope.
Guardband note: guardband is defined by the measured anomaly boundary minus the maximum operating envelope, at worst-case corners.
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