Power / eFuse Co-Design for Comparators: PG, Latch, Retry
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Power / eFuse co-design means defining a clear, testable contract from sense → detect → filter/blank → latch/retry → PG/FAULT, so protection stays fast without false trips and recovery is predictable across no-load, inrush, and real shorts.
Use field names (VTH+/VTH−, VHYS, TBLANK, TQUAL, TDEGLITCH, I_TRIP, TON/TOFF, NRETRY) to turn “it hiccups” into measurable criteria, then verify on the bench.
Definition & system boundary: what “co-design” means here
Co-design means turning power protection into a verified signal contract: sense → compare → filter/blank → latch/retry → PG/FAULT/EN → load, with clear ownership, timing windows, and pass/fail criteria.
System boundary (scope contract)
- PG/FAULT/EN/RESET semantics, ownership rules, and race-condition prevention.
- No-load vs light-load vs short criteria expressed as threshold + time window.
- Deglitch / blanking / qualification windows that balance fast protection and noise immunity.
- Fault latching and retry policies (when to latch off vs auto-retry, how to qualify “success”).
- Verification hooks: what to probe, what to trigger on, and what “pass” means.
- eFuse internal power-stage details (SOA/thermal modeling/foldback implementation).
- Full EMI/ESD standards deep-dives (only the effect on thresholds and timing is covered).
- End-to-end functional safety processes (only traceable fields + bench tests are covered).
Interfaces & required inputs (the minimum dataset)
Treat signals as a design API. Define names, logic levels, timing, and ownership before picking parts or drawing schematics.
- PG (power-good state), FAULT/FLT (fault event), EN (command), RESET (re-arm / clear-latch).
- VSENSE / IMON (current/voltage sensing), TIMER (time constant / blanking), BLANK (startup ignore window).
- LATCH (fault hold-off), RETRY (auto-restart policy), UVLO/OVP/OCP (threshold causes).
| Field | Unit | Why it matters |
|---|---|---|
| Vrail range | V | Sets PG window and divider accuracy needs. |
| Iload profile | A vs t | Separates light-load dips from true shorts. |
| Inrush | A, ms | Defines blanking + deglitch windows. |
| Allowed dip | V, ms | Prevents PG chatter from load steps. |
| MCU reaction time | ms | Decides hardware-autonomy vs mixed ownership. |
Output of H2-1 should be a single, testable sentence: “If condition X persists for time Y, action Z must occur within time W, and PG/FAULT must reflect it consistently.”
Diagram focus: the power path is separate from the protection logic path. Co-design aligns thresholds, windows, and ownership so PG/FAULT/EN behave deterministically under load steps, inrush, and faults.
Signal taxonomy: PG / FAULT / EN / RESET and ownership rules
PG is a state; FAULT is an event
- Represents a stable power window (valid operating state).
- Requires hysteresis and qualification time to avoid chatter.
- Should be designed for predictable deassert during dips.
- Represents a detected incident (something happened).
- May require capture of short pulses and latch for reporting.
- Should be tied to cause tags (OCP/OVP/UV/OT) whenever possible.
Ownership rules (who decides what)
Every system must explicitly assign ownership for protection action (turn-off / retry) and reporting (logging / telemetry). Unassigned ownership creates race conditions and “PG says OK while hardware is already shutting down.”
- Hardware detects; MCU decides latch/retry timing.
- Risk: slow reaction or firmware stalls can allow repeated brownouts.
- Hardware detects and enforces latch-off or retry without firmware.
- Risk: a noise spike can cause persistent latch-off if re-arm is not defined.
- Hardware handles fast shutoff; MCU controls retry policy and logging.
- Key requirement: define RESET/REARM semantics and success qualification.
Open-drain ORing (wired-OR) and the signal contract table
Open-drain ORing is ideal for multi-source faults and cross-voltage domains, but it must be treated as a shared resource: define the pull-up, rise time, and “release” rules, or the line will appear “stuck low” during debugging.
| Signal | Type | Typical owner | Must define |
|---|---|---|---|
| PG | State | Hardware | VPG_RISE, VPG_FALL, VHYS, TQUAL, TPG_DELAY |
| FAULT/FLT | Event | Mixed | Cause tags, FAULT_MIN_PULSE, TDEGLITCH, TLATCH, TREPORT |
| EN | Command | MCU/PMIC | Polarity, gating rules, startup blanking, max disable latency |
| RESET / REARM | Command | MCU/PMIC | Min pulse width, safe re-arm condition, success qualification |
Diagram focus: multiple fault causes can share one open-drain line, but the pull-up and release rules become part of the system contract. Ownership is enforced by where EN/RESET enter the latch/retry block.
Common failure patterns to prevent early
- PG chatter: PG toggles during load steps because VPG_RISE/VPG_FALL and TQUAL were never defined.
- Event lost: FAULT is a short pulse that firmware misses; TLATCH or minimum pulse capture is required.
- Stuck-low wired-OR: one device keeps the OD line asserted; without cause tags and pull-up sizing, debug becomes guesswork.
- Ownership race: MCU asserts EN while hardware is deasserting it; add gating rules and define max disable latency.
PG interactions: sequencing, race conditions, and “PG chatter”
PG is only useful when it behaves like a state: stable, qualified, and aligned with system actions. “PG chatter” is repeated PG toggling caused by rail crossings, noise injection, or sequencing races.
Three root causes, each with a measurable signature
- Signature: PG toggles track rail noise near the threshold.
- Fast check: overlay Vrail and PG; toggles occur at the same crossing point.
- Fix class: define VPG_RISE and VPG_FALL (VHYS) instead of one threshold.
- Signature: PG toggles correlate with high di/dt switching (load steps, PWM edges).
- Fast check: probe at the comparator input node vs rail; toggles originate at the sense node.
- Fix class: deglitch/qualification plus routing that keeps the sense node out of power return currents.
- Signature: a load enable or mode change produces a dip that crosses VPG_FALL, then recovers.
- Fast check: capture the event with a trigger on the load-control edge + rail minimum.
- Fix class: qualify PG as “valid” only after TQUAL, and stage system actions after PG is stable.
The classic PG race: “PG=1 → action → PG=0”
A race occurs when a system action is triggered on a non-qualified PG edge. The action itself changes the load state, pushing the rail back through the PG window and invalidating the decision.
- Do not use a raw PG edge to immediately enable a heavy load stage.
- Gate actions with PG_valid = (PG in window for TQUAL) and optionally a second condition (e.g., current below a limit).
- Define a maximum disable latency: when PG deasserts, the system must stop the dependent action within a known time.
- Prefer staged enabling: Stage-1 (soft start) → verify stability → Stage-2 (full load).
Mitigation ladder: VHYS → TBLANK → TQUAL
- Goal: prevent repeated toggles near the threshold.
- Definition: VPG_RISE and VPG_FALL create a window instead of a point.
- Tradeoff: larger VHYS can delay undervoltage recognition and narrow the “valid” region.
- Goal: ignore known “dirty windows” (startup, mode switches).
- Constraint: blanking must be phase-bounded and never hide real faults indefinitely.
- Tradeoff: too long TBLANK can mask a real short during startup.
- Goal: make PG a true state signal (stable long enough to trust).
- Rule: PG asserts only after the rail remains in the valid window for TQUAL.
- Tradeoff: longer TQUAL increases startup confirmation time.
Required parameter fields (PG contract)
| Field | Meaning | Typical use |
|---|---|---|
| VPG_RISE | PG assertion threshold (upper edge of the valid window). | Prevents early “PG=1” during ramps. |
| VPG_FALL | PG deassert threshold (lower edge of the window). | Defines allowable dip before PG drops. |
| VHYS | Hysteresis width (VPG_RISE − VPG_FALL or equivalent). | Stops chatter at the crossing. |
| TBLANK | Time window during which PG transitions are ignored. | Startup / mode-change immunity. |
| TQUAL | Required continuous in-window time before PG asserts. | Converts PG into a state, not a pulse. |
| TPG_DELAY | Intentional output delay (if used) to suppress brief toggles. | Aligns PG timing with system sequencing. |
If Vrail stays above VPG_RISE continuously for TQUAL, PG shall assert once and remain stable; if Vrail drops below VPG_FALL, PG shall deassert within TPG_DELAY, and dependent actions shall stop within the system’s maximum disable latency.
Diagram: PG chatter timing — bad vs qualified behavior
The “good” lane shows the minimum structure: two thresholds (VTH+/VTH−), a bounded blanking window (TBLANK), and a qualification time (TQUAL). This converts PG into a stable state and prevents sequencing races.
Comparator/Schmitt implementation patterns for PG and fault detect
Fast decision rules (choose the structure first)
- If absolute threshold accuracy and repeatability matter, use Precision comparator + external hysteresis.
- If the input is slow, noisy, or “logic-like” and a clean edge is needed, use an RR Schmitt-trigger buffer.
- If short glitches must be rejected and the output must be a clean logic signal, use Comparator + RC + Schmitt (filter then shape).
Three reusable patterns (PG or fault detect)
- Best for: accurate UV/OV/PG windows and stable thresholds across temperature.
- Key fields: VTH+, VTH−, VHYS, Rfb, Rin.
- Common trap: divider/source impedance shifts thresholds (bias/leakage × R).
- Best for: slow ramps, long wires, and “dirty” signals that must become clean logic edges.
- Key fields: VTH+ / VTH− from datasheet, plus input clamp/series resistance if needed.
- Common trap: fixed thresholds may be too loose for precision PG windows.
- Best for: rejecting short glitches while still producing a sharp logic output.
- Key fields: R·C, TDEGLITCH, min-pulse-to-catch, plus TPG_DELAY alignment.
- Common trap: RC increases delay; excessive RC can worsen sequencing races.
Output type: open-drain vs push-pull (treat as a system constraint)
- Best for: wired-OR fault aggregation and cross-voltage domains.
- Must define: Rpu, line capacitance, and a rise-time budget.
- Common trap: “stuck low” lines when one device keeps asserting or pull-up is undersized.
- Best for: clean edges without pull-ups; stronger drive for direct logic inputs.
- Must define: level compatibility and fault-sharing rules (no wired-OR by default).
- Common trap: multi-source lines collide unless explicitly gated.
Diagram: three PG-generation chains (structure templates)
Use these as templates. Each chain must still satisfy the PG contract: VHYS, bounded blanking, and qualification where required by sequencing risk.
Threshold accuracy budget: divider, bias current, hysteresis error, and drift
Threshold errors become deterministic once every contributor is written as a budget term. The goal is a worst-case ΔVTH contract that predicts field behavior across temperature, humidity, and board contamination.
Root causes (what moves the real threshold)
- R tolerance and ratio mismatch shift VTH directly.
- Temperature coefficient mismatch changes the ratio with temperature.
- Parasitic leakage across the divider node acts like an extra resistor.
- Ib × Req: input bias current creates a voltage error on the divider node.
- Ileak × Req: ESD structures, board contamination, and moisture create leakage-driven offset.
- Higher divider resistance increases sensitivity to both Ib and Ileak.
- External hysteresis changes the node’s effective source impedance.
- VTH+/VTH− can shift when the input source has non-negligible Rsrc.
- Over-sized hysteresis can move system boundaries (e.g., PG/UV windows).
Budget template (fieldized, worst-case friendly)
Define a worst-case threshold error as a sum of bounded contributors (do not assume cancellation).
- Rtop, Rbot, Req (node equivalent resistance).
- Ib_max at relevant VICR and temperature corners.
- Ileak_max (device + board surface + protection networks).
- Rratio_tol and Rratio_TC (ratio mismatch limits).
- VHYS_target and a defined injection topology (for ΔHYS_cpl).
- Treat Ib and leakage as same-direction error unless proven otherwise.
- Budget humidity/contamination as a leakage corner when high-value dividers are used.
- Budget temperature as both ratio drift and leakage/bias drift, not just one term.
When to lower the divider, add a buffer, or change the device
- Reduce divider resistance (lower Req).
- Use a lower-Ib comparator/input stage at the relevant common-mode range.
- Add a buffer if the divider must remain high value for power reasons.
- Lower divider impedance and reduce exposed node area.
- Improve cleanliness/coating strategy; treat board surface leak as a spec term.
- Re-evaluate protection networks that add leakage paths into the node.
- Re-check hysteresis injection point and the assumed source impedance (Rsrc).
- Prefer buffering when the input source is high impedance or varies across modes.
- Keep VHYS sized for noise/chatter control, not as a substitute for filtering/qualification.
Diagram: threshold network + error budget bar chart (terms only)
- Measure VTH at temperature corners and a “wet/dirty” board condition if high-value dividers are used.
- Confirm that the measured VTH range stays inside the system window with the planned hysteresis and qualification.
- Force leakage by adding a known high-value resistor to ground/rail and verify the predicted shift scales with Req.
Fault latching strategies: latched-off vs auto-retry vs foldback
Safety-first. A qualified fault forces OFF until a defined reset condition occurs.
Availability-first. Attempts recovery on a schedule; must control average dissipation to avoid thermal accumulation.
Power-limited protection. Reduces stress while trying to keep the rail partially alive (when the system tolerates derating).
Strategy selection map (system risk → recommended policy)
| System priority / risk | Recommended policy | Key parameters to lock |
|---|---|---|
| Human/asset safety, mandatory investigation | Latched-off | RESET_COND, LATCH_COND |
| Faults likely transient (plug-in, momentary short) | Auto-retry | RETRY_PERIOD, ON_TIME, COOLDOWN, N_RETRY_MAX |
| Thermal-limited system, stress must be bounded | Foldback or strict retry | I_LIMIT / P_LIMIT, ON_TIME, COOLDOWN |
| User experience sensitive to “hiccup” | Latched-off or limited retries | N_RETRY_MAX, RESET_COND, report/alert path |
Retry/latch timing contract (why “hiccup” happens)
- RETRY_PERIOD: overall cadence.
- RETRY_ON_TIME: how long the switch is enabled each attempt.
- COOLDOWN_TIME: off-time for thermal recovery.
- N_RETRY_MAX: cap the number of attempts before latching.
- RESET_COND: explicit clearing rule (EN toggle / MCU clear / power-cycle).
P_avg ≈ E_retry / RETRY_PERIOD
If average dissipation is not bounded, repeated retries accumulate heat even when each single attempt “looks safe”.
Diagram: latching vs retry state machine (timers and counters annotated)
- Confirm that TFAULT_MIN and the deglitch chain qualify only real faults (no spurious latch/retry).
- Measure retry waveform cadence and verify RETRY_PERIOD / ON_TIME / COOLDOWN match the contract.
- Compute or measure P_avg during retries and verify thermal behavior stays within limits before shipping.
- Verify the exact RESET_COND clears LATCH_OFF reliably across brown-out and MCU reset scenarios.
Retry tuning: no-load/short ambiguity, thermal cooldown, and exponential backoff
Retry should be treated as a closed-loop policy with a success contract and a stress limit. Without both, no-load/light-load can cause endless retries and hard shorts can periodically pull down the upstream bus.
Model retry as a 4-stage loop (not just ON/OFF)
Fault is accepted only after deglitch/qualification (TFAULT_MIN), preventing short spikes from entering retry.
Off-time protects the bus and the switch silicon. Backoff expands this window after repeated failures.
Each attempt has bounded energy via TON_RETRY; short bursts reduce bus droop and heat accumulation.
Success must be a multi-condition contract (VGOOD + time + current window) to avoid false success/fail under light-load behavior.
Success contract: three conditions that prevent endless retries
Vrail ≥ VGOOD_MIN. This guards against “near threshold” oscillation being treated as power-good.
Hold VGOOD continuously for SUCCESS_TQUAL. This blocks PG chatter and light-load ripple from flipping state.
Isense must return inside a defined I_WINDOW (or below I_NORM_MAX) to avoid treating an ongoing overload as a successful start.
Breaking the no-load vs short ambiguity (avoid infinite retries)
- Vrail reaches VGOOD quickly, then light-load behavior can create ripple or mode transitions.
- If success is based on an instantaneous PG/threshold, the state can flip: “success → fail → retry”.
- Fix: require SUCCESS_TQUAL and a current window (I_WINDOW) to avoid chasing benign ripple.
- Fail-to-start evidence: Vrail stays < VGOOD_MIN at the end of TON_RETRY.
- Escalation rule: after repeated fail-to-start, enforce NRETRY_MAX or longer cooldown.
- Goal: prevent periodic bus brownouts and heat accumulation under a persistent short.
Backoff options (fixed period vs exponential vs temperature-linked)
Simple and fast, but can periodically pull down the upstream bus under a hard short.
Increase TOFF after each failure using BACKOFF_FACTOR to reduce bus droop frequency and average dissipation.
Expand cooldown with temperature/thermal stress to prevent cumulative heating (especially for small packages or hot environments).
Recommended parameter fields (copy-ready contract)
| Field | Controls | Primary failure prevented |
|---|---|---|
| NRETRY_MAX | Maximum attempts before escalation | Endless retries on no-load/PG chatter |
| TON_RETRY | Energy per attempt | Bus droop and thermal accumulation |
| TOFF_COOLDOWN | Thermal and bus recovery time | Hiccup pulling the upstream rail down |
| BACKOFF_FACTOR | TOFF growth vs retry index | High-frequency retries under persistent faults |
| SUCCESS_TQUAL | Stable-good confirmation time | False success/fail from PG chatter or ripple |
Diagram: retry waveform and backoff (interval grows, stress drops)
Engineering checklist & verification hooks (scope/bench-ready)
Design review checklist (copy-ready)
- VTH+ / VTH− and VHYS documented as fields.
- Worst-case threshold budget closed (divider ratio, bias/leak, drift).
- Source impedance assumptions (Rsrc) validated for hysteresis coupling.
- TBLANK_START and TDEGLITCH_RUN bounded and justified.
- TFAULT_MIN and SUCCESS_TQUAL defined for state transitions.
- PG chatter conditions explicitly handled (threshold + time).
- PG assert/deassert conditions defined (window + qualification + delay).
- Open-drain pull-up voltage and wired-OR behavior verified.
- RESET_COND and LATCH_COND unambiguous across brown-out and MCU reset.
- Probe points identified: Vrail, VSENSE/IMON, PG, FAULT, EN.
- Scope triggers planned for PG edge and FAULT assertion.
- Any filtering that changes visibility is documented (RC, one-shot, timers).
Bench test hooks (repeatable injections)
- Hard short (instant).
- Soft short (ramped resistance).
- Intermittent short (pulsed).
- No-load → light-load → nominal load.
- Step load (fast edges) to trigger PG chatter conditions.
- Hold light-load ripple long enough to test SUCCESS_TQUAL.
- Startup into capacitive load (worst-case inrush).
- Startup with delayed load enable to test sequencing races.
- Capture blanking vs true short boundary (TBLANK_START).
- Trigger on PG falling edge and record Vrail around VTH− crossing.
- Trigger on FAULT assertion and measure TRESPONSE_MAX to switch-off.
- Trigger on EN toggle and verify timing to PG valid (with qualification).
Pass/Fail criteria fields (report-ready)
| Criterion field | Used in tests | What it proves |
|---|---|---|
| TRESPONSE_MAX | Short injection, fault steps | Protection reacts fast enough |
| N_FALSE_TRIP_MAX | No-load/light-load transitions, ripple | Debounce/qualification prevents spurious faults |
| TRECOVERY_MAX | Auto-retry success cases | System returns to normal within bounds |
| NRETRY_MAX | Persistent short cases | No endless retries under hard fault |
| SUCCESS_TQUAL | PG chatter capture / light-load ripple | Success is stable, not instantaneous |
Diagram: verification bench setup (PSU, e-load, short switch, scope triggers)
Layout & grounding for protection comparators (avoid ground-bounce false trips)
This section focuses only on threshold / comparator layout problems that create false trips: Kelvin sense integrity, quiet-ground ownership, and PG/FAULT return paths. It does not expand into broad EMI system design.
The three most common false-trip paths (ground-bounce driven)
Kelvin return is not truly Kelvin, so switching current injects a transient into the comparator’s effective input. The threshold becomes a moving target during load steps.
Divider bottom or reference return lands on a noisy ground. Large di/dt makes the reference node jump, so VTH+/VTH− shifts exactly when protection decisions are made.
Open-drain PG/FAULT is “digital” on paper, but its pull-up current forms a return loop. If that loop crosses the switching return, ground-bounce becomes logic glitches.
Partitioning rule: build a Comparator Quiet Island
- Quiet island contents: comparator, divider/RC, reference decoupling, and the local ground they return to.
- Power loop area: FETs, sense resistor power pads, hot capacitors, and high di/dt traces stay outside the island.
- Single ownership: all threshold-critical returns land on the same quiet ground before touching the system ground.
- Keep-out discipline: never route the switching return through the quiet island copper.
Kelvin sense & differential symmetry (turn rules into PCB actions)
- Route Kelvin+ / Kelvin− as a pair, with matching environment and short loops.
- Return the input filter capacitor to quiet ground next to the comparator input pin.
- Keep the divider and Vref decoupling inside the quiet island boundary.
- Do not land Kelvin− on a nearby “convenient” power ground pour.
- Do not let sense traces cross split planes or travel through the switching return corridor.
- Do not share the divider bottom with high-current returns or via fences near hot loops.
Open-drain PG/FAULT: treat the pull-up loop as a sensitive analog loop
- Define the return: pull-up current must return to the same digital ground domain it references (not via the power loop).
- Wired-OR aggregation: place the pull-up at the aggregation/receiver node; keep the aggregation ground quiet and consistent.
- Cross-voltage domains: if pulled up to another rail, route return to that domain’s ground and avoid crossing switching corridors.
Where to place R / RC / TVS (decision rules tied to false-trip prevention)
Place near the sensitive pin (comparator/Schmitt input) to limit clamp current and slow damaging spikes before they enter the quiet island.
Place as a tight loop around the comparator input. The capacitor return must go to quiet ground to avoid converting ground-bounce into threshold motion.
Place at the entry point (connector) to dump energy early. Ensure clamp return does not route through the comparator quiet island.
Layout review checklist (threshold-focused)
- Comparator, divider/RC, and Vref decoupling all return to quiet ground.
- Kelvin+ / Kelvin− are paired, symmetric, and do not traverse the switching return corridor.
- Divider bottom is not shared with high-current returns; quiet island connects to system ground by a short, controlled path.
- OD pull-up loop return does not cross the power loop; wired-OR aggregation ground is defined and stable.
- TVS/ESD is at the entry point; clamp return does not cut through the quiet island copper.
- Probe points exist: Vrail, VSENSE/IMON, divider node, PG, FAULT (for correlation with ground-bounce).
Example parts pool (starting points for datasheet lookup)
TLV7031 (TI), NCS2200 (onsemi), MCP6561 (Microchip), LTC6752 (Analog Devices).
SN74LVC1G17 (TI).
PESD5V0S1UL (Nexperia).
Note: selection should follow the system fields (VTH+/VTH−, VHYS, TDEGLITCH, domain pull-ups, and worst-case threshold budget) and must be verified on the bench.
Diagram: layout zones and return paths (GOOD vs BAD)
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FAQs: PG chatter, false trips, and retry tuning
Short, bench-ready answers that stay within this page boundary: PG windows (VTH+/VTH−, VHYS), blanking/qualification (TBLANK, TQUAL), deglitch (TDEGLITCH), no-load/short criteria, wired-OR (open-drain), and retry fields (TON_RETRY, TOFF_COOLDOWN, BACKOFF_FACTOR).
