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Ultrasound / ToF Echo Pick-Off with Comparator Gating

Ultrasound / ToF Echo Pick-Off with Comparator Gating

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This page shows how to build a stable first-echo pick-off for Ultrasound/ToF using a comparator gate: define blanking + valid window + re-arm, then set VTH/VHYS from measured noise and edge slope so false triggers drop while timing jitter stays inside budget.

The focus is practical and measurable: P99 timing and false triggers per 1k TX, validated across overdrive recovery, protection networks, EMI, and temperature corners.

What this page solves: stable first-echo pick-off with a comparator gate

This page turns “first echo pick-off” into a repeatable, testable gate event: the first valid threshold crossing inside a defined time window (after blanking), with programmable hysteresis sized against noise and slow ramps.

Success criteria (measurable)

  • False-trigger rate: triggers outside the expected echo region stay rare (track per N bursts).
  • Timing jitter: trigger-time distribution stays tight (use P95/P99, not just “typical”).
  • Miss rate: the smallest expected echo still crosses inside the valid window.
  • Corner stability: performance holds across supply, temperature, and cable/EMI perturbations.

Typical failure modes → first action

Noise triggers before the echo
Check: trigger-time distribution looks scattered and not strictly locked to TX.
First action: increase VHYS or raise VTH, then confirm the valid window is not opening too early.
Slow ramp causes chatter / multi-toggles
Check: input crosses threshold back-and-forth; output shows a burst of toggles.
First action: prioritize more hysteresis; only then consider minimum pulse-width qualification or light input limiting.
TX feedthrough / ringdown triggers the gate
Check: trigger time is nearly fixed relative to TX burst (highly repeatable).
First action: extend blanking to cover ringdown and comparator recovery; validate overdrive recovery in-circuit.
Threshold drifts with temperature or supply
Check: trigger timing shifts slowly across corners even with the same target and window.
First action: audit offset/drift and the threshold source (reference/DAC noise and TC) before chasing filters.

Minimal action path (fast to implement)

  1. Capture the comparator input at the pin: mark TX ringdown and the expected echo region.
  2. Set blanking to fully cover ringdown + recovery; open a valid window only where echoes are allowed.
  3. Choose VTH to pass the smallest echo; choose VHYS to block noise and slow-ramp chatter; then confirm with burst statistics (false rate + P95/P99 jitter).
Problem vs solution for first-echo pick-off using blanking, valid window, and comparator hysteresis Left shows input waveform with TX feedthrough, ringdown, echo and noise. Right shows blanking and valid window gates and a single pick-off pulse for the first echo. First-echo pick-off: define time gates + size hysteresis Comparator input (at pin) time VTH TX feedthrough ringdown echo noise gate + pick-off Gate definition Blanking Valid window Comparator VHYS Gate out Rule: first crossing inside the valid window.

System view: where the comparator sits in an ultrasound/ToF receive chain

A stable pick-off starts with an input contract at the comparator pin: minimum echo, noise, slope near threshold, ringdown/recovery, common-mode range, and source impedance. Without these, threshold and hysteresis tuning becomes guesswork.

Minimal receive chain (pick-off scope only)

Sensor/Receiver → (optional) gain / limiter / envelope shaping → Comparator → Gate/Latch/Timer → MCU/FPGA/TDC

Optional front-end blocks are treated only as input-condition modifiers (amplitude, noise, slope, saturation recovery), not as a separate design topic.

Comparator input contract (must be defined at the pin)

1) Vecho_min
Meaning: smallest echo amplitude reaching the comparator input.
Why it matters: sets the upper limit for VTH and the safe range for VHYS without missing the echo.
2) Vnoise_rms / Vnoise_pk
Meaning: noise level inside the intended valid window.
Why it matters: dictates minimum hysteresis and whether fixed thresholding is feasible.
3) dV/dt near VTH
Meaning: input slope around the threshold crossing.
Why it matters: converts voltage noise into timing jitter (slow edges amplify jitter).
4) Ringdown / TX residue time
Meaning: how long TX feedthrough and ringing dominate the input after a burst.
Why it matters: sets the minimum blanking time and prevents “always-early” triggers.
5) Max overdrive & recovery
Meaning: worst-case saturation at the input and how quickly the comparator resumes valid behavior.
Why it matters: blanking must cover recovery; otherwise the first “valid” crossing is not the echo.
6) VCM range & source impedance (Rs)
Meaning: common-mode conditions and how “stiff” the source drives the input.
Why it matters: bias current × Rs and input capacitance can shift thresholds and slow edges.

Fast measurement path (get the contract in minutes)

  1. Probe at the comparator pin: record TX burst, ringdown, and the expected echo region.
  2. Measure noise in-window: view the intended valid window with no target / blocked path to estimate Vnoise.
  3. Estimate slope near VTH: use cursors around the crossing region to approximate dV/dt; log over corners.

Risk mapping (what breaks first)

  • Vecho_min too small → lowering VTH increases false triggers; fix by windowing + VHYS sizing.
  • dV/dt too slow → timing jitter inflates even if noise is unchanged; avoid heavy RC / weak pull-ups that slow edges.
  • Recovery not covered → blanking is underestimated; the “first crossing” becomes a post-saturation artifact.
  • Rs too high → bias and capacitance shift thresholds and slow the edge; reduce Rs or buffer/reshape.
Comparator location in an ultrasound/ToF receive chain and the required input contract Block diagram shows receiver to comparator to gate and digital processing. A side panel lists the key input conditions to define at the comparator pin. Receive chain (pick-off scope) + input contract at the comparator pin Receiver sensor in Front-end gain / limiter Comparator VTH + VHYS Gate latch / timer MCU/FPGA TDC input Input contract (define at the comparator pin) Vecho_min min echo Vnoise in-window dV/dt@VTH edge slope Ringdown TX residue Recovery after OD VCM / Rs range + drive Use these six fields to set blanking, valid window, VTH, and VHYS without guessing.

Timing anatomy: blanking, windowing, and “first-cross” definition

Most pick-off failures are timing-definition failures: the gate is allowed to “see” TX residue, the valid window is too wide or misplaced, or re-arm is too short and counts the same echo multiple times. A stable implementation treats timing as a three-zone contract and defines first-cross as a verifiable event inside that contract.

The 3-zone timing contract (define it before tuning thresholds)

1) Blanking (t_blank)
Meaning: ignore comparator activity while TX feedthrough/ringdown and saturation recovery dominate.
Driven by: ringdown decay + comparator overdrive recovery (when the input is pushed hard).
If too short: triggers lock to TX residue (repeatable “early” triggers).
If too long: near-range echoes can be clipped (missed first echo).
2) Valid window (t_win_start → t_win_end)
Meaning: the only time range where a threshold crossing is allowed to become an event.
Driven by: expected ToF range (earliest/latest echo times) and the system rule (first-echo only).
If opens too early: residual ringing is misclassified as the echo.
If opens too late: the true first echo is missed and a later crossing becomes “first.”
3) Hold-off / re-arm (t_rearm)
Meaning: after a valid trigger, block further triggers until the chain is re-armed.
Driven by: echo packet length and any residual ringing in-window.
If too short: double-counting within one echo packet (multiple events).
If too long: the next burst’s event can be blocked at high repetition rates.

“First-cross” as a circuit-level event (strict and testable)

Mandatory rule
First-cross = the first threshold crossing that occurs inside the valid window (after blanking).
Optional qualifiers (use only when needed)
  • Minimum pulse width (t_min): reject single-sample glitches and EMI spikes.
  • Minimum stable time (t_stable): require the output to stay asserted briefly before latching.
  • Edge-only capture: count rising-edge only to avoid chatter-driven double events.
Recommended tuning order
  1. Extend blanking until TX residue no longer produces a trigger.
  2. Place and tighten the valid window to the allowed ToF range.
  3. Only then tune VTH/VHYS (threshold and hysteresis) and verify with burst statistics.

Parameters to record (so timing stays reproducible)

  • t_blank: covers ringdown + comparator recovery at worst overdrive.
  • t_win_start / t_win_end: the only interval where first-cross is allowed.
  • t_rearm: blocks re-triggers within one burst/echo packet.
  • Metrics: false-trigger rate per N bursts, and trigger-time P95/P99 jitter.
Timing diagram for blanking, valid window, and first-cross latch behavior Five-row timing diagram shows TX trigger, blanking, valid window, comparator output with possible chatter, and latched gate output that captures only the first valid crossing and holds off until re-arm. Blanking + valid window + re-arm define the first-cross event Signals TX trigger Blanking Valid window Comparator_out Latch_out time t_blank valid window t_win_start t_win_end first-cross t_rearm Comparator_out may chatter; latch captures the first valid crossing only.

Comparator choice for pick-off: speed, input behavior, and output topology

“High-speed” alone is not enough. Pick-off reliability depends on how delay changes at small overdrive, how the input stage behaves after large TX-induced overdrive, and how output topology (push-pull vs open-drain) shapes edge timing into the digital latch/TDC.

Propagation delay vs overdrive (why window edges “drift”)

  • Problem: weaker echoes produce smaller overdrive, which often increases delay and its variation.
  • Impact: the same echo can cross inside the window, yet the event time shifts later and spreads out.
  • What to look for: delay specified at multiple overdrive points (or a curve). If absent, measure on-board with known stimulus levels.

Overdrive recovery (sets the blanking floor)

  • Problem: TX feedthrough can drive the input far beyond the threshold region (saturation-like conditions).
  • Impact: if recovery extends past blanking, the first “valid” crossing may be a recovery artifact, not the echo.
  • Action: blanking must cover ringdown + recovery, validated at worst-case TX amplitude and loading.

Output topology (push-pull vs open-drain) and edge timing

Push-pull output
Cleaner, faster edges with less dependency on external pull-ups. Typically reduces edge uncertainty into a latch/TDC.
Open-drain output
Rise time is set by pull-up and load capacitance. A weak pull-up saves power but slows edges and can widen timing spread.

Pick-off selection checklist (only the load-bearing fields)

  • td vs overdrive: delay (and spread) at small input steps.
  • Recovery behavior: time to regain valid switching after large TX residue.
  • tr/tf under load: edge timing into the digital receiver at real Cload and VDD.
  • Output type: push-pull vs open-drain; if OD, treat pull-up as a timing component.
Spec-to-impact mapping for comparator pick-off selection Left column lists key specs such as delay vs overdrive, recovery, rise/fall time, and output topology. Right column shows impacts on jitter, blanking floor, false triggers, and digital edge uncertainty. Arrows connect specs to impacts. Comparator pick-off: specs → real system impacts Load-bearing specs td vs overdrive weak echo case recovery time after TX OD tr / tf under load Cload + VDD output topology PP vs OD Impacts to control timing jitter P95 / P99 blanking floor t_blank min false triggers rate / N digital edge uncertainty into latch Treat pull-up (OD), recovery, and small-overdrive delay as timing components, not afterthoughts.

Programmable hysteresis done right: VHYS sizing and independence from threshold

Hysteresis only works when two roles are separated and controlled: VTH sets the trigger point (where the crossing happens), while VHYS sets stability (how much noise and slow ramps are rejected). Treating VHYS as a “generic noise fix” often shifts the effective trip point and creates either false triggers (too small) or missed weak echoes (too large).

Separate the two knobs (do not tune them as one)

  • VTH (threshold): decides which part of the echo becomes the event (timing reference).
  • VHYS (hysteresis): decides whether noise/slow edges cause chatter, multiple triggers, or widened timing spread.
  • Failure pattern: raising VHYS without checking VTH+ can push the effective “arm” level above Vecho_min.

Three comparator-side ways to implement programmable hysteresis

1) Built-in programmable VHYS
Best for stable, repeatable gates with minimal external variability.
Watch step size and any VHYS dependency on VDD/temperature; validate across corners with burst statistics.
2) External positive feedback (R network)
Best for flexible VHYS with low BOM cost.
Watch source impedance and bias currents (threshold shift), and output swing (VOH/VOL) altering VTH+/VTH−. Compute VTH+ and VTH− using the two output states and verify on-board.
3) DAC/reference + feedback (decouple VTH and VHYS)
Best for keeping VTH under control while VHYS remains fixed (or scheduled later).
Watch DAC/reference settling and update glitches; treat threshold updates as a gated timing event.

VHYS sizing method (noise-based, then bounded by Vecho_min)

Step 1 — define noise in the valid window
Measure or estimate Vnoise_pk at the comparator pin inside the valid window. Window noise matters more than global noise.
Step 2 — set a stability lower bound
Choose VHYS ≥ k · Vnoise_pk with k ≈ 3–6 to suppress chatter and EMI spikes.
Step 3 — bound it so weak echoes still cross
Check that the upper trip level (VTH+) stays below what the smallest expected echo can reliably exceed. If VHYS increases VTH+ into the weak-echo region, the first-cross becomes late or disappears.
Practical validation (fast and decisive)
  • Log false-trigger rate per N bursts while sweeping VHYS.
  • Log trigger-time P95/P99 while sweeping VHYS at the minimum echo condition.
  • If jitter remains wide at large VHYS, the edge slope (dV/dt) is limiting and must be improved separately.

Common traps (and what to check first)

  • VHYS raised → missed echoes: check VTH+ vs Vecho_min at the pin.
  • Still multiple triggers: check slow edges (dV/dt) and ensure hold-off is not too short.
  • Threshold drifts: check bias current × source impedance and reference/DAC stability.
  • OD output feels “random”: check pull-up and load capacitance; rise-time becomes a timing component.
Hysteresis thresholds VTH+ and VTH- with noise and a sizing rule for VHYS Input ramp with small noise crosses lower and upper thresholds. The diagram labels VTH+, VTH-, VHYS, and a rule VHYS greater than k times peak noise. VHYS controls stability; VTH controls the trip point Vin + noise time VTH+ VTH− VHYS too small → chatter too large → miss weak echo Sizing rule VHYS ≥ k · Vnoise_pk k ≈ 3–6 then bound by Vecho_min

Dynamic thresholding: TVG/AGC ripple and how it breaks a fixed comparator threshold

In real receive chains, echo amplitude and effective gain often change over time. A fixed threshold that is safe early can be too strict later (misses), or a threshold that catches weak late echoes can be too permissive early (false triggers). The safe approach keeps changes inside the timing contract: schedule thresholds in segments and guard every update against glitches.

Why fixed VTH fails when gain/envelope changes with time

  • Time-varying envelope: the echo level is not constant across the window (early vs late differs).
  • AGC/TVG activity: gain steps or ripple modulate the signal near VTH and move the crossing time.
  • Outcome: either early false triggers (too-low VTH) or late misses (too-high VTH), even if VHYS is correct.

Two pick-off-safe ways to adapt without breaking the page boundary

1) Segmented thresholds inside the window
Split the valid window into 2–4 segments and apply VTH(t) (and optionally VHYS(t)) per segment. Keep update points away from expected crossings and add a short guard time after each update.
2) Enable gating (only watch inside the window)
Disable comparator observation during blanking/outside-window. Re-enable only inside the valid window with an enable-stabilization time so the first-cross rule remains meaningful.

How AGC/TVG ripple breaks timing (what it looks like in data)

  • Periodic drift: trigger-time histogram forms bands aligned to an update or ripple frequency.
  • Edge slope changes: dV/dt near VTH varies across the window, widening P95/P99 jitter.
  • Diagnosis: correlate trigger timestamps against AGC update timing and the segmented VTH schedule.

Guard rules (prevent threshold updates from creating false triggers)

  • Update = temporary blanking: do not accept comparator events during VTH/VHYS changes.
  • Wait for settling: enforce t_settle after each update (worst-case corners).
  • Place updates in safe zones: avoid switching near expected crossing times.
  • Prefer monotonic schedules: fewer “back-and-forth” crossings and fewer edge cases.
Segmented threshold schedule VTH(t) over a valid window with an echo envelope Time diagram shows blanking and valid window, an echo envelope curve, and a stepwise VTH(t) schedule with small update-guard intervals after each threshold change. Dynamic thresholding: segment VTH(t) inside the valid window and guard updates time blanking valid window echo envelope VTH(t) VTH1 VTH2 VTH3 update guard Make threshold updates event-safe: disable acceptance during updates and wait for t_settle before re-arming.

False triggers taxonomy: noise, EMI bursts, TX feedthrough, and slow-ramp chatter

Debugging false triggers becomes fast and repeatable when each symptom is mapped to a category. Each category has a distinct fingerprint (random vs synchronous vs TX-locked vs chatter) and a highest-yield first action. The goal is to cut false triggers while preserving weak-echo sensitivity inside the valid window.

Fast classification (one-minute decision)

  • TX-locked? triggers appear at a fixed delay after TX (even with no target).
  • Synchronous? triggers align to a switching/PWM event or a periodic disturbance.
  • Random? triggers scatter in time with no strong correlation.
  • Chatter? multiple toggles near VTH during a slow crossing in the valid window.

1) Wideband noise spikes (random)

Fingerprint
Trigger times scatter inside the window. Rare spikes cross VTH without a stable phase relationship to TX or power events.
First actions
  • Increase VHYS (then re-check VTH+ vs Vecho_min).
  • Add minimum pulse width or minimum stable time before latching.
  • Add light input band-limit (do not slow the echo edge excessively).
Verify
False-trigger rate per N bursts drops without shifting the legitimate first-cross later than expected.

2) EMI bursts (synchronous)

Fingerprint
Trigger times repeat at a fixed phase relative to a switching edge, PWM, motor event, or relay activity.
First actions
  • Prove correlation: trigger scope from the suspected switching node and compare against comparator_out.
  • Fix the coupling path: return-current continuity, shielding, and ground-bounce control.
  • Add input “pulse-hardening”: small series-R + C / RC, then re-check edge slope for jitter impact.
Verify
The time correlation to the switching event disappears, or the false-trigger count collapses under identical switching conditions.

3) TX feedthrough / ringdown (TX-locked)

Fingerprint
Triggers occur at a nearly fixed delay after TX, often near the blanking edge. The effect may persist even without a target.
First actions
  • Extend t_blank to cover ringdown + comparator recovery.
  • Reduce destructive overdrive (limit/clamp so recovery is shorter and repeatable).
  • Break the coupling path in layout/partitioning and return-current routing.
Verify
Removing the target does not produce an event; increasing blanking eliminates the trigger instead of merely moving it randomly.

4) Slow-ramp threshold chatter (multi-toggle)

Fingerprint
Comparator_out toggles multiple times around VTH because the crossing slope is small and noise repeatedly re-crosses the trip point.
First actions
  • Increase VHYS using the noise-based sizing method.
  • Add hold-off / re-arm so only one event is accepted per burst.
  • Improve dV/dt near VTH: reduce excessive RC/clamp capacitance and avoid ultra-weak OD pull-ups.
Verify
Multiple toggles collapse to a single first-cross; event count per burst becomes 0/1 and repeatable.

Recommended troubleshooting order (avoid random threshold tweaking)

  1. TX-locked first: validate blanking and recovery coverage.
  2. Synchronous EMI next: prove correlation and fix coupling/return paths.
  3. Slow-ramp chatter: increase VHYS and enforce hold-off.
  4. Random noise spikes: add pulse-width/stability checks and gentle band-limiting.
Four false-trigger waveform fingerprints: Noise, EMI, TX ringdown, and Ramp chatter Four small waveform panels show distinct patterns for random noise spikes, synchronous EMI bursts, TX feedthrough ringdown, and slow-ramp chatter. Each panel includes a dashed threshold line and a single keyword label. False-trigger fingerprints (look for correlation and crossing behavior) Noise EMI TX Ramp

Jitter budget: edge timing error from noise, slope, and output transition

First-echo pick-off is a timing problem. Timing jitter becomes predictable when expressed as a budget: reduce the noise at the crossing (σv), increase the edge slope at the crossing (dV/dt), and avoid adding output-edge uncertainty (especially with open-drain pull-ups).

Core engineering relation (use it as a budget knob)

σt ≈ σv / (dV/dt)
Larger noise or slower edges widen the crossing time distribution. The fastest way to shrink σt is to lower σv in-window and raise dV/dt at VTH.

What reduces dV/dt (makes the edge slow at VTH)

  • Excessive input RC / over-filtering (edge becomes rounded and slow).
  • Protection capacitance (clamps/TVS/ESD parts) that loads the node.
  • Open-drain output with weak pull-up and large Cload (slow rising edge into latch/TDC).
  • Probe/wiring loading (measurement setup changes the edge and the jitter).

What increases σv (noise at the crossing)

  • Front-end noise inside the valid window (amplifier + sensor chain).
  • Ground bounce and common-mode disturbance coupled into the comparator input.
  • Threshold-side noise when using DAC/reference/dividers (VTH becomes noisy).
  • Coupled digital edges near the input node (crosstalk into the threshold region).

Output-edge uncertainty (do not re-introduce jitter in the digital domain)

Even a clean input crossing can produce a noisy timestamp if the output transition is slow or load-dependent. With open-drain outputs, pull-up selection and load capacitance set the edge shape, so they must be treated as timing components.

Minimal jitter budget fields (measure at the comparator pin)

  • σv_in: RMS noise in the valid window at the input node.
  • dV/dt@VTH: slope at the threshold crossing region.
  • σt_in: estimated input timing spread from σv_in / (dV/dt).
  • tr_out: output rise time under real pull-up and Cload (if OD).
  • P95/P99: acceptance metrics for timestamp stability across N bursts.
Noise and slope create timing jitter at a threshold crossing A sloped edge with an overlaid noise band crosses a threshold line. The diagram labels noise sigma_v, slope dV/dt, and the resulting time spread sigma_t between two vertical dashed lines. σt ≈ σv / (dV/dt): noise and slope set the timing spread time VTH σt σv dV/dt Reduce σv in-window and increase dV/dt at VTH; avoid slow OD edges adding uncertainty into the latch/TDC.

Input conditioning & protection: clamp/RC/series-R without killing speed

Echo pick-off inputs often see large transients and harsh interference. Protection is mandatory, but “heavy” protection directly reduces edge slope at the threshold and shifts recovery behavior, which can destroy first-cross timing. The safest approach builds protection in three controlled functions—limit current, limit voltage, and limit bandwidth—then tunes from light to stronger while watching timing metrics.

Define the protection boundary (measure here, then tune)

  • Vmax_event: worst transient at the comparator pin (TX feedthrough + line events).
  • Vecho_min: smallest valid echo level that must still cross VTH+.
  • σv_in: in-window noise at the pin (sets VHYS and filtering needs).
  • dV/dt@VTH: slope at the crossing region (sets jitter sensitivity).
  • t_recovery_budget: maximum acceptable recovery time after overdrive/clamping.

Series-R (current limiting): the cheapest insurance and the most common speed killer

What it does
Limits surge current into clamps and input structures, isolates cable energy, and reduces damage risk during abnormal events.
What it breaks
Series-R plus total input capacitance (Cin + clamp C + trace C) forms a low-pass that reduces dV/dt@VTH. Slower edges increase timing spread and can push the first-cross later.
Tuning rule
Start with the smallest R that achieves current limiting; increase in small steps and re-check dV/dt@VTH and P95/P99 jitter after each step.

Clamp / TVS (voltage limiting): protect the pin, then prove recovery and threshold stability

What it does
Limits overvoltage by steering energy to rails/ground through a controlled path, preventing destructive input overdrive.
What it breaks
  • Capacitance / charge storage: slows edges and can extend overdrive recovery, pushing blanking longer.
  • Leakage paths: with high source impedance, leakage can shift the effective threshold and drift with temperature.
Tuning rule
Prefer low-C, low-leakage clamps; keep the clamp return path short and controlled; prove that recovery time fits within the timing contract.

Small RC (band limiting): remove spikes without turning echoes into slow ramps

What it does
Softens narrow spikes and high-frequency bursts so VHYS and pulse-width rules can reject them more reliably.
What it breaks
Excess RC reduces dV/dt@VTH and can create slow-ramp chatter. The goal is spike removal, not flattening the noise floor.
Tuning rule
Apply the smallest RC that reduces spike-triggering; if the edge becomes rounded near VTH, back off and use digital gating instead.

Tune from light to stronger (do not add everything at once)

  1. Series-R first: minimum current limiting that protects the clamp and the pin.
  2. Clamp next: low-C, low-leakage option; validate recovery time.
  3. RC last: smallest band-limiting that removes spikes without slowing the echo edge.
  4. Then refine: VHYS and pulse-width / hold-off rules usually beat heavier analog filtering for timing accuracy.

Validation checklist (protection + timing)

  • Recovery: after a worst-case transient, the node returns to normal within the blanking/window budget.
  • Timing: dV/dt@VTH remains sufficient and P95/P99 jitter stays within the budget.
  • Threshold stability: VTH does not shift with temperature or with realistic source impedance.
  • False-trigger resilience: spike/EMI injection does not create events inside the valid window.
Input protection for comparator pick-off: series resistor, RC, and clamps to rails Block diagram shows sensor/connector feeding a series resistor into a protected node, with optional RC to ground and clamp diodes/TVS to rails. Arrows indicate speed impact and offset impact. Protection network: limit current, limit voltage, limit bandwidth (without killing dV/dt) Sensor / Cable transients + EMI Series-R Protected node RC Clamp / TVS AVDD GND Comparator IN speed hit offset hit Tune lightly first: verify recovery, then verify dV/dt@VTH and jitter before adding more filtering.

Layout & grounding for pick-off accuracy: symmetry, return paths, and shielding

Many “false trigger” problems are board problems: uncontrolled return paths, ground bounce, and coupling from TX and switching nodes into the receive input. A pick-off layout must protect the threshold region and keep return currents predictable. The following rules are the minimum set that preserves timing repeatability across temperature, loads, and operating modes.

Minimum partition model (keep RX reference clean)

  • TX zone: high dv/dt nodes and large transient currents.
  • RX zone: input network, comparator, threshold/reference components.
  • Digital zone: FPGA/MCU, clocks, fast I/O edges.
  • Rule: RX return paths must stay continuous; avoid splits/slots that force return detours.

Input routing rules (single-ended or differential)

  • Keep the input path short and away from TX drivers, switch nodes, and clocks.
  • Maintain symmetry for differential inputs; keep pair coupling consistent and avoid skewed detours.
  • Do not route the input across plane gaps; return current must remain directly under the trace.
  • Avoid long parallel runs with fast digital or power gate signals; crossing is safer than paralleling.

Decoupling, reference, and output return paths (where ground bounce is created)

  • Place comparator decoupling to minimize loop area (VDD → cap → GND must be tight).
  • Keep the threshold/reference return quiet; noisy returns modulate VTH directly.
  • For push-pull outputs, manage di/dt return currents so output switching does not disturb the RX reference region.
  • For OD outputs, pull-up current return should not share the sensitive input/threshold ground path.

Shielding and keep-out (minimum isolation rules)

  • Define a keep-out around TX switching nodes; do not route RX inputs or threshold nets through it.
  • Keep RX input and threshold components inside the RX zone; avoid “leaking” them into digital corridors.
  • Use shielding/guarding only when return paths remain continuous; avoid creating plane discontinuities.

Layout checklist (10 checks that catch most pick-off failures)

  • No input trace crosses plane splits; return path stays under the trace.
  • RX input and threshold nets keep distance from TX and switch nodes.
  • Comparator decoupling loop is minimal and local.
  • Reference/DAC/divider return is quiet and not shared with power switching returns.
  • Output return (push-pull) does not disturb the RX reference region.
  • OD pull-up return does not share the sensitive threshold ground.
  • Clamp/TVS return path is short and controlled.
  • TX zone keep-out is respected for RX signals and reference nets.
  • Digital clocks/IO do not parallel the RX input path for long runs.
  • Probe/measurement ground points are planned to avoid injecting ground noise.

Quick localization (prove the board is the root cause)

  • Check whether false events align to a digital I/O transition or a power switching phase.
  • Short the RX input to a quiet reference and confirm whether events disappear.
  • Change probing ground method (short spring vs long ground lead) and observe event sensitivity.
  • Change TX drive strength or edge rate and watch whether the RX event timing shifts.
PCB partition for echo pick-off: TX, RX, and Digital zones with return paths and keep-out Simplified PCB diagram shows TX, RX, and Digital areas, with a keep-out region near TX switching node, and arrows indicating recommended return current paths for RX and TX. Partition and return paths: keep RX quiet and keep TX currents away TX zone RX zone Digital Switch node keep-out Input net Comp Ref / DAC MCU / FPGA Clocks / IO RX return path TX return path keep RX away Keep return paths continuous and local; keep TX switching and digital edges out of the RX threshold region.

Engineering checklist & validation tests: prove first-echo pick-off works

A stable pick-off is not “a fast comparator.” It is a measurable outcome: low false-trigger rate inside the valid window, tight timing percentiles (P95/P99), and robust recovery after TX feedthrough and saturation. Use the checklist below as a reusable field template, then validate with 10k-shot statistics and corner sweeps.

A) Input boundary checklist (measure at the comparator pin)

Required fields
  • Vecho_min (minimum first-echo amplitude inside valid window)
  • Vnoise_rms (RMS noise with TX running; same bandwidth as real pick-off)
  • Vmax_overdrive (TX feedthrough / ringdown peak at the input)
  • Ringdown_time (time until residual decays below the safe threshold band)
  • Source_R and Cin_total (sensor/AFE output impedance + clamp/filter + comparator Cin)
  • Vcm range (common-mode seen at the comparator input under real conditions)
Quick pass/fail hooks
  • Recovery must fit blanking: input must settle to the “valid” behavior before t_win_start
  • Edge slope must support timing: if dV/dt at the crossing is slow, jitter will expand (see H2-8)
  • Overdrive must not corrupt VTH: clamps and bias currents must not shift thresholds under large TX hits

B) Timing window & threshold checklist (make it unambiguous)

Window parameters
  • t_blank: hides TX feedthrough + ringdown (sets the earliest legal trigger)
  • t_win_start / t_win_end: the only time the pick-off is allowed to fire
  • t_rearm: prevents second-echo / multi-toggle triggers
  • Min pulse / min hold: rejects narrow spikes inside the valid window
Threshold & hysteresis
  • VTH (trip point): must be below Vecho_min with margin across corners
  • VHYS (noise immunity): target VHYS ≥ (3–6) × Vnoise_pk and re-check echo detect margin
  • Step-settle time (if VTH/VHYS are updated): enforce a short “ignore” time after each change
  • Thermal drift: VTH(T) must not drift into the noise band or outside echo margin

C) Metrics that end arguments (define success in numbers)

Timing (per shot)
  • Report P50 / P95 / P99 of t_pickoff (relative to TX reference or window start)
  • Track σt and P99 (percentiles are more robust than averages)
  • Separate populations if multiple slopes exist (TVG/AGC steps, mode changes)
False triggers (per 1k TX)
  • Count false_in_window (the only one that corrupts ToF)
  • Also record false_outside_window to diagnose EMI vs timing-window mistakes
  • Tag correlation: TX-synchronous vs switching-synchronous vs random

D) Validation tests (scope + statistics + corners)

  1. 10k-shot repeatability (fixed target / fixed distance)
    Capture t_pickoff for 10k firings; output histogram and P95/P99. If P99 expands, the first suspects are dV/dt at crossing, pull-up strength (OD), and excess input RC/clamp capacitance.
  2. Corner sweep (temperature + VDD)
    Repeat the same 10k-shot test at cold/room/hot and VDD(min/typ/max). Watch for drift in VTH margin and for recovery changes that force longer blanking.
  3. EMI stress (synchronous diagnosis)
    Observe false triggers against the system switching node (motor/PWM/DC-DC). If false events phase-lock to switching, layout/return/shielding dominates; do not “solve” it by over-increasing VHYS alone.
Validation loop for stable first-echo pick-off Flowchart showing a repeatable validation loop: set window and thresholds, capture 10k shots, compute histogram and percentiles, check corners, then update one knob at a time. Validation loop (one knob per iteration) Set timing window t_blank / t_win / t_rearm Set VTH & VHYS margin + stability Capture 10k t_pickoff Histogram + percentiles P95 / P99 + σt Corner checks temp / VDD / EMI Update ONE knob, then re-run window / VTH / VHYS / input network Report: P99(t_pickoff) • false_in_window / 1k TX • recovery_ok (fits t_blank)
Minimal log schema (CSV-ready)
run_id, temp_C, vdd_V, target, distance_cm, tx_setting, t_blank, t_win_start, t_win_end, t_rearm, min_pulse_width, VTH, VHYS, threshold_mode, settle_us, Rseries, Cfilter, clamp, pullup_R, load_C, trials, valid, false_in_window, false_outside, p50_ns, p95_ns, p99_ns, sigma_ns

IC selection logic: vendor questions + quick decision tree (with example part numbers)

Pick-off selection is not a “fastest comparator wins” game. The shortlist must be driven by: delay vs overdrive behavior, recovery after TX saturation, hysteresis control, and output edge integrity under real loading. Use the template below to ask vendors for exactly the data that predicts first-echo stability.

A) What to ask vendors (field → risk mapping)

  • Propagation delay vs overdrive curve → window edge drift when echo amplitude varies
  • Overdrive dispersion (timing spread) → ToF timing percentile floor under changing overdrive
  • Overdrive recovery / behavior after saturation → minimum feasible blanking; near-range detect loss risk
  • Input offset & drift → absolute threshold error across temperature and VDD
  • Input bias current + input capacitance → threshold shift with high source-R; slope loss (jitter expansion)
  • Programmable hysteresis range/step/tempco → stable gating without over-filtering or missed Vecho_min
  • Output topology + rise/fall vs load → OD pull-up limited edge (timing error) vs push-pull di/dt noise
  • Latch / minimum output pulse support → reliable “first-cross” capture with narrow spikes rejected
Copy/paste RFQ questions
1) Provide delay vs overdrive curves (and dispersion) at the intended VDD and temperature range.
2) Provide recovery behavior after input saturation (time to return to valid crossing behavior).
3) Confirm programmable hysteresis: range, step, symmetry, and temperature drift (if applicable).
4) Provide output rise/fall vs load (Cload, Rpullup for OD) and output swing guarantees.
5) Provide input bias current, input capacitance, and any clamp/ESD structure details that affect high source impedance.
6) Confirm latch/enable/blanking support and any minimum pulse requirements or internal filtering.

B) Example part numbers to shortlist (pick-off-relevant families)

These examples are starting points for datasheet lookup and lab validation. The decision must be driven by the field template above: recovery, hysteresis control, and edge integrity under the real RX front-end and timing window.

Bucket 1 — High-speed pick-off with hysteresis + latch control
  • TI: TLV3603, TLV3603-Q1 (family options with adjustable hysteresis and latch)
  • Analog Devices: LTC6752 family (variants with latch and adjustable hysteresis options)
  • Analog Devices: ADCMP602 (family with latch inputs; some variants support adjustable hysteresis via control pin)
Bucket 2 — Timing-consistency emphasis (dispersion-aware) + programmable hysteresis pin
  • Analog Devices: ADCMP564 (separate programmable hysteresis pin; evaluate dispersion and recovery behavior)
Bucket 3 — Fast comparators with latch support (hysteresis often external or fixed)
  • Analog Devices: LT1711 / LT1712 (output latch; validate hysteresis strategy and recovery)
  • Maxim/ADI (legacy Maxim): MAX961 / MAX962 (internal hysteresis; validate that VHYS fits the noise model)
Bucket 4 — Precision/monitoring helpers (not ns-class pick-off, but useful in the same system)
  • TI: LMP7300 (micropower precision comparator with adjustable hysteresis and reference; often used for stable thresholds)
  • Microchip: MIC833 (comparator + on-chip reference + latch; independently adjusted thresholds for wide hysteresis)
  • TI Smart DAC (threshold helper): DAC53701 / DACx3701 (programmable high/low margins can implement hysteresis-like thresholds for slow paths)
Six-node decision tree for pick-off comparator selection Decision tree showing selection order: speed tier, recovery after saturation, hysteresis programmability, output topology, offset and drift, and robustness. Quick decision tree (pick-off only) Speed tier ns vs µs Recovery fits t_blank VHYS control prog / ext Output type OD vs PP Offset / drift VTH accuracy Robustness EMI / ESD Gate-quality checklist before tape-out: recovery_ok ≤ t_blank • VHYS fits noise • rise/fall under load • delay stability vs overdrive

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FAQs: Ultrasound / ToF first-echo pick-off (short, actionable)

Each answer is structured as Trigger → Check → Threshold → Action. Scope points use a consistent map: IN (comparator pin), GATE (blanking/window enable), OUT (comparator/latch output), VTH (DAC/REF threshold node), REF (TX reference / switching node).

Why does it trigger on TX ringdown instead of the echo? Adjust blanking first or hysteresis first?
Trigger
OUT fires immediately after TX, before the first-echo arrival, often at a repeatable time offset from TX.
Check
  • IN vs REF alignment: is the false trigger phase-locked to TX?
  • IN decay envelope: measure ringdown time until IN stays outside the threshold band.
  • Recovery behavior: after large overdrive, does IN crossing behavior look “normal” before window start?
Threshold
  • If false events are TX-synchronous: prioritize t_blank ≥ t_ringdown + t_recovery_margin.
  • If false events are not TX-synchronous: prioritize VHYS ≥ (3–6)·Vnoise_pk (within window).
Action
  1. Extend blanking until ringdown + recovery fits comfortably before the valid window.
  2. Only then raise VHYS to suppress residual noise inside the valid window.
  3. Last resort: add small input conditioning (minimal RC / series-R) if ringdown is not the limiter.
With the same noise amplitude, why does jitter explode when the edge becomes slower?
Trigger
Timing spread (P95/P99) grows sharply after adding RC/clamps/loads, even if the noise amplitude looks similar.
Check
  • Measure dV/dt at the actual crossing (near VTH) on IN, not only peak-to-peak noise.
  • Compare IN slope with/without added clamp/RC/probe loading.
  • Check OD output rise-time vs load (if timing is taken from OUT).
Threshold
  • Use σt ≈ σv / (dV/dt): halving slope doubles timing jitter.
  • If OUT is OD and used for timing: ensure tr is not the dominant slope limiter.
Action
  1. Reduce slope killers: lower Cload / clamp capacitance; avoid oversized RC at the input.
  2. Strengthen edges: lower OD pull-up resistance or use push-pull; reduce source impedance.
  3. Re-check P99 after each single change (one knob per iteration).
For open-drain output, how large does the pull-up resistor need to be before it hurts timing jitter?
Trigger
Timing jitter grows after increasing pull-up resistance or adding load capacitance on OUT.
Check
  • Measure OUT rise-time (tr) with the real load (MCU/FPGA pin + trace + probe).
  • Confirm whether timing is captured from OUT (vs internal latch or a faster node).
  • Estimate effective Cload (pin + trace + clamp + probe).
Threshold
  • First-order: tr ≈ 2.2 · Rpullup · Cload.
  • Keep tr comfortably smaller than the allowed edge-time contribution to P99 timing error (budget by ratio, not an absolute number).
Action
  1. Reduce Rpullup or reduce Cload (shorter trace, lighter probe, fewer clamps on OUT).
  2. If fast timing is required, capture timing from a latched/fast domain or use push-pull output.
  3. Validate by comparing P99 before/after with 10k-shot statistics.
If programmable hysteresis is too large, why does it miss the first echo? How to estimate an upper bound from noise?
Trigger
False triggers drop, but valid picks disappear at long range or weak targets after increasing VHYS.
Check
  • Measure Vecho_min at IN (minimum echo amplitude in the valid window).
  • Measure Vnoise_pk (peak noise around the crossing band, same bandwidth as operation).
  • Confirm the actual switching thresholds: VTH+ and VTH− (or their effective equivalents).
Threshold
  • Noise immunity floor: VHYS ≥ (3–6) · Vnoise_pk.
  • Detection constraint: VHYS must still allow Vecho_min to cross VTH+ with margin (no “dead zone” inside the valid window).
Action
  1. Compute a feasible VHYS band from measured Vnoise_pk and Vecho_min (floor from noise, ceiling from echo margin).
  2. If no feasible band exists, improve SNR or slope at the crossing (reduce loading, improve front-end gain/noise).
  3. Re-validate false_in_window and P99 at the chosen VHYS.
When VTH is set by a DAC, how does reference noise turn into trigger jitter?
Trigger
Jitter increases when the threshold is moved to a DAC/REF node, even if IN looks unchanged.
Check
  • Measure VTH node noise (RMS/peak in the relevant band) while the system is active.
  • Check coupling: does VTH noise correlate with REF (TX or switching activity)?
  • Confirm whether VTH updates occur inside the valid window (step transients can self-trigger).
Threshold
  • Equivalent jitter contribution: σt,th ≈ σv,th / (dV/dt at crossing).
  • If VTH step updates are required, enforce a small “ignore” time after each step before enabling pick-off.
Action
  1. Filter/buffer the VTH node (reduce σv,th) and isolate its return from high di/dt currents.
  2. Move VTH updates outside the valid window; re-enable pick-off only after settle time.
  3. Budget σt,th explicitly in the P99 target; do not treat threshold noise as “free.”
If datasheets do not show overdrive recovery time, how to measure it in the lab?
Trigger
After a large TX feedthrough hit, the pick-off behaves unpredictably until much later than expected.
Check
  • Inject a controlled overdrive pulse at IN (amplitude similar to worst TX feedthrough).
  • After the overdrive pulse, apply a small calibrated “echo-like” ramp/step and observe crossing behavior.
  • Measure the earliest time when crossing delay/jitter returns to the “no-overdrive” baseline.
Threshold
  • Define recovery time as: time until P99 delay and false_in_window match the baseline within a small tolerance band.
  • System requirement: t_recovery + margin ≤ t_blank.
Action
  1. Measure recovery with the real protection network installed (clamps/series-R/RC change recovery behavior).
  2. Set blanking using measured recovery + ringdown, not guesswork.
  3. If recovery is too long, reduce clamp capacitance/leakage and avoid deep saturation at IN.
After adding a TVS at the input, false triggers became more frequent. Which two parameters are the top suspects?
Trigger
The system is “protected” but OUT toggles more often, especially near window start or under strong interference.
Check
  • TVS capacitance: compare dV/dt at IN crossing before/after TVS.
  • TVS leakage / dynamic behavior: check static threshold shift and recovery tails after TX hits.
  • Return path: confirm TVS current returns to the intended low-impedance reference (not through sensitive grounds).
Threshold
  • If dV/dt drops significantly at VTH, jitter and false triggers will rise (via σt ≈ σv/(dV/dt)).
  • If input bias × source-R causes VTH shift comparable to noise band, false triggers will increase.
Action
  1. Switch to lower-capacitance / lower-leakage protection (or move protection earlier where it is less slope-critical).
  2. Use modest series-R for current limiting, but re-check slope and jitter after each change.
  3. Fix TVS return routing (short, direct, and away from threshold/reference returns).
Why does the trigger point drift when the probe cable is moved? Check shielding first or ground return first?
Trigger
OUT timing shifts when cables are touched/moved; false triggers may correlate with mechanical motion.
Check
  • Repeat with a short ground spring vs a long probe ground lead (ground inductance changes noise pickup).
  • Observe IN baseline shift and noise bursts while moving the cable.
  • Compare different shield termination strategies consistent with the system grounding plan.
Threshold
  • If timing changes mainly with probe grounding method, return-path/ground impedance dominates.
  • If timing changes with field coupling but not with ground method, shielding/electric-field pickup dominates.
Action
  1. First ensure low-impedance, continuous RX return paths and short sensitive loops.
  2. Then apply shield/guard strategy to high-impedance nodes and cable entries.
  3. Re-check false_in_window and P99 while intentionally moving cables (a “motion stress” test).
A second trigger happens inside the valid window. What is the most effective re-arm / hold-off strategy?
Trigger
OUT fires twice in one window (multiple echoes or chatter near VTH), corrupting ToF selection.
Check
  • Check whether the second event aligns with a real secondary echo (IN has a second peak) or is noise chatter.
  • Measure pulse width of the first OUT event; narrow spikes often indicate noise/EMI bursts.
  • Confirm if latch/hold-off is implemented in logic or hardware (GATE vs OUT behavior).
Threshold
  • Hold-off must be ≥ the minimum allowed spacing between “first echo” and any later valid crossings for the application.
  • Spike rejection: enforce min_pulse_width so narrow noise spikes do not qualify as a first-cross.
Action
  1. Latch the first valid crossing and ignore subsequent crossings until re-arm time expires.
  2. Add a minimum pulse/hold qualifier inside the valid window (reject narrow spikes).
  3. If chatter persists, increase VHYS or improve slope at crossing (reduce loading / improve drive).
At low temperature, pick-off becomes earlier/later. Is offset drift or hysteresis drift the usual root cause?
Trigger
Timing shifts with temperature even under the same target/distance; sometimes false triggers change too.
Check
  • Log t_pickoff, false_in_window, and the configured VTH/VHYS at cold/room/hot.
  • Check if changing VTH shifts timing predictably (offset/drift signature) or changes chatter immunity (VHYS signature).
  • Measure VTH node stability (DAC/REF drift) if applicable.
Threshold
  • If timing shift tracks VTH changes (predictable), offset/drift dominates threshold accuracy.
  • If timing shift appears mainly as increased chatter/false rate at cold, VHYS (or noise pickup) dominates immunity.
Action
  1. For offset/drift: choose lower-drift parts or re-trim VTH by temperature corner (simple corner table).
  2. For VHYS/noise: re-size VHYS from measured cold noise band and verify Vecho_min still crosses with margin.
  3. Always validate using P99 and false_in_window across corners, not typical timing.
How to quickly distinguish EMI-burst triggers vs wideband-noise triggers on a scope (what to probe)?
Trigger
False triggers happen intermittently; it is unclear whether the cause is switching EMI or random noise.
Check
  • Probe IN, OUT, and REF (switching node or TX reference) simultaneously.
  • Time-stamp false triggers and check phase-lock to REF periodic activity.
  • Check whether the noise burst on IN has a consistent shape and repetition rate.
Threshold
  • If false triggers are phase-locked to REF (fixed phase), it is EMI/synchronous coupling.
  • If event timing is not correlated and looks memoryless, it is wideband/random noise.
Action
  1. For EMI: prioritize return paths, shielding, partitioning, and keep-out from switching nodes.
  2. For random noise: prioritize VHYS sizing, slope improvement at crossing, and minimal RC filtering.
  3. Track false_in_window per 1k TX before/after changes to confirm the dominant mechanism.
After adding RC at the input, the system is more stable but ranging is worse. Is it slope loss or threshold drift?
Trigger
False triggers reduce, but measured ToF shifts or precision degrades after adding RC/series-R.
Check
  • Compare dV/dt at VTH on IN before/after RC (slope loss causes timing spread and delay).
  • Check DC baseline / bias shift at IN and VTH node (leakage + source-R can drift thresholds).
  • See if the ToF error is mostly systematic shift (drift) or statistical spread (slope/jitter).
Threshold
  • If P99 grows while mean stays similar, slope/jitter dominates (σt grows via reduced dV/dt).
  • If mean shifts consistently across shots, threshold drift/bias shift dominates (leakage × source-R or VTH drift).
Action
  1. If slope/jitter: reduce RC burden (smaller C, smaller series-R), or move filtering earlier where slope is less critical.
  2. If threshold drift: reduce source impedance, use lower-leakage parts, and stabilize VTH/REF routing and decoupling.
  3. Re-validate with 10k shots and report P99 + false_in_window per 1k TX.
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