Basic vs Reinforced Insulation for Digital Isolators & Power
← Back to: Digital Isolators & Isolated Power
Basic vs Reinforced insulation is not a label—it is an auditable engineering claim.
This page turns standards language into field-ready criteria: define system inputs, lock layout/process guardrails, and close the loop with PD/hi-pot evidence plus traceable certificates and test records.
H2-1. Scope Guard & Who This Page Is For
This page is a definitions + evidence page. It converts “Basic / Reinforced” labels into a system-level safety claim that can be reviewed, tested, and accepted—without mixing into adjacent topics such as creepage tables, surge fixtures, or device-by-device comparisons.
IN-SCOPE (Owned by this page)
- Claim decoding: interpret “Basic / Reinforced” as a verifiable statement grounded in standards + certificates + test conditions, not as a single datasheet checkbox.
- Evidence vocabulary: explain what VIORM/VIOTM, hi-pot and partial-discharge (PD) do—and do not—prove, and how to keep them consistent as acceptance language.
- System decision logic: translate system inputs (working voltage, environment, lifetime assumptions, altitude, pollution context) into an insulation target and a minimum evidence chain.
- Verification gates & deliverables: define what must exist for design review, lab testing, and production release (test records + certificate identifiers + documentation package).
OUT-OF-SCOPE (Link only, no duplication)
- Creepage/Clearance numeric tables & detailed derivations: keep this page at “allocation logic + acceptance language.” For numeric tables and rule-by-rule distance work, use the dedicated sibling page Creepage & Clearance / Pollution Degree.
- Impulse/Surge waveforms, fixtures, and energy paths: only referenced here as “evidence types.” For waveform classes and lab fixture constraints, use Impulse / Surge Withstand.
- Device selection and interface-specific implementation details: isolators, isolated interfaces, gate-driver protection circuits, or isolated power topologies are handled in their respective device and application pages.
WHO THIS PAGE IS FOR (Task-based)
- Hardware owner: lock the system insulation target and define what “pass” means before layout starts.
- Compliance engineer: convert standard/certificate language into review-ready acceptance criteria and document checklists.
- Test engineer: know which tests and records are required per phase, and how failures map to actionable causes.
- FAE / technical support: align terminology so “reinforced” discussions remain evidence-based and audit-friendly.
Page rules: (1) This page outputs claim, evidence chain, and acceptance gates.
(2) Any numeric table, fixture detail, or deep implementation step is link-only.
(3) Every “reinforced” statement must be attachable to a review checklist.
Figure · Scope Map
H2-2. Basic vs Reinforced: What the Claim Actually Means
“Basic” and “Reinforced” are not single-parameter labels. They are system safety claims that must be supported by an evidence chain: isolation structure + geometry + materials/environment + test/certification context. A label without its conditions is not an acceptance criterion.
Basic insulation (what it really provides)
- Protection role: one primary insulation layer intended to reduce the risk of electric shock under normal conditions.
- System implication: system-level safety typically depends on additional measures (protective earthing, enclosure strategy, spacing controls, or controlled environment assumptions).
- Engineering takeaway: “Basic” must be written as a bounded claim: which working voltage range, which environment assumptions, and which verification gates apply.
Reinforced insulation (what must be true for the claim)
- Protection role: an enhanced insulation system intended to provide a higher level of protection comparable to a “double protection” concept—but only under stated conditions.
- System implication: reinforced is credible only when the system boundary (PCB spacing, pollution context, altitude, materials, processes) aligns with the evidence chain.
- Engineering takeaway: reinforced must be attachable to an acceptance package: certificate identifiers + VIORM/VIOTM context + PD/hi-pot gates + geometry/material assumptions.
COMMON MISREADS (fast rejection tests)
-
Misread #1 · “Device reinforced = system reinforced”
Rejection test: if PCB creepage/clearance, pollution context, altitude derating, and assembly tolerance are not part of acceptance, the reinforced label is not a system claim. -
Misread #2 · “Higher hi-pot voltage = reinforced”
Rejection test: hi-pot is a short-duration withstand check; it does not prove lifetime working stress capability (VIORM), and it does not guarantee PD behavior or tracking resistance under real environment. -
Misread #3 · “Creepage is enough, done”
Rejection test: geometry alone ignores materials, contamination paths, humidity/condensation, and process variability. Reinforced requires a stable insulation system, not just a spacing snapshot.
Minimum evidence chain for any “reinforced” statement:
(A) working-stress context (VIORM),
(B) geometry strategy (creepage/clearance allocation),
(C) insulation quality indicator (PD gate),
(D) short-time withstand (hi-pot gate),
(E) stated conditions (temperature/humidity, pollution context, altitude),
(F) certificate/report identifiers that match the exact part and conditions.
Figure · Protection Layers
H2-3. Standards Landscape: VDE 0884-11 / UL 1577 / IEC 62368 / IEC 60601-1
Isolation standards are used to support a safety claim, not to decorate a datasheet. This section positions each standard as an engineering role (device evidence vs system judgement) and ties it to an auditable deliverables set: certificate/report identifiers plus the specific datasheet fields that must match the tested conditions.
Core framing
- Standard = judgement framework: defines how a “Basic / Reinforced” claim is evaluated at the system level.
- Certificate / report = deliverable evidence: proves a specific device insulation barrier under stated test conditions.
- This page boundary: focuses on engineering fields + acceptance language, not clause-by-clause citations.
Standards as “roles + outputs + fields”
VDE 0884-11
- Role: device-level insulation barrier evidence model (working stress, surge/impulse context, and quality indicators).
- Typical deliverables: certificate identifiers and test-condition statements that can be attached to a design review pack.
- Datasheet fields to match: VIORM/VIOTM context, PD conditions (if stated), creepage/clearance claims, temperature limits.
UL 1577
- Role: device-level isolation withstand evidence (commonly used as a recognizable proof anchor in reviews).
- Typical deliverables: UL file references plus test ratings stated with scope and limitations.
- Datasheet fields to match: isolation rating wording, test voltage context, insulation type claim (basic/reinforced where applicable), package spacing statements.
IEC 62368
- Role: system-level judgement framework for IT/AV equipment safety claims, driven by risk-based safeguards.
- Typical deliverables: compliance evaluation records and safety case documentation referencing device evidence + system geometry.
- Datasheet fields to match: insulation category claims, spacing and environmental assumptions, and any stated certification alignments.
IEC 60601-1
- Role: system-level judgement framework for medical equipment safety, typically demanding strict documentation and leakage-aware insulation decisions.
- Typical deliverables: medical safety evaluation artifacts and test records tied to insulation and leakage requirements.
- Datasheet fields to match: reinforced/basic statements under medical-relevant conditions, environmental limits, and certificate/report identifiers that match the exact part.
Minimum acceptance package (system claim support): (1) standard context (judgement) + (2) device certificate/report identifiers (evidence) +
(3) matching datasheet fields + (4) documented system boundary assumptions (environment, geometry, lifetime).
Figure · Standards-to-Deliverables Matrix (card map)
H2-4. Key Isolation Vocabulary: Working Voltage, VIORM, VIOTM, Impulse, PD
These terms define the acceptance language used throughout the page. The key is to separate long-term working stress, short transient stress, and verification stress. Mixing them causes incorrect “reinforced” conclusions.
Vocabulary (definition + evidence meaning)
Working voltage
- Definition: the sustained electrical stress applied across the isolation barrier in normal operation.
- Supports: selecting a working-stress class and aligning system assumptions (environment, lifetime intent).
- Does not prove: short-time withstand capability by itself; it must be paired with explicit verification gates.
- Where to find: system spec and barrier allocation notes; often referenced indirectly via working-voltage classes.
VIORM
- Definition: a long-term working-stress rating intended to map to insulation lifetime behaviour.
- Supports: writing an auditable “reinforced” claim with stated operating conditions and lifetime assumptions.
- Does not prove: transient surge survival on its own; it is not interchangeable with impulse ratings.
- Where to find: datasheet/certificate field lists that state the working-stress class and conditions.
VIOTM / Impulse
- Definition: short-duration overvoltage stress classes representing transient events rather than steady operation.
- Supports: stating what the barrier can tolerate during defined transient categories.
- Does not prove: long-term insulation ageing performance; not a substitute for working-stress classes.
- Where to find: certificate/datasheet impulse fields; detailed waveform and fixture constraints belong to Impulse / Surge Withstand.
Partial discharge (PD)
- Definition: an insulation quality indicator where microscopic discharge activity signals barrier weakness under stress.
- Supports: reinforced credibility because it reflects insulation system integrity and process stability.
- Does not prove: PCB spacing compliance by itself; PD must be interpreted with stated conditions and geometry.
- Where to find: test-condition statements in certificate/report sections (conditions matter more than the label).
Barrier capacitance / coupling
- Definition: capacitive coupling across the isolation barrier that can transfer common-mode energy.
- Supports: explaining why an isolation barrier can influence system-level noise coupling and emissions.
- Boundary: this page uses it as vocabulary only; detailed CM emission analysis belongs to Barrier Capacitance & CM Emission.
Vocabulary lock: all later sections use these meanings consistently. Working stress (VIORM) ≠ transient stress (VIOTM/impulse) ≠ verification stress (hi-pot/PD).
Figure · Voltage Stress Timeline (3-lane view)
H2-5. System Inputs That Decide the Insulation Level
Insulation level is a system decision. Device labels become meaningful only after the system boundary is locked (primary vs secondary) and the environment, lifetime intent, and equipment category are stated as inputs. This section defines those inputs as a reusable requirement interface.
A. Domain boundary (primary vs secondary)
- Primary domain: any node that can be electrically continuous with, or fault-coupled to, a hazardous energy source.
- Secondary domain: user-accessible or functional low-energy circuitry that must remain protected under stated fault assumptions.
- Boundary lock requirement: the isolation barrier must be drawn as a concrete boundary (PCB, connector, harness, enclosure), otherwise “reinforced” cannot be audited as a system claim.
- Fast re-check trigger: if a credible fault path can bring hazardous potential onto a supposed secondary node, the domain assignment must be revised and the insulation target escalated.
B. Environment & materials (severity drivers)
- Pollution context: dust, salt, chemical residues, and conductive contamination change the effective surface path risk.
- Humidity / condensation: moisture can turn “clean geometry” into a conductive bridge; treat condensation as a risk flag.
- Material group / CTI: tracking resistance and material stability influence long-term surface behaviour and process margins.
- Altitude: reduced air density changes breakdown behaviour and often triggers derating policies at the system level.
C. Lifetime intent & duty profile
- Lifetime intent: design lifetime must be stated to avoid using short-time withstand checks as a proxy for ageing performance.
- Temperature curve: insulation stress is coupled to temperature; worst-case thermal corners must be part of the requirement input.
- Duty / operating curve: duty cycles and operating modes define the sustained working stress across the barrier.
- Evidence implication: long-term working-stress alignment (e.g., VIORM context) must match the stated life and thermal intent.
D. Equipment category (input fields only)
- IT / AV: typically driven by a system judgement framework; the key is consistent documentation and boundary definition.
- Industrial: often implies harsher exposure assumptions (switching transients, contamination, wide temperature) as input tags.
- Medical: often implies stricter touch-risk and leakage sensitivity; treat this as a requirement input, not a clause discussion here.
Output of this section: a stable input set that feeds geometry allocation, working-stress target (VIORM context),
verification gates (PD / hi-pot), and the documentation package.
Figure · Inputs → Requirements Flow
H2-6. Creepage & Clearance: How to Allocate Margin Without Over-Design
This section covers allocation strategy only. Numeric requirements and standards tables are handled in the dedicated Creepage/Clearance page. The focus here is how to distribute margin across device package, PCB geometry, and protective techniques without blindly over-sizing everything.
Allocation method (strategy, not tables)
-
Step 1 · Partition the path
Identify the shortest credible paths: through-air (clearance), along-surface (creepage), and contamination bridges. Treat “surface path under contamination” as a distinct risk, not a footnote. -
Step 2 · Allocate across package + PCB
Package spacing is only one contributor. The system claim depends on the minimum of package + PCB + assembly tolerance. A strong package claim can still fail if the PCB creates a shorter contamination path. -
Step 3 · Protect (change the effective path)
Use engineering techniques to improve the effective path without forcing excessive board area: slots extend surface paths, coatings reduce tracking likelihood, and keepouts prevent hidden bridges. Treat each technique as a controlled process element, not an informal patch. -
Step 4 · Avoid over-design by targeting uncertainty
Margin should be concentrated where uncertainty is highest: contamination variability, assembly tolerance, and environmental exposure. “More distance everywhere” can degrade layout, increase coupling, and raise system cost while failing to address the real weak link.
Typical system failure pattern: relying on a device creepage claim while the PCB creates a shorter surface path
through residues, flux, humidity, or connector contamination. System acceptance must track the weakest path.
Figure · PCB Isolation Geometry (simplified)
For numeric creepage/clearance requirements and standards tables, use the dedicated Creepage/Clearance page.
This section remains allocation-only to avoid cross-page overlap.
H2-7. Certificates & Datasheet: What to Read and What to Ignore
A “reinforced” claim becomes valid only when evidence (certificate/report identifiers) matches fields (datasheet ratings) under the same stated conditions. This section provides a review SOP: what must be present, what must be consistent, and which marketing lines should be treated as non-evidence.
A. Evidence chain (priority order)
- Standard: the judgement framework used to evaluate a system claim (basic/reinforced).
- Certificate / report: the deliverable evidence proving a specific device barrier under stated conditions.
- Datasheet: the field index; useful for locating ratings, but not a substitute for traceable evidence.
B. Must-read fields (claim-critical)
-
VIORM (working-stress context)
Must align with the stated lifetime intent and the operating environment tags (from H2-5). A short-time withstand number is not a VIORM substitute. -
VIOTM / Impulse / Surge class (transient context)
Must be treated as short-duration event capability. It must not be used as evidence for long-term working stress. -
Basic / Reinforced statement (with conditions)
Must be tied to an identifiable evidence source (certificate/report). A label without conditions is not auditable. -
Creepage / Clearance (geometry context)
Device package geometry must not be confused with the system minimum path. The system allocation logic is handled in H2-6 and the dedicated Creepage/Clearance page. -
PD test conditions (quality context)
PD is meaningful only with conditions. If conditions are absent, treat the PD mention as non-evidence. -
Temperature range & lifetime notes (assumption context)
Any reinforced claim must remain valid under the stated temperature envelope and the intended service life assumptions.
C. Consistency checks (fast audit sequence)
- Part identity: the certificate/report must match the exact part number and package variant.
- Condition matching: temperature, insulation type, and stress context must not conflict across fields and deliverables.
- Domain boundary fit: the barrier claim must map cleanly to the system primary/secondary boundary (H2-5).
- Geometry fit: creepage/clearance must be treated as system weakest-path behaviour, not “a single datasheet line”.
- Misuse prevention: hi-pot withstand and transient ratings must not be used as lifetime evidence.
D. Red flags (what to ignore until proven)
-
Vague wording without conditions
Phrases such as “reinforced-grade”, “high isolation”, or “compliant” without conditions and traceable identifiers should be treated as marketing. -
No certificate/report identifier
If a claim cannot be linked to a certificate/report/file reference, it cannot serve as an acceptance deliverable. -
Single-number storytelling
A single withstand number without working-stress context, PD conditions, and temperature envelope is incomplete evidence. -
Geometry shortcut
“Creepage compliant” is insufficient if it ignores PCB contamination paths and system minimum geometry allocation.
E. Deliverable types (what they are used for)
- VDE certificate: device-level evidence artifact that typically summarizes insulation claims and the tested context.
- UL file reference: traceable certification anchor often used for device-level acceptance packaging.
- CB report: report-form deliverable often used within a broader system compliance evidence chain.
Decision rule: if a field lacks conditions or lacks a traceable deliverable identifier, it is not acceptance-grade evidence.
Figure · Datasheet Callout Map (synthetic)
H2-8. Test Strategy: Hi-Pot, Partial Discharge, Surge/Impulse (System-Level View)
Testing should be staged as gates with defined outputs, not as a list of buzzwords. Hi-pot checks short-time withstand, PD checks insulation-system quality, and surge/impulse checks the system transient path. Detailed surge fixtures and waveforms belong to the Surge/Impulse page; this section remains system-level.
A. What each test validates (and what it does not)
-
Hi-pot
Validates short-time withstand across the barrier. It must not be used as lifetime evidence or as a substitute for working-stress alignment. -
Partial discharge (PD)
Validates insulation-system quality under stated conditions. It is a key credibility gate for reinforced claims because it reflects integrity and process stability. -
Surge / impulse
Validates system transient robustness including return paths and loop behaviour. Fixture and waveform details are handled in the Surge/Impulse page.
B. Stage gates (EVT → DVT → PVT)
-
EVT (prototype gate)
Goal: expose gross barrier defects and layout/process risks early.
Tests: hi-pot + PD screening; surge/impulse as risk-based sampling.
Outputs: traceable records, failure mode tags, and corrective actions tied to the boundary definition. -
DVT (verification gate)
Goal: demonstrate repeatability across variants and corners.
Tests: hi-pot + PD across representative corners; surge/impulse as system-level robustness proof with documented loop assumptions.
Outputs: verification summary, traceability to certificate/datasheet fields, and pass/fail criteria documentation. -
PVT (production gate)
Goal: control drift and ensure manufacturing consistency.
Tests: hi-pot as production screen where applicable; PD sampling to confirm insulation integrity; surge/impulse as audit/qualification maintenance.
Outputs: production records, lot traceability, and retention policy for compliance audits.
C. Common failure causes (system view)
- Contamination / residues: flux, dust, or salts create surface paths that invalidate geometry assumptions.
- Moisture / condensation: humidity changes surface conduction and can trigger edge discharge behaviour.
- Edge discharge: sharp edges, voids, or uncontrolled interfaces can concentrate field stress.
- Assembly variability: spacing shifts, material inconsistencies, and harness routing create new weak paths.
- Surge path mistakes: return-path and loop assumptions differ between bench and system; detailed analysis belongs to the Surge/Impulse page.
Minimal record fields (every gate): DUT identity + environment tag + test type + result + failure-mode label + trace link to certificate/datasheet fields.
Figure · Test Gate Ladder (EVT → DVT → PVT)
Boundary rule: surge/impulse fixture and waveform details remain in the Surge/Impulse page. This section stays system-level and output-oriented to avoid cross-page overlap.
H2-9. Layout & Mechanical Guardrails for Insulation Integrity
Insulation integrity fails most often through uncontrolled paths: unintended copper crossing a barrier, contamination bridges across a keepout, or mechanical tolerance shrinking the minimum distance. This section converts insulation intent into layout and mechanical guardrails without entering EMI or signal-integrity detail.
A. Primary / Secondary partition (red-line rules)
-
Barrier must be a closed boundary
The isolation barrier must be drawn as a clear, closed boundary across PCB, connector transitions, and mechanical interfaces. -
No conductive features inside the keepout
Keepout is a true forbidden zone: no copper, no vias, no test pads, and no exposed metal features that can become a contamination bridge. -
No hidden crossings
Watch for hidden crossings such as mounting hardware proximity, shield cans, exposed copper under silkscreen gaps, and connector pin escape routes. -
Single allowed crossing point
If a crossing is required, make it explicit and unique (e.g., the isolation device/module footprint). Everything else must remain isolated.
B. No-return-across-barrier (principle-only checks)
- Do not create a reference shortcut across the barrier through copper, shields, fixtures, or mounting features.
- Audit mechanical-to-electrical coupling: shield hardware and chassis features can silently create a cross-domain path.
- Leakage and Y-cap considerations should be treated as a dedicated topic; details belong to the Y-cap/leakage page.
C. Slots, windows, coating (process-aware guardrails)
-
Slot / window intent
Slots and windows change the effective surface path and reduce contamination bridging risk; treat them as intentional geometry, not decoration. -
Edge control
Keep edges controlled: burrs, sharp corners, and uncontrolled interfaces can concentrate stress or create discharge-prone features. -
Coating is a controlled process item
Coating effectiveness depends on consistent coverage and defined inspection points. Treat coating/encapsulation as a controlled manufacturing element. -
Residues and moisture sensitivity
Flux residues, dust, and humidity can turn a compliant drawing into a failing system path. Guardrails must include cleanliness and moisture tags.
D. Connector / transformer / module (tolerance-aware integrity)
-
Minimum distance is a tolerance-dependent property
Nominal spacing is not acceptance-grade evidence. Assembly shift, component tilt, and mounting hardware can shrink the minimum path. -
Explicit tolerance zones
Mark tolerance-sensitive regions around connectors, transformers, and modules. Treat these as review gates for mechanical and PCB co-design. -
Metal features are risk multipliers
Shields, screws, standoffs, and exposed frames can create unintended cross-domain bridges if not isolated by design intent.
Medical and portable designs are often leakage-sensitive. Treat leakage-path review as an input and use the dedicated Y-cap/leakage page for detailed strategy and criteria.
Figure · Partition + Keepout Blueprint
H2-10. Lifetime & Aging: Why VIORM Is a “Time Claim”
VIORM should be treated as a time claim: it only makes sense together with the intended service life, the operating stress profile, and the environmental tags. Reinforced credibility depends on sustained-stress integrity, not a single short-time withstand check.
A. Ageing mechanisms (engineering intuition)
-
Electrical treeing
Under sustained electric-field stress, microscopic paths can grow over time. This is a long-duration process, not a momentary withstand event. -
Chemical ageing
Moisture, contamination, and material interactions can gradually reduce insulation robustness by changing surfaces and interfaces. -
Thermal ageing
Temperature accelerates many degradation mechanisms. Thermal extremes and repeated cycles increase uncertainty and reduce margin.
B. Stress drivers (trends & methods, no fragile formulas)
- Working stress up → lifetime down: lifetime typically decreases nonlinearly as sustained stress increases.
- Temperature up → ageing accelerates: thermal stress acts as a multiplier on degradation rate.
- Environment severity up → margin shrinks: humidity and contamination increase the probability of surface tracking and discharge initiation.
- Design action: treat unknowns as a design margin band, not as a single-point assumption.
C. How to write lifetime intent into specs
-
Lifetime target
State the service-life intent as a requirement input that governs how working-stress claims are interpreted and verified. -
Operating profile
Define the stress profile in terms of temperature envelope and operating modes (duty/profile), not only a nominal point. -
Environment tags
Carry environment severity tags (humidity/condensation/contamination exposure) as requirement inputs, not post-test excuses. -
Derating strategy
Specify how the design margin is maintained across corners, and when derating is required as conditions become more severe. -
Verification gates
Connect lifetime intent to staged evidence outputs (H2-8): PD evidence and traceable records support reinforced credibility under stated conditions.
D. Field failure separation (two dominant paths)
-
Path 1: contamination / moisture → surface tracking
Often manifests as surface-related degradation consistent with environmental exposure. First check residue, humidity tags, and contamination paths. -
Path 2: long-term material/interface ageing → breakdown
Often correlates with sustained stress and thermal history. First check operating stress profile, temperature history, and time-at-stress distribution.
Practical rule: a reinforced claim must remain valid under the stated life + temperature + environment intent; otherwise the claim is not acceptance-grade.
Figure · Stress vs Lifetime Curve (conceptual)
H2-11. Engineering Checklist: Spec → Design → Test → Production Docs
This page closes into an executable checklist. The objective is to keep the insulation claim auditable: inputs must be explicit, design actions must be reviewable, verification must be staged, and deliverables must be traceable. (Detailed creepage tables, surge fixtures, and leakage/Y-cap strategy remain in their dedicated pages.)
Card A · Design inputs (requirements fields)
-
Domain boundary
Define primary vs secondary, including where the barrier exists across PCB, connectors, and modules. -
Vwork / operating stress profile
Declare working-stress context together with operating modes (duty/profile) and the temperature envelope. -
Altitude / environment tags
Capture altitude and humidity/condensation risk as requirement inputs, not post-failure notes. -
Pollution degree / CTI (material group)
Carry PD/CTI assumptions as explicit inputs used to allocate geometry and margin (details belong to Creepage/Clearance). -
Lifetime target
State the intended service life and how the system will be operated over time (VIORM is a time claim). -
Insulation goal
Declare basic vs reinforced at the system level and define acceptance evidence (certificate/report IDs + test records).
Acceptance readiness begins with complete inputs. Missing inputs produce non-auditable claims.
Card B · Design actions (layout / mechanical / process)
-
Partition + keepout
Draw a closed barrier; keepout is a forbidden zone (no copper/vias/test pads/exposed metal). Allow only one explicit crossing footprint (the isolation device/module). -
Slot / window geometry
Use slots/windows as intentional geometry to reduce contamination bridging. Control edges and avoid uncontrolled sharp features. -
Coating / encapsulation as a controlled process item
Treat coating/potting as process-controlled with inspection points (coverage, voids, interface control). Avoid relying on “assumed” coverage. -
Connector / transformer / module tolerance zones
Mark tolerance-sensitive areas where assembly shift can shrink minimum distances. Audit metal hardware and shield structures for unintended cross-domain paths. -
Cleanliness + moisture control tags
Residues and humidity exposure can turn compliant drawings into failing systems; track cleanliness and moisture tags through verification.
Example material part numbers (for insulation integrity actions)
The items below are examples used to make the checklist concrete (procurement-friendly). Final selection must match the product environment, approvals, and process capability.
- Conformal coating (urethane / silicone examples) Urethane HumiSeal 1A33 (urethane conformal coating) · Silicone DOWSIL 1-2577 (conformal coating) · Acrylic HumiSeal 1B73 (acrylic conformal coating)
- Encapsulation / potting (void control & interface stability) DOWSIL 3-4207 (silicone encapsulant) · 3M Scotchcast 2131 (electrical resin) · Henkel Loctite Stycast 2850FT (encapsulant family; verify variant/process)
- Insulation films / barrier tapes (mechanical separation aids) DuPont Kapton HN (polyimide film family; specify thickness) · 3M Polyimide Film Tape 5413 (polyimide tape) · 3M PTFE Film Tape 5490 (PTFE tape)
- Standoffs / insulating hardware (mechanical tolerance control) Keystone Electronics 1902 (nylon standoff example) · Keystone Electronics 8198 (nylon screw example) · Essentra / Richco NYLON STANDOFF families (select per stack-up)
- Cleaning (residue control is insulation control) 3M Novec 72DE (cleaning solvent family; check availability/regulatory) · Chemtronics Electro-Wash ES1626 (electronics cleaner) · KYZEN AQUANOX A4625 (aqueous cleaner; process-dependent)
Boundary rule: these examples support the insulation-integrity checklist. EMI/leakage strategy (e.g., Y-cap sizing/placement) remains in the dedicated leakage page.
Card C · Verification gates + deliverables (evidence pack)
Verification gates (EVT → DVT → PVT)
-
EVT
Purpose: early defect discovery and layout/process risk exposure.
Evidence: hi-pot + PD screening records; surge/impulse as risk-based sampling.
Output: failure-mode labels + corrective actions + trace links to fields (VIORM/PD conditions/cert IDs). -
DVT
Purpose: repeatability across corners and variants.
Evidence: staged hi-pot + PD across corners; surge/impulse robustness proof with documented assumptions.
Output: verification summary + traceability matrix (part ID ↔ certificate/report ↔ test record set). -
PVT
Purpose: manufacturing consistency and drift control.
Evidence: production screening (where applicable) + PD sampling; surge/impulse audit maintenance.
Output: lot traceability + retention policy suitable for audits.
Deliverables (what must be archived)
-
Certificate / file identifiers
VDE certificate ID, UL file reference, and/or CB report references as applicable to the product category. -
Test record templates
Minimum record fields: DUT ID + environment tag + test conditions + result + failure-mode label + trace link to evidence identifiers. -
Risk assessment pack
Consolidate: input assumptions + design guardrails + verification outputs + known residual risks and mitigations. -
Production documentation
Process controls for coating/encapsulation + inspection gates + retention rules (audit readiness).
Example verification equipment part numbers (for planning & procurement)
Examples below make procurement discussions concrete. Equivalent instruments are acceptable if they meet the required ranges and measurement capabilities.
- Hi-pot tester (with programmable profiles) Chroma 19032 (AC/DC withstand tester family) · Associated Research HypotULTRA 7800 (hipot tester family)
- Partial discharge (PD) measurement platform OMICRON MPD 600 (PD measurement system family)
- Surge / impulse generator (system-level robustness) EMC Partner MIG 系列（surge/impulse generator families; select per required waveform class）
Evidence pack rule: a reinforced claim is acceptance-grade only when deliverable IDs and staged test records remain consistent under the stated input assumptions.
Figure · Checklist Pipeline (Spec → Design → Verification → Docs)
Request a Quote
H2-12. FAQs (Field Troubleshooting & Acceptance Criteria)
These FAQs close the page into field troubleshooting and acceptance criteria. Each answer uses the same 4-line structure and provides quantified placeholders (X/Y/N) for lab-ready criteria and recordkeeping.
Recordkeeping rule (always): log DUT ID, environment window (T/RH/altitude), fixture ID, ramp rate, test duration, and pass/fail thresholds.
1) Datasheet says “reinforced”, but the lab still flags insulation—first check what?
- Likely cause: The reinforced claim is conditional (missing test conditions), or the tested build does not match the certified configuration (exact part / package / process).
- Quick check: Verify part number + package code + revision; request certificate/report IDs; compare PD/hi-pot conditions (voltage, time, ramp rate, environment window).
- Fix: Align the tested configuration with the certified one; obtain missing test-condition fields; freeze process steps that affect insulation (cleaning/coating/assembly tolerance zones).
- Pass criteria: Evidence pack matches exact PN/package/rev + conditions; PD ≤ X pC @ Y Vrms for Z s; hi-pot leakage ≤ X µA @ Y Vac/Vdc for Z s; environment within T= X–Y°C, RH= X–Y% (logged).
2) Hi-pot passes, but PD fails—what’s the fastest root-cause split?
- Likely cause: Short-time withstand is adequate, but insulation quality/path is degraded (surface contamination, edge features, voids, or humidity-driven discharge initiation).
- Quick check: Repeat PD with controlled environment window; compare pre-dry vs no pre-dry; inspect barrier edges/slots/coating for voids; confirm fixture/guarding and ramp rate.
- Fix: Control cleanliness + moisture exposure; remove sharp-edge initiators; make coating/encapsulation a controlled process step with inspection gates; tighten assembly tolerance zone around the barrier.
- Pass criteria: PD ≤ X pC @ Y Vrms for Z s with logged T/RH; repeatability: ≤ N PD events over Y runs; hi-pot leakage ≤ X µA @ Y for Z s with ramp rate X V/s recorded.
3) Same PCB, different humidity → sporadic failure—pollution path or coating voids?
- Likely cause: Humidity activates surface conduction/tracking (residue/pollution path) or reveals coating coverage/void issues that become discharge sites.
- Quick check: Correlate failures with RH window; compare cleaned vs as-built; inspect coating coverage/edge wetting; run a controlled pre-soak (RH/time) and re-test.
- Fix: Add residue control (cleaning + verification), define moisture handling (dry-bake/pre-soak), and convert coating to a controlled, inspectable process step (coverage + void checks).
- Pass criteria: Pass across humidity window: PD ≤ X pC @ Y Vrms for Z s at RH X–Y%; no carbon tracking evidence after N cycles; log RH/T and pre-conditioning time X min.
4) Creepage meets target on package, but board fails—where did the path go?
- Likely cause: The limiting path is on the PCB (surface contamination bridge, solder mask edge, board edge, cutout/slot edge), not the package.
- Quick check: Trace the shortest surface path on the assembled board (including board edge and hardware); inspect mask openings, copper exposure, residues, and proximity to mounting/shield metal.
- Fix: Enforce keepout as a true forbidden zone; add slots/windows or increase separation where the PCB path is limiting; control edges and residues; mark tolerance-sensitive zones near hardware/connector interfaces.
- Pass criteria: Board-level path verified with photos/trace note; PD ≤ X pC @ Y Vrms for Z s; hi-pot leakage ≤ X µA; no visible tracking after N stress cycles; cleaning verification result logged (Y/N) per build.
5) After conformal coating, PD got worse—thickness issue or trapped voids?
- Likely cause: Voids, poor wetting at edges, or trapped contamination under coating create discharge initiation sites; thickness alone rarely explains a step-worse PD outcome.
- Quick check: Compare PD before/after coating with identical conditions; inspect edge coverage and suspected void regions; review coating process steps (cleaning, cure, masking, rework).
- Fix: Add pre-clean + dry control; update coating process for wetting/coverage; introduce inspection gates (coverage/void criteria) and rework limits for the barrier region.
- Pass criteria: PD improves or remains within limit: PD ≤ X pC @ Y Vrms for Z s; coating inspection pass (Y/N) with coverage threshold X%; rework count ≤ N per unit; logged cure condition (time/temp) = X/Y.
6) Altitude derating not considered—what symptom appears first in testing?
- Likely cause: Reduced air density lowers margin for air-gap withstand, increasing discharge/instability sensitivity under the same test voltage.
- Quick check: Compare results at altitude vs near sea-level; review clearance-limiting features (board edge, hardware, connector pins); confirm test voltage/ramp are not implicitly “sea-level assumed”.
- Fix: Treat altitude as a requirements input; allocate additional margin to the limiting geometry; update verification plan to include altitude condition or equivalent derating rationale.
- Pass criteria: Pass under stated altitude tag: PD ≤ X pC @ Y Vrms for Z s at altitude X m; hi-pot leakage ≤ X µA @ Y; record altitude condition (Y/N) and test rationale ID.
7) UL file exists, but certificate doesn’t match the exact part number—accept or not?
- Likely cause: A family-level listing is being mistaken for exact-part coverage; variants (package, creepage geometry, material system, process) may not be included.
- Quick check: Match exact PN/package suffix/revision; confirm the listed construction details and conditions; verify the deliverable IDs explicitly reference the shipped configuration.
- Fix: Request the correct listing/letter for the exact variant, or constrain procurement to the covered variant; update BOM control rules so substitutions require evidence review.
- Pass criteria: Deliverable IDs explicitly cover exact PN/package/rev (Y/N); verification records reference those IDs; procurement substitution rule documented (Y/N) with approval gate; audit pack completeness = X/ Y items present.
8) Reinforced claim is conditional—what are the missing test conditions to request?
- Likely cause: Marketing-level “reinforced” lacks the conditions needed to make it acceptance-grade (stress/time/environment/PD conditions not specified).
- Quick check: Request: PD test voltage/time/ramp + environment window; hi-pot voltage/time/ramp + leakage limit; working-stress basis (VIORM context) + temperature range; exact creepage/clearance geometry reference.
- Fix: Freeze a minimum evidence set required for procurement acceptance; reject claims that lack traceable conditions; tie acceptance to certificate/report IDs and test records.
- Pass criteria: Conditions provided (Y/N) for: PD = X pC @ Y Vrms, Z s, ramp X V/s, RH X–Y%; hi-pot leakage ≤ X µA @ Y, Z s; temperature range = X–Y°C; evidence IDs present (Y/N).
9) Passing in one lab, failing in another—fixture / ramp rate / environment mismatch?
- Likely cause: Hidden condition differences: fixture guarding/grounding, ramp rate, dwell time, environment window, pre-conditioning, or test lead routing.
- Quick check: Compare the full metadata: fixture ID, grounding scheme, ramp rate, dwell, pre-dry/pre-soak, T/RH/altitude; run an A/B test with identical setup and swapped fixtures.
- Fix: Standardize the acceptance recipe and record template; lock down fixture configuration; require metadata parity before comparing results across labs.
- Pass criteria: Cross-lab delta within limit: ΔPD ≤ X pC or Δleakage ≤ X µA under matched recipe; recipe match checklist = Y/N fields complete; ramp rate = X V/s ± Y%; environment window logged.
10) Field returns show carbon tracking—what should be logged to prove mechanism?
- Likely cause: Surface tracking driven by contamination + moisture + geometry that enables a pollution path; mechanism proof requires traceable environment and build-history evidence.
- Quick check: Capture location photos and path trace; collect environment exposure tags (RH/condensation events); check cleaning/coating process records; compare to known-good units from other lots.
- Fix: Close the pollution path (keepout/slot/edge control), tighten cleanliness and moisture handling, and introduce inspection gates for barrier region residues and coating coverage.
- Pass criteria: Required logs present (Y/N): lot ID, cleaning verification, coating inspection, environment exposure window; reproduce test: tracking not observed after N cycles at RH X–Y%; PD ≤ X pC @ Y Vrms for Z s.
11) Slots added, but clearance still fails—board edge / assembly tolerance issue?
- Likely cause: The limiting clearance is not the intended slot region but another path (board edge, hardware, connector pins, assembly shift) shrinking the minimum distance.
- Quick check: Re-identify the true minimum path on the assembled unit (not the CAD nominal); inspect board edge and metal hardware; check tolerance stack-up and mounting positions.
- Fix: Move the limiting geometry away from edges/hardware, enlarge keepout and tolerance zones, and lock assembly constraints (alignment features, hardware isolation).
- Pass criteria: True minimum path documented with photos/measurement note (Y/N); pass hi-pot leakage ≤ X µA @ Y for Z s; PD ≤ X pC @ Y Vrms for Z s; assembly alignment within X mm (logged).
12) Hipot trip only on cold start—condensation or flux residue?
- Likely cause: Condensation during cold start creates a temporary conductive film, or flux residue becomes conductive under moisture, causing leakage spikes and trips.
- Quick check: Log temperature/RH and dew-point risk; inspect for residue; repeat after controlled dry-bake; compare leakage over time as the unit warms and dries.
- Fix: Add moisture handling (packaging, warm-up, dry-bake policy), strengthen cleaning verification, and protect vulnerable paths with keepout/edge control/coating inspection gates.
- Pass criteria: Cold-start recipe passes: leakage ≤ X µA @ Y for Z s with ramp X V/s; pre-conditioning defined: dry-bake X°C for Y min (or RH soak X–Y% for Z min); dew-point risk logged (Y/N).
