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Capacitive Digital Isolator Design Guide (High CMTI)

Capacitive Digital Isolator Design Guide (High CMTI)

← Back to: Digital Isolators & Isolated Power

Capacitive digital isolation is the fastest, lowest-latency way to break ground loops and survive high dv/dt noise between control and power/measurement domains.

This page turns CMTI, timing, EMI coupling, low-power behavior, and layout into a measurable selection-and-validation workflow, so field reliability is proven by X/Y/N acceptance criteria instead of “good-looking waveforms.”

H2-1. Definition & When to Use Capacitive Digital Isolation

Purpose: define the device boundary, the system placement, and the decision triggers—so selection stays vertical and does not spill into sibling pages.
A capacitive digital isolator transfers digital state across an isolation barrier using capacitive coupling plus internal encoding/decoding, while keeping the two grounds electrically separated. This page focuses on digital timing, CMTI/dv/dt robustness, EMI coupling mechanisms, fail-safe behavior, and layout/verification hooks for MCU↔AFE and MCU↔driver control.
What it is
  • Digital-only barrier crossing: designed for logic-level channels (one-way or mixed-direction) with defined propagation delay and skew.
  • Encoding/decoding inside: not a “wire through a wall”; internal modulation and recovery define pulse-width behavior and jitter sensitivity.
  • Barrier capacitance exists: the isolation barrier behaves like a small coupling capacitor; common-mode transients can inject displacement current.
  • System-level result: fast, low-latency control paths with strong dv/dt immunity, when return paths and decoupling are designed correctly.
When it wins (decision triggers)
  • Fast control timing matters: tight loop control, fast digital handshakes, or multi-channel alignment where tPD and skew must fit a timing window.
  • High dv/dt environment: motor drives, inverter stages, switching nodes, or long return paths—where CMTI (kV/µs-class) is a first-order requirement.
  • Power budget is constrained: isolated nodes, battery-backed control islands, or duty-cycled links—where static + dynamic power must be bounded across activity rates.
  • EMI is manageable by design: edge-rate control and clean partitioning can keep barrier-coupled common-mode emission within system limits.
When to pause (common misfits)
  • Extreme common-mode emission constraints: barrier capacitance inevitably couples displacement current; layout and edge shaping must be feasible.
  • Undefined power sequencing is expected: if either side frequently brownouts, confirm fail-safe defaults and UVLO behavior match the safety concept.
  • Protocol behavior is the main challenge: interface-level nuances (e.g., open-drain bi-directional semantics) belong to dedicated Isolated Interface pages; this page stays device-centric.
Scope guard (no overlap)
Magnetic/inductive isolation physics and optocoupler drop-in compatibility are handled on their own sibling pages. Interface-protocol details (USB/CAN/Ethernet stacks) are out of scope here; this page focuses on capacitive digital isolator device behavior, timing, dv/dt robustness, EMI coupling, fail-safe states, and layout/verification.
Capacitive Digital Isolator — System Placement Control Domain MCU / FPGA CTRL High-Noise / HV Domain AFE Gate Driver Power Stage dv/dt Isolation Barrier TX RX CTRL STAT GND1 GND2 Place the barrier between control and noisy/HV domains Keep grounds separated; route returns without crossing the gap

H2-2. Working Principle: Capacitive Barrier & Encoding/Decoding Path

Key idea: digital information crosses the barrier only after being encoded into a form that can couple through the barrier capacitance.
The barrier is not a conductive path. It behaves like a small coupling capacitor, so the signal chain must shape, encode, couple, and then recover the data. The same capacitance that enables coupling also creates a displacement-current path under fast common-mode transients—linking timing behavior, CMTI, EMI, and layout into one system mechanism.
Signal chain (why timing is a device behavior)
Step 1 — Input conditioning
Shapes edges, rejects ultra-short glitches, and establishes a clean logic interpretation before encoding. This is where pulse-width filtering and noise margin begin.
Step 2 — Encoding / modulation
Converts a logic state into a coded waveform that can traverse the capacitive barrier. Encoding choices directly influence propagation delay, pulse-width distortion, and jitter sensitivity.
Step 3 — Coupling + recovery (decode)
The coupled waveform is reconstructed into a stable logic output using thresholds and timing logic. Supply noise, ground bounce, and transient injection can shift the effective decision point.
The dv/dt mechanism (why CMTI and EMI share the same root)
Displacement current: I = Cbarrier · (dv/dt)
  • Fast common-mode steps drive current through the barrier capacitance into the secondary reference network.
  • Return-path impedance converts that injected current into ground movement (bounce) near the decoder thresholds.
  • Asymmetry turns CM into DM: mismatch in coupling, routing, or copper distribution converts common-mode injection into differential disturbance.
  • Outcome: bit flips, false toggles, or “works on bench, fails in real switching” unless partitioning, decoupling, and edge control are intentional.
Typical distortion / error roots (used later in timing, CMTI, EMI, and FAQ)
  • Coupling mismatch: uneven copper, asymmetrical routing, or different reference planes around the barrier.
  • Threshold sensitivity: low VDD corners, temperature drift, or noise near the decoder comparator.
  • Supply transient coupling: inadequate local decoupling or poor return-current containment on either side.
  • Over-aggressive edges: fast output transitions exciting reflections/crosstalk that look like data events at the receiver.
Capacitive Digital Isolator — Internal Signal Chain Signal Path Input Condition Encoder Capacitive Barrier Decoder Output Encoded pulses Threshold decision Common-Mode Transient Path I = Cbarrier · dv/dt dv/dt step Return impedance Cbarrier Encoding enables coupling across the barrier dv/dt drives displacement current; layout controls the impact

H2-3. Architecture Variants & Channel Topologies

Goal: lock the channel topology early (direction, count, and power domains) so timing, CMTI, EMI, and fail-safe checks stay consistent and vertical.
Bidirectional behavior is rarely “two one-way lanes.” It often includes direction control windows, contention handling, and defined idle states. Multi-channel parts add die-level matching benefits, but they also introduce cross-channel coupling paths that must be checked with activity sweeps and supply-domain validation.
Topology library (fixed fields)
Unidirectional channels (TX-only lanes)
When to use: clean one-way control/trigger lanes where propagation delay and channel-to-channel skew dominate the timing budget.
Pitfall: adding a “return lane” later without re-budgets turns skew into a silent system failure mode.
Quick check: measure tPD and skew at the same threshold/bandwidth; verify minimum input pulse width and output drive/load corner behavior.
Output state: confirm power-down/UVLO defaults (Hi/Lo/Hi-Z) match safety assumptions.
Bidirectional channels (true bi-dir behavior)
When to use: signals where either side may drive the line and idle direction is not fixed (direction-aware semantics).
Pitfall: internal direction detection/handshake windows can add turn-around delay and undefined behavior under contention.
Quick check: validate turn-around timing, contention handling, and idle defaults across power sequencing (primary-first vs secondary-first).
Output state: verify what the powered side observes if the other side browns out (forced idle, clamp, or Hi-Z).
Mixed-direction multi-channel (control + status)
When to use: grouped signals such as PWM/EN (TX) plus FAULT/READY (RX) with shared barrier and predictable alignment.
Pitfall: cross-channel skew and coupling can turn a quiet status lane into a false fault during high activity on control lanes.
Quick check: sweep activity on “noisy” lanes while monitoring “quiet” lanes for spurious transitions; re-check skew under the same load and threshold conditions.
Output state: ensure fault lanes fail to a safe state when any supply domain collapses.
Multi-channel density (2/4/6/8 lanes)
When to use: compact barrier crossing where die-level matching helps keep skew tight across lanes.
Pitfall: a shared supply and finite decoupling impedance can convert one lane’s activity into threshold movement for other lanes.
Quick check: run an “activity sweep” (one lane toggling at max rate, others idle) and verify idle lanes remain stable; repeat over Temp/VDD corners.
Output state: confirm whether a shared UVLO event forces all lanes to a common safe default.
Shared VDD2 vs independent VDD2 (what changes in real systems)
  • Shared VDD2: simpler BOM and consistent channel environment, but higher risk of supply-coupled interaction (activity on one lane perturbs quiet lanes through supply impedance).
  • Independent VDD2: isolates “noisy” lanes (high toggle rate) from “quiet” lanes (fault/status/clock), but requires separate regulation/decoupling discipline.
  • Verification hook: compare lane stability and skew drift under the same activity sweep with shared vs segmented supplies; treat results as a topology decision, not a layout afterthought.
Cross-channel coupling paths (root-cause classification)
  • Supply coupling: shared VDD/ground impedance turns activity into threshold movement; symptom scales with toggle rate and improves with local decoupling/short returns.
  • Barrier coupling: common-mode transient injection through barrier capacitance; symptom correlates with dv/dt events and improves with partitioning/edge control.
  • Pin/package coupling: adjacent pins and routing induce near-end crosstalk; symptom improves with pin reassignment, spacing, and controlled edge rate.
Mixed-direction Channels and Power Domains Mixed-direction Channel Maps 2CH TX RX 4CH 6CH Secondary Power Domains (VDD2) Shared VDD2 Independent VDD2 VDD2-A VDD2-B Shared rails can couple activity into quiet lanes Segment rails when quiet lanes are sensitive

H2-4. Timing Deep Dive: Prop Delay, Skew, PWD, Jitter

Timing becomes predictable only when definitions, thresholds, bandwidth, and statistics windows are fixed.
Propagation delay, skew, pulse-width distortion, and jitter are not abstract “datasheet numbers.” They are measurement-defined behaviors that must be budgeted against the system timing window under Temp/VDD/load corners and under realistic supply/transient conditions.
Metric definitions (use a single measurement contract)
  • tPD (prop delay): time from input threshold crossing to output threshold crossing (fixed threshold rule).
  • tSK (skew): difference between two output channels’ threshold crossings under the same trigger and load.
  • PWD (pulse-width distortion): change in high/low pulse width from input to output (or duty-cycle shift) under defined conditions.
  • Jitter: statistical time variation of edge crossing (RMS or p-p) with defined bandwidth/filtering and observation window.
Fix these knobs before comparing results: threshold reference (50% or VIH/VIL rule), scope bandwidth/filtering, load (CL/drive), input slew rate, and sample size (N edges or T seconds).
Budgeting method (convert into a spreadsheet line item)
Timing margin = System window − [ tPD + tSK + PWD + Corner drift + Supply-induced shift ]
  • Corner drift: adders for Temp/VDD/load (use max specs or measured envelopes, not typical).
  • Supply-induced shift: delay/skew movement under realistic droop/noise; evaluate with controlled load steps and local decoupling variants.
  • Practical rule: treat any “small but systematic” skew as a budget term, not as measurement noise.
Common traps (why “scope looks fine” can still fail)
  • Typical-only thinking: using typical tPD/tSK ignores corner drift and collapses the timing margin at temperature/voltage extremes.
  • Single-ended measurement: measuring only one lane misses relative alignment; skew failures are inherently differential across channels.
  • Non-fixed thresholds/bandwidth: changing trigger levels or filtering makes results non-comparable across labs and builds.
  • Glitch filtering assumptions: hidden debounce or bandwidth limits can “clean up” a waveform while the digital receiver still sees edge uncertainty.
Validation checklist (repeatable and comparable)
  • Probe references: measure each side with its local ground; avoid creating an unintended return across the isolation gap.
  • Trigger contract: use the same input edge trigger and capture both outputs simultaneously to compute skew.
  • Statistics window: record N edges (or T seconds) and report distribution (min/max/percentiles) rather than a single snapshot.
  • Corner sweep: repeat across Temp/VDD/load; note any systematic drift as a budget term.
  • De-glitch control: document scope bandwidth/filtering and any device-side filtering assumptions before drawing conclusions.
Timing Metrics: tPD, tSK, PWD, Jitter Input / Output Alignment (Fixed Threshold) IN OUT1 OUT2 tPD tSK PWD Temp VDD Load Jitter = edge time variation Use fixed thresholds, bandwidth, and statistics windows Budget drift across Temp/VDD/Load and measure relative skew

H2-5. CMTI & dv/dt Immunity: System-Level Meaning

CMTI is not a standalone datasheet number—its real meaning is “no false toggles during the actual dv/dt events in the system.”
A fast common-mode step drives displacement current through the isolation barrier capacitance. If that current develops voltage on the secondary reference network near the decoder thresholds, the device can produce false edges, short pulses, or state upsets. System survivability depends on return-path geometry, local decoupling, and how dv/dt events are generated and contained.
Mechanism → Path → Countermeasures → Acceptance
Mechanism (what CMTI means in practice)
  • Definition: no unintended output state changes during specified common-mode dv/dt events.
  • Failure events: false toggle, short glitch pulse, missed edge, decoder upset, or latch/restart behavior.
  • Not a constant: depends on dv/dt waveform, repetition, supplies, load, and the return-path impedance near the decoder.
Injection path (how dv/dt becomes a logic error)
  • Source: HV switching node creates a fast common-mode step (dv/dt).
  • Coupling: barrier capacitance conducts displacement current into the secondary reference network.
  • Conversion: return-path impedance turns injected current into ground movement near threshold decisions.
  • Trigger: asymmetry (routing/copper/pin) converts common-mode disturbance into differential threshold error.
Countermeasures (system hooks that actually reduce false toggles)
  • Contain the return loop: place secondary decoupling tight to the isolator; keep high-frequency return paths compact and symmetric.
  • Partition correctly: never allow signal or power return currents to cross the isolation gap; avoid “accidental bridges” via copper, shields, or measurement wiring.
  • Edge moderation: reduce the highest-frequency content when timing allows (driver setting or series resistance) to lower peak injected current.
  • Defined safe states: ensure outputs default to safe values during UVLO/brownout so any transient event cannot trigger a hazardous action.
Acceptance contract (X/Y/N placeholders)
  • Stimulus: dv/dt slope = X kV/µs, CM step = Y V, repetition = N kHz (define both polarities).
  • Waveform definition: specify measurement point for dv/dt (HV node and reference) and the rise/fall segment used for slope.
  • Observation window: monitor for N events or Y minutes; count all false edges/pulses/state upsets.
  • Pass criteria: error events = 0; any glitch must stay below defined width/amplitude limits (X/Y placeholders).
dv/dt Injection Loop: Bad vs Good Return HV / Noisy Domain Control / Secondary Domain Switch Node dv/dt Power Stage CM step source Barrier Cbar Decoder / Logic threshold decision VDD2 + Decoupling Local C Idisp Bad loop (long return) Good loop (tight return) GND1 GND2 dv/dt drives displacement current through the barrier capacitance Tight return paths and local decoupling prevent false toggles

H2-6. EMI & Barrier Capacitance: CM Emission and Edge-Rate Trade-offs

Barrier capacitance turns fast edges and common-mode steps into common-mode current; that current is what becomes emission and “sensitive-ground pollution.”
Lower Cbarrier reduces coupling, but system emission is also controlled by edge spectrum and return-path geometry. Faster edges can improve timing margin yet increase CM current peaks and coupling into cables, shields, chassis, and nearby analog references. The goal is to choose a balanced edge profile that still meets timing and robustness requirements.
What Cbarrier changes (system-visible outcomes)
  • CM current amplitude: larger Cbarrier increases displacement current for a given dv/dt.
  • Emission sensitivity: fast edges push more energy into high-frequency paths that couple into harness/chassis structures.
  • Ground contamination: injected CM current creates voltage on finite return impedances and can modulate “quiet” references.
  • Trade-off axis: edge speed helps timing but can worsen CM emission and crosstalk unless returns are controlled.
Design modes (Fast edges vs Low EMI vs Balanced)
Fast edges (timing-first)
  • Knobs: stronger drive, smaller series R, short controlled return.
  • Best when: tight sampling windows or high-rate control demands maximum edge fidelity.
  • Risk: higher CM emission peaks and greater sensitivity to harness/chassis geometry.
  • Quick check: emission or field upsets correlate strongly with edge transitions.
Low EMI (emission-first)
  • Knobs: weaker drive, larger series R, tightly defined return path.
  • Best when: ports/harness act like antennas and emission headroom is limited.
  • Risk: reduced timing margin and increased susceptibility near threshold if the window is tight.
  • Quick check: modest series R produces large emission reduction without breaking timing.
Balanced (production-friendly)
  • Knobs: moderate drive, tuned series R, controlled return geometry.
  • Goal: meet timing budget while reducing CM peaks enough to stay stable across cable and enclosure variations.
  • Verification: A/B test across harness routing and enclosure states; require stable metrics in a fixed observation window.
Field symptom: “door open / harness moved” changes behavior
  • Mechanism: enclosure and harness geometry changes parasitic capacitance and return paths, shifting CM coupling and resonances.
  • Fast discriminator: adjust only one knob at a time (drive strength or series R). If symptoms track edge shaping, coupling is edge-dominated.
  • Path discriminator: improve return containment locally (shorter loop / better partition). If symptoms track loop geometry, coupling is path-dominated.
CM Emission: Path and Control Knobs Common-Mode Current Path Primary Fast edge Secondary Sensitive ref C bar Icm Harness / Chassis Coupling Return path Control Knobs Drive strength Series R Return path Lower CM emission by shaping edges and controlling return paths Balance timing margin against emission and crosstalk

H2-7. Power & Low-Power Modes: Quiescent, Dynamic, Auto-Wake Interactions

Low-power isolation cannot be validated by IQ alone; the real budget must include activity-rate power and wake overhead.
Static current sets the sleep floor, dynamic current scales with toggling, and wake behavior adds burst energy that can dominate average power when wake frequency is high. A robust plan defines a power ledger, a wake strategy that suppresses false activity, and a verification matrix that sweeps activity rate, wake frequency, corners, and power sequencing.
Power breakdown (ledger that avoids “IQ-only” mistakes)
Total power = Static + Dynamic + Wake overhead
  • Static (sleep floor): defined by VDD, temperature, and input pin states (never assume “idle” is free if inputs can float).
  • Dynamic (activity-rate dependent): scales with toggle rate, edge shape, output drive/load, and internal encode/decode switching.
  • Wake overhead (per event): burst energy during wake/settle windows; average power can be dominated by wake frequency, not IQ.
What to record (for budgets and lab repeatability)
  • Supply rails (VDD1/VDD2), temperature corner, and the exact “idle” pin levels.
  • Activity profile: toggle rate, duty, burst pattern, and the measurement window length.
  • Wake profile: wake pulse width, wake-to-valid time, and wake count per minute/hour.
Auto-wake interactions (avoid false activity and jittery wake loops)
Typical failure patterns
  • False wake: noise near threshold or floating inputs trigger wake events without meaningful data transfer.
  • Wake jitter: repeated partial-wake behavior increases average current and creates unpredictable timing for downstream logic.
  • Default-state side effects: undefined states during ramp can be interpreted as valid commands by the receiving domain.
System-level knobs (kept within isolator scope)
  • Wake gating: only allow wake when a qualified event is present (avoid counting noise as “activity”).
  • Debounce windows: require stability for a defined time window before accepting wake.
  • Defined input states: enforce pull-up/down or upstream idle drive so sleep does not equal “floating.”
  • Power sequencing awareness: ensure the receiver ignores control lines until rails are valid and defaults are safe.
Verification matrix (X/Y/N placeholders)
  • Activity sweep: Sleep → Mid activity → Full toggle (use a fixed measurement window).
  • Wake frequency: wake count ≤ N/hour; wake pulse width ≥ X ns; wake-to-valid ≤ Y ms.
  • Corners: Temp / VDD / load (repeat pass criteria at each corner).
  • Sequencing: primary-first, secondary-first, and brownout recovery.
  • Pass criteria: IAVG ≤ X mA over Y minutes; false wakes ≤ N/hour; unsafe output actions = 0.
Activity Rate → Power (Concept) Activity Rate → Power Trend (Concept) Activity Sleep Mid Full Power Sleep Mid Full Wake spikes Ledger Pstatic Pdyn Pwake Power depends on activity rate, not only IQ Wake overhead scales with wake frequency

H2-8. Fail-Safe Behavior & Robustness: UVLO Defaults, Glitch Immunity, Watchdog Paths

Fail-safe behavior is defined by what outputs do during OFF/RAMP/UVLO, not by “normal-mode” timing specs.
Robust isolation requires explicit defaults, validated power sequencing, and measurable glitch immunity. A consistent engineering contract uses the same template for each scenario: Trigger → Symptom → Root cause → Fix → Pass criteria (X). This makes brownout and restart behavior testable and prevents unsafe actuation from transient or undefined states.
Robustness scenarios (fixed engineering template)
Scenario: UVLO / brownout (either side)
  • Trigger: VDD1 or VDD2 crosses UVLO or falls rapidly.
  • Symptom: false edges, short pulses, or uncontrolled output state during the ramp.
  • Root cause: decoder state transitions while thresholds and references are moving.
  • Fix: choose safe default output behavior; block external actions until rails are valid; enforce defined inputs.
  • Pass criteria (X): false events = 0 across X brownout events; recovery to stable state ≤ Y ms.
Scenario: power sequencing (primary-first vs secondary-first)
  • Trigger: one side powers first, the other powers late or cycles.
  • Symptom: the receiving domain interprets default levels as valid commands.
  • Root cause: default state + undefined inputs during ramp create “meaningful-looking” levels.
  • Fix: set default-safe logic; add an enable/valid window; define all inputs with pulls or upstream idle drive.
  • Pass criteria (X): external actuation events = 0 under all sequencing permutations within a Y-second window.
Scenario: glitch immunity (short pulses and spikes)
  • Trigger: short input pulses, crosstalk spikes, or threshold-near noise bursts.
  • Symptom: output glitch pulses or unintended state changes.
  • Root cause: insufficient pulse-width rejection or ramp-region threshold sensitivity.
  • Fix: enforce minimum valid pulse width; apply debounce/filters; use safe-state gating on critical outputs.
  • Pass criteria (X): pulses < X ns produce no valid output events; false events = 0 over N trials.
Scenario: diagnostics / watchdog paths (if available)
  • Trigger: fault/status pins change during UVLO/OT/abnormal conditions.
  • Symptom: unclear field root cause (power vs isolation vs upstream logic).
  • Root cause: status signals not captured, latched, or correlated with events.
  • Fix: log UVLO/reset/fault counts; define latch/clear policy; avoid retry storms on recovery.
  • Pass criteria (X): logged events match injected stress cases; clear policy does not re-trigger faults.
Black-box records (minimal set for field debugging)
  • UVLO entry count and duration (per rail side).
  • Reset/restart count and time-to-stable after power transitions.
  • False-toggle/glitch event counters with a fixed observation window.
Power/Fail-Safe State Machine OFF → RAMP → ON (Fail-Safe Contract) OFF RAMP ON Default Hi-Z LOW UVLO active Safe state Valid data Normal Primary-first Secondary-first HIGH Option Define outputs during OFF/RAMP to prevent unsafe actions Validate both sequences and brownout recovery

H2-9. Layout & Isolation Barrier Implementation: Partition, Return Paths, Creepage/Clearance Hooks

Isolation reliability is primarily a PCB implementation problem: partition, return paths, and barrier keepout define success more than component selection.
The barrier must be treated as an electrical boundary. The most common field failures come from hidden bridges across the slot, broken reference planes near the boundary, and unintended return paths created by copper pours, vias, silk, contamination, or measurement wiring. This section provides implementation hooks without duplicating safety-regulation text.
Do: partition and return-path rules that prevent hidden coupling
Partition hard rules
  • Primary/secondary planes: keep copper and reference planes strictly separated; maintain continuity within each domain.
  • Barrier keepout: enforce a no-copper/no-via zone near the slot; avoid test pads, exposed copper, and stitching vias near the boundary.
  • Slot as an electrical boundary: treat the slot as “no return path crossing,” not merely a mechanical gap.
  • Edge containment: keep fast-edge routes away from the slot so their reference plane stays intact and local.
Return paths and loop area control
  • Local return: route signals so the return current closes within the same domain; minimize loop area.
  • Reference integrity: avoid cutting reference planes near fast lines; do not route over split planes close to the barrier.
  • Decoupling placement: place decouplers tight to each-side supply pins; keep the supply-current loop compact per domain.
  • Measurement discipline: ensure probes and cables do not create an accidental ground bridge across the barrier during validation.
Creepage/clearance implementation hooks (no regulation text)
  • Slot geometry: use a slot to lengthen surface paths; avoid exposed copper edges near the slot.
  • Vias and copper traps: keep vias away from the boundary to avoid contamination traps and field concentration points.
  • Silk/mask policy: avoid long silk lines near the slot; keep solder mask openings controlled to reduce pollution paths.
  • Connector/chassis proximity: keep barrier region away from metal edges and connectors unless a controlled design requires it.
Don’t: common layout patterns that create cross-barrier bridges
  • Do not route across the slot (signals, shields, copper pours, or “temporary” ECO wires).
  • Do not allow return current across the barrier via plane stitching, cable shields, or probe grounds.
  • Do not place vias/test pads near the slot that can collect residue and form a hidden surface path.
  • Do not break reference planes for fast-edge routes near the barrier; it forces large loops and radiated coupling.
  • Do not leave inputs floating near the barrier; noise and dv/dt coupling can be interpreted as activity.
Quick layout review checklist
  • Barrier keepout is truly empty: no copper, no vias, no test pads, no silk “bridges.”
  • Critical fast lines stay away from the slot and keep a continuous reference plane within the same domain.
  • Decouplers are near pins; power loops are compact on both sides.
  • No accidental bridges exist: shields, mounting hardware, measurement fixtures, or solder residues.
PCB Partition & Return Path Rules PCB Partition & Barrier Keepout (Concept) Primary plane Secondary plane Slot Keepout Keepout Bad trace Bad return Good Good Vias Copper Keep return paths inside each domain; never cross the slot Enforce keepout near the barrier to avoid hidden bridges

H2-10. Validation & Production Tests: CMTI Stress, EFT/ESD, Timing Corners, Documentation

Validation must close the loop with repeatable setups, observation windows, and counter-based pass criteria (X/Y/N), then map into production screening and traceability.
A practical plan defines timing and power behavior across corners, quantifies immunity failures during stress, and documents the exact stimulus and counting method. Production tests should separate 100% screening from sampling, and every test result must be traceable to board/BOM/fixture/script versions.
Validation matrix (card list, mobile-safe)
Test case: timing corners
  • Setup: defined source/load; controlled VDD1/VDD2; temperature corner.
  • Stimulus: edge rate and toggle rate representative of the system.
  • Observe: tPD, tSK, PWD with a fixed statistics window.
  • Pass criteria: worst-case tPD ≤ X ns; skew ≤ Y ns; PWD ≤ N ns.
Test case: activity-rate power and wake overhead
  • Setup: current measurement on each rail; controlled input states.
  • Stimulus: Sleep/Mid/Full patterns; wake bursts at controlled frequency.
  • Observe: IAVG over Y minutes and wake count per hour.
  • Pass criteria: IAVG ≤ X mA; false wakes ≤ N/hour.
Test case: fail-safe defaults and sequencing
  • Setup: controllable power sequencing for both sides; event capture on outputs.
  • Stimulus: primary-first, secondary-first, and brownout recovery cycles.
  • Observe: false output events and time-to-stable.
  • Pass criteria: unsafe actions = 0; stable recovery ≤ X ms over N cycles.
Test case: EFT/ESD-triggered error counting
  • Setup: defined pattern; capture/counter with a fixed observation window.
  • Stimulus: stress events; repeat count N times with consistent coupling path.
  • Observe: bit errors, false toggles, resets, and recovery time.
  • Pass criteria: error count ≤ X within Y seconds; recovery ≤ Y ms.
Test case: CMTI / dv/dt injection (system-level definition)
  • Setup: define dv/dt node, polarity, and measurement point for slope.
  • Stimulus: dv/dt ramp with target slope ≥ X kV/µs; repeat N cycles.
  • Observe: false transitions and error counts within window Y.
  • Pass criteria: false transitions = 0 over N cycles at defined dv/dt.
Production tests and traceability (what to screen vs sample)
100% screening candidates
  • Functional signature (known pattern), basic timing bounds, and safe default behavior on controlled power cycling.
  • Basic continuity and boundary sanity checks that detect accidental cross-barrier bridges.
Sampling / audit candidates
  • EFT/ESD stress audits, dv/dt injection audits, and extended corner runs.
  • Long-window false-event counting to detect rare restart or glitch patterns.
Trace fields to store with each test record
  • Board revision, BOM revision, fixture revision, script version, and firmware version.
  • Date/lot identifiers and the exact pass-criteria thresholds used (X/Y/N).
Documentation strategy (kept brief)
Test plans should reference certificates and safety reports through a controlled document list; detailed standard clauses and compliance mappings are handled in the Safety & Compliance page to avoid duplication.
Validation Test Path (Concept) Validation Test Path (Concept) Source Pattern DUT Isolator Capture Receiver Counter Logger window threshold dv/dt • EFT • ESD Define stimulus, observation window, and counters before testing Pass criteria uses X/Y/N placeholders for repeatability

H2-11. Engineering Checklist & Selection Logic: Spec Priorities + Quick Pairings

Goal: turn datasheet specs into a repeatable selection + verification flow (bring-up → EVT → DVT → PVT), with measurable pass criteria (X/Y/N placeholders) and a short, non-overlapping pairing shortlist.

Selection priority (do not reorder)
  1. Safety gate: insulation class + working voltage + lifetime model → then choose “basic / reinforced” (details stay on Safety & Compliance page).
  2. CMTI target: set dv/dt environment goal (kV/µs-class) + define injected waveform + counting window.
  3. Timing: propagation delay + skew + pulse-width distortion + corners (Temp/VDD/load) → budget as a system window.
  4. EMI coupling: barrier capacitance / edge-rate strategy → minimize common-mode current into the secondary reference.
  5. Power: static vs dynamic power, enable pins, low-power/auto-wake interactions, default output levels on power-down.
  6. Channel topology: 1ch/2ch/4ch, direction mix (e.g., 1/1 or 3/1 or 2/2), and whether channels must be matched on the same die.
  7. Package & layout fit: creepage/clearance, pinout that enforces partitioning, decoupling geometry, and test access.
Example capacitive digital isolator families (part numbers):
  • 2ch (1/1): TI ISO7721 (and automotive ISO7721-Q1), Diodes Inc API7722 (1 forward / 1 reverse)
  • 2ch (2/0 same direction): Diodes Inc API7720 (both channels same direction)
  • 4ch (3/1): TI ISO7741 (and automotive ISO7741-Q1)
  • 4ch (2/2): TI ISO7742 / higher isolation option ISO7842
Note: exact suffix/package selects default output options, creepage width, and sometimes automotive control; keep the decision on this page, keep ordering details on BOM pages.
Engineering checklist (measurable + stage-based)
Bring-up (bench sanity)
1) Power-up defaults & enable behavior
Verify: output default state during UVLO / power-down / enable toggle.
How: step VDD1/VDD2 independently; monitor outputs + downstream safe-state pin(s).
Pitfall: assuming “input low” equals “output low” during brownout; missing Hi-Z behavior.
Pass criteria: no unsafe assertion; default matches system safe policy for X power cycles / Y corners; N=0 unsafe events.
2) Basic timing at room (tPD / skew / PWD)
Verify: propagation delay and channel-to-channel skew on the intended topology (e.g., 1/1 or 2/2).
How: same edge stimulus to all channels; measure at the final logic threshold point (not at probe-ring).
Pitfall: mixing probe grounds across barrier; measuring at different loads or different trigger points.
Pass criteria: (tPD, skew, PWD) stay within system window with margin ≥ X% over Y minutes; N=0 unexpected toggles.
3) Decoupling + edge-rate knob sanity
Verify: output edge quality and emissions sensitivity to drive strength / series R / return path geometry.
How: sweep series resistor (XΩ…YΩ) and note eye/overshoot + common-mode noise at the secondary reference.
Pitfall: optimizing only for “fastest edges” and later failing EMI due to CM current injection.
Pass criteria: stable logic with no overshoot beyond X V and no EMI regression > Y dB; N=0 link faults.
EVT (first system integration)
4) CMTI stress in real dv/dt environment
Verify: no false toggles during worst-case common-mode steps (power stage switching, long returns, cable harness).
How: inject representative dv/dt waveform; count errors in a fixed window; log event time correlation to switching edges.
Pitfall: validating only with “clean bench dv/dt” while real system has ringing + return-path bounce.
Pass criteria: dv/dt ≥ X kV/µs with Y repetitions yields N=0 false transitions.
5) Timing corners by system window (not by typical)
Verify: system-level setup/hold margins remain positive over Temp/VDD/load corners.
How: measure relative timing between signals that must align (e.g., multi-channel control strobes).
Pitfall: checking channels one-by-one instead of checking “relative alignment” at the receiving latch.
Pass criteria: worst-corner margin ≥ X ns across Y units; N=0 corner escapes.
6) Partition & “no return across barrier” audit
Verify: primary/secondary grounds do not get accidentally stitched by copper, via fences, shield cans, or probing.
How: layout review checklist + continuity tests + “near-slot copper” inspection and contamination path review.
Pitfall: accidental “quiet” bridge that makes bench look stable but fails EFT/ESD in the field.
Pass criteria: zero unintended DC bridges; creepage/clearance meets target with ≥ X mm margin; N=0 violations.
DVT (robustness & compliance readiness)
7) EFT/ESD susceptibility with counting window
Verify: transient events do not create silent logic corruption (glitch) or protocol-level misbehavior.
How: run a deterministic traffic pattern; count mismatches within a defined window; capture before/after states.
Pitfall: “pass” judged by no reset only; missing single-bit flips that break state machines later.
Pass criteria: at stress level X, duration Y, observed mismatch count N ≤ threshold.
8) Low-power mode + wake interaction scan
Verify: sleep IQ matches system budget AND wake behavior is stable (no wake storm / no missed wake).
How: sweep activity factor (sleep → mid → full toggle) and log wake counts per hour/day across corners.
Pitfall: meeting average power while failing user experience due to periodic false wake events.
Pass criteria: IQ ≤ X µA in sleep; wake false-positive rate ≤ N/Y hours.
9) EMC trade: edge-rate vs margin
Verify: chosen edge-rate (drive strength / series R) meets both timing margin and emission targets.
How: characterize timing margin as R increases; lock a “balanced” setting before final EMC tests.
Pitfall: fixing EMI late by adding too much R and silently violating setup/hold on cold/low-VDD corners.
Pass criteria: EMC improvement ≥ X dB with remaining timing margin ≥ Y ns; N=0 corner failures.
PVT (production control)
10) What to test 100% vs sample (traceability)
Verify: minimal production tests catch assembly escapes (solder bridges near slot, wrong variant, wrong default state).
How: 100%: digital continuity + direction check + default output check; sample: timing margin + stress spot checks.
Pitfall: skipping default-state verification and shipping a “suffix mismatch” that flips safety behavior.
Pass criteria: 100% tests detect ≥ X% of seeded faults; field returns for isolation issues ≤ N/Y units.
11) Documentation package for audits
Verify: certifications and reports are referenced correctly and version-controlled (CB report, UL file, VDE certificate).
How: store links + revision IDs in the product dossier; keep standard details on the Safety page to avoid duplication.
Pitfall: mixing report versions between EVT/DVT/PVT and losing traceability at audit time.
Pass criteria: all docs mapped to BOM revision X; audit checklist completion = Y/Y; N=0 missing items.
Quick pairings (short, non-overlapping)
MCU ↔ AFE / data-acq control
  • Isolation device: TI ISO7721 (2ch 1/1) or TI ISO7742 (4ch 2/2) / TI ISO7842 (4ch 2/2, higher isolation)
  • When it fits: low latency control strobes + deterministic alignment across channels.
  • First verification hook: multi-signal skew budget + corner margin at the receiving latch.
MCU ↔ power stage control (noise / dv/dt)
  • Isolation device: TI ISO7721 / TI ISO7742; Diodes Inc API7722 (1/1) for compact dual-signal control
  • Pairing examples (driver page holds details): TI UCC21520 (isolated dual gate driver), TI UCC21750 (isolated SiC driver)
  • First verification hook: dv/dt injection test with a fixed counting window (X/Y/N) + “no return across barrier” layout audit.
Multi-channel mixed control (direction + skew)
  • Isolation device: TI ISO7741 (3/1) or TI ISO7742 / ISO7842 (2/2)
  • Alt compact dual: Diodes Inc API7720 (2 same direction) / API7722 (1/1)
  • First verification hook: channel-to-channel skew across Temp/VDD corners; verify that edge-rate tuning does not break alignment.
Note: clock paths that require sub-ps jitter isolation stay on the “Low-Jitter Clock Isolator” page; do not force general-purpose isolators into that role.
Diagram: Selection decision tree (Use case → Safety → CMTI → Timing → EMI → Power → Package)
Use case Signals, direction (1/1, 3/1, 2/2), data rate, latency window Safety gate Basic vs reinforced, working voltage, creepage fit (then lock package width) CMTI target Define dv/dt waveform + counting window (X/Y/N) for “no false toggle” Timing budget tPD + skew + PWD + corners (Temp/VDD/load) vs system window EMI / coupling Barrier coupling + edge-rate knobs (drive / series R / return path) Power & defaults Static vs dynamic power, enable pins, UVLO default state, wake behavior Example mapping: ISO7721 / ISO7741 / ISO7742 / ISO7842 · API7720 / API7722 Lock direction + default state by suffix; verify with X/Y/N windows before finalizing BOM
Diagram usage: keep node text short; treat it as the review checklist during design reviews and when explaining selections in documentation.

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H2-12. FAQs (Field Debug & Acceptance Criteria)

Scope (do not expand)

These FAQs only close out long-tail field failures and acceptance language. No new knowledge domains are introduced.

Data format (X / Y / N)
  • X = threshold (with unit): dv/dt, ns, dB, Ω, kV, etc.
  • Y = window: seconds/minutes, shots, cycles, temperature range, or corner set.
  • N = count limit: false toggles, bit flips, resets, retrains, or mismatches allowed.
Tip: treat “Pass criteria” as test-plan-ready text. Keep the metric definition consistent across labs and fixtures.
Accordion (each answer is fixed 4 lines)
1) Eye/waveform looks good, but the system still false-toggles — check measurement window or glitch filter first?
Likely cause: metric window/denominator mismatch or probing/threshold mismatch hides narrow glitches.
Quick check: standardize the counter window + reset points; re-measure at the receiver threshold with identical load/trigger.
Fix: align glitch filter (min pulse width) to system noise; tighten probing/return to avoid cross-barrier artifacts.
Pass criteria (X/Y/N): false toggles ≤ N within Y s under defined stimulus X (metric=FALSE_TOGGLE; X=stimulus level; Y=window; N=count).
2) Same board, very different CMTI results across labs — dv/dt definition or fixture return path?
Likely cause: dv/dt is not measured at the same node (ringing/overshoot differs) and fixture return geometry changes CM injection.
Quick check: capture VCM(t) at device pins (same bandwidth/termination); photograph fixture return points and cable routing.
Fix: lock a dv/dt waveform template + measurement node; standardize fixture return and probing rules.
Pass criteria (X/Y/N): CMTI outcome consistent within ±X% across Y labs/fixtures; mismatch count N ≤ limit (metric=CMTI_RESULT_SPREAD; X=%; Y=labs; N=out-of-family runs).
3) Delay drifts with temperature and timing margin collapses — check VDD corner or load change first?
Likely cause: worst-case tPD/PWD occurs at a Temp/VDD/load corner not covered by “typical” measurements.
Quick check: sweep temperature while holding load constant; then sweep VDD while holding temperature; compare which axis moves tPD/PWD more.
Fix: re-budget timing with corners; adjust edge-rate/series R only after confirming receiver threshold noise is not dominating.
Pass criteria (X/Y/N): worst-corner tPD ≤ X ns and skew ≤ X ns across Y corners; failures N=0 (metric=TIMING_CORNER_FAIL).
4) Added series R fixed EMI, but timing now fails — budget PWD/edge-rate or threshold noise first?
Likely cause: edge-rate slowed enough to violate receiver window (PWD shrink/shift) or increased susceptibility near threshold.
Quick check: sweep series R in steps; measure PWD + receiver threshold crossing jitter, not just “looks clean” at the pin.
Fix: choose the minimum R that meets EMI; if needed, change load/termination strategy and re-validate corners.
Pass criteria (X/Y/N): EMI margin ≥ X dB while timing margin ≥ X ns over Y corners; timing failures N=0 (metric=EMI_TIMING_TRADE_FAIL).
5) After power-cycle, default state causes a wrong action — how to accept UVLO/default behavior?
Likely cause: default output state during UVLO/ramp differs from the assumed safe level; enable sequencing is not enforced.
Quick check: independently ramp VDD1/VDD2; record output level/Hi-Z during OFF→RAMP→ON and during brownout.
Fix: gate downstream actions with an explicit “power-good/enable” policy; select a variant/suffix whose default matches the system safe state.
Pass criteria (X/Y/N): unsafe assertions N=0 across Y power cycles with ramp profile X (metric=UNSAFE_DEFAULT_EVENT; X=ramp profile; Y=cycles; N=count).
6) Multi-channel channels interfere with each other — shared decoupling impedance or barrier asymmetry?
Likely cause: supply/ground common-impedance coupling or pin/package coupling causes correlated jitter/false edges across channels.
Quick check: run one channel at full toggle and others static; correlate error events to aggressor activity and VDD ripple.
Fix: tighten per-side decoupling loop, split high-edge returns, and keep high-speed traces away from the barrier edge/slot.
Pass criteria (X/Y/N): victim errors ≤ N within Y s at aggressor toggle rate ≥ X (metric=CHANNEL_CROSSTALK_ERROR; X=toggle rate; Y=window; N=count).
7) ESD hit triggers retrain/reset — where is the first return-path checkpoint?
Likely cause: ESD current returns through signal reference paths, injecting a fast CM step across the barrier and upsetting logic/rails.
Quick check: identify where ESD current is supposed to go (chassis/earth) and verify no unintended return through secondary ground near the isolator.
Fix: shorten the ESD return to chassis, keep barrier-edge copper clean, and prevent “across-slot” bridges (copper/vias/shields/probing).
Pass criteria (X/Y/N): at ESD level X, over Y shots, retrains/resets ≤ N (metric=ESD_RETRAIN_RESET; X=ESD level; Y=shots; N=count).
8) Low-power mode sees sporadic false wake — EMI injection or debounce strategy?
Likely cause: threshold-adjacent noise + CM injection produces short pulses that the wake path treats as valid.
Quick check: log wake timestamps; correlate to switching/EMI sources; temporarily disable auto-wake to separate “wake-path” from “data-path” issues.
Fix: add wake gating + minimum pulse qualification; reduce CM injection via return-path tightening and edge-rate control.
Pass criteria (X/Y/N): false wakes ≤ N per Y hours under environment X (metric=FALSE_WAKE; X=environment; Y=time; N=count).
9) High dv/dt environment causes occasional bit flips — check barrier-edge copper or switching loop area first?
Likely cause: displacement current from dv/dt finds a “bad loop” through barrier-adjacent copper and secondary reference bounce.
Quick check: inspect barrier-edge copper/vias/guarding; measure dv/dt and ringing at the real node; compare flips with switching edges.
Fix: enforce barrier keepout + slot discipline; compact switching loops; reduce CM injection by return-path control and edge-rate tuning.
Pass criteria (X/Y/N): bit flips ≤ N over Y cycles at dv/dt ≥ X kV/µs (metric=BIT_FLIP; X=dv/dt; Y=cycles; N=count).
10) Same footprint, different vendor makes EMI worse — first sanity check: barrier capacitance or edge-rate?
Likely cause: different effective barrier coupling and output edge characteristics change common-mode current into the secondary.
Quick check: compare CM noise at the secondary reference under identical drive/loads; sweep series R to see which device is more sensitive.
Fix: lock edge-rate (series R/drive) per device; if EMI margin is tight, choose a lower-coupling option and re-validate timing corners.
Pass criteria (X/Y/N): EMI margin ≥ X dB with timing failures N=0 over Y corners (metric=VENDOR_SWAP_EMI; X=dB; Y=corners; N=fails).
11) Production test passes, but field sees sporadic flips — counter window/denominator or harness/fixture difference?
Likely cause: acceptance metric differs between factory and field, or field wiring/returns create stronger CM injection than the fixture.
Quick check: verify counter reset timing + denominator definition; reproduce with field harness on the bench using the same window.
Fix: unify measurement definition and add event logging (timestamp + dv/dt correlation); tighten layout return-path controls near the barrier.
Pass criteria (X/Y/N): field fault rate ≤ N per Y hours under condition X (metric=FIELD_FAULT_RATE; X=condition; Y=time; N=count).
12) Same device, different lot behaves differently — check corner conditions, supply ripple, or variant mismatch first?
Likely cause: system corners (Temp/VDD/ripple/load) shift the effective margin; or a package/suffix variant changes defaults/drive behavior.
Quick check: record Temp/VDD/ripple during failures; confirm exact ordering code/suffix; re-run timing and CM noise under the same conditions.
Fix: tighten power filtering/decoupling, lock variant selection, and derate margins to cover worst observed conditions.
Pass criteria (X/Y/N): spread of key metrics ≤ X% across Y lots; excursions N ≤ limit (metric=LOT_TO_LOT_SPREAD; X=%; Y=lots; N=outliers).

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