CMTI & dv/dt: 50–150 kV/µs Immunity for Digital Isolation
← Back to: Digital Isolators & Isolated Power
CMTI is not a slogan number—it is the system’s ability to survive a defined dv/dt environment with zero false toggles. This page turns “≥50–150 kV/µs” into a controllable chain (Ctotal → ICM → Zreturn → Vbounce) plus testable pass criteria.
H2-1. Definition & Why It Breaks Systems
Key takeaways (engineering meaning)
CMTI is not a marketing number; it is the maximum common-mode transition rate the isolation path can tolerate without producing a functional error under specified conditions.
Engineering definition (testable & auditable)
A system-level CMTI statement should always bind (1) the common-mode stimulus, (2) the DUT configuration, and (3) the pass/fail criterion.
- Common-mode step amplitude: VCM = X V (or kV)
- Edge rate: dv/dt = X kV/µs (rise/fall shape matters)
- Repetition: single-shot or repetitive at Y kHz
- Supply rails: VDD(min/typ/max), decoupling stated
- Load model: pull-up, capacitive load, cable/fixture
- Logic mode: channel direction, default state, enable pins
- No false switching: no unintended edges at output
- No bit error: BER ≤ X over Y seconds (or 0 observed)
- No functional upset: no reset, latch, UVLO event
- Different labs can report different outcomes if any of the above is unspecified.
- “150 kV/µs” is meaningless unless the stimulus + criterion match the real system.
Boundary guard: This chapter defines what immunity means. It does not derive physical coupling equations (handled later in the mechanisms/budget chapters).
How it breaks systems (observable signatures)
A dv/dt event rarely “looks like an error” at the source. It breaks the system when injected transients cross a decision boundary (threshold or sampling window).
- Glitch crosses threshold: a narrow pulse becomes a counted edge or a logic flip.
- Sampling-window hit: a glitch aligned with sampling creates a deterministic bit error.
- Reference bounce: local ground shift alters input margin and produces sporadic toggles.
- State upset: receiver enters an invalid state, resets, or locks until power-cycle.
- Secondary-side collateral: false enables, spurious interrupts, or corrupted serial framing.
Where “≥50–150 kV/µs” typically appears
High dv/dt is not only a number; it also implies large common-mode swings, high repetition, and complex return paths.
- SiC/IGBT half-bridges: fast edges + large VCM + switching bursts.
- Isolated power stages: switching nodes near the barrier with rich harmonic content.
- Gate-drive loops: rapid node motion couples into control/reference domains.
- Long cables / remote nodes: common-mode current excites harness return impedance.
Diagram: dv/dt source → barrier coupling → victim threshold
The failure path is a closed loop: edge stress drives barrier coupling, which creates a victim-side decision error.
H2-2. CMTI vs dv/dt: Metrics, Units, and Common Misreads
Definitions (keep the vocabulary consistent)
dv/dt (kV/µs) describes the edge rate of the common-mode stimulus in the application environment.
CMTI (kV/µs) describes the maximum dv/dt the isolation path can tolerate without a defined error, under specified test conditions.
A valid statement always binds: VCM amplitude, edge shape, repetition, VDD, load, temperature, measurement setup, and error criterion.
Boundary guard: This chapter aligns metrics and prevents misreads. It does not choose a device class (handled in the selection chapter).
Common misreads (why “same number” can fail in the field)
- Misread 1 — ignoring VCM amplitude: the same dv/dt with larger amplitude can drive more displacement energy into the victim domain.
- Misread 2 — ignoring edge shape: ringing/overshoot can create multiple crossings even if the nominal dv/dt is unchanged.
- Misread 3 — ignoring repetition: repetitive bursts can heat, shift bias, and reveal recovery weaknesses not seen in single-shot tests.
- Misread 4 — ignoring load and pull structures: push-pull vs open-drain changes how glitches translate into logic edges.
- Misread 5 — ignoring timing context: propagation delay, skew, and jitter define whether a glitch lands inside the sampling window.
- Misread 6 — ignoring measurement setup: probe ground loops and bandwidth limits can hide or invent “glitches.”
- Misread 7 — ignoring “what counts as error”: a waveform artifact is not a failure unless it violates the system’s criterion.
3-step normalization (fastest way to reconcile datasheet vs system)
- VCM step amplitude = X
- dv/dt edge shape (single edge vs ring)
- Repetition = Y (single-shot vs burst)
- Allowed false edges = 0 / test
- BER limit = X over Y time
- No reset / latch / UVLO event
- Probe bandwidth and grounding stated
- Trigger window aligned to sampling
- Fixture/cable model documented
- If any step differs, “same CMTI” can legitimately produce different results.
- Only after normalization does a numeric comparison become meaningful.
Diagram: one CMTI number depends on conditions
A datasheet CMTI value is valid only when tied to its stimulus, DUT configuration, and error criterion.
H2-3. Physical Mechanisms: How dv/dt Injects Across the Barrier
Minimal model (the controllable knobs)
dv/dt immunity can be reduced to a closed-loop chain that is both measurable and designable. The barrier does not “see” dv/dt directly; it sees displacement current driven through an effective coupling capacitance.
- Ctotal: barrier + package + PCB parasitics (all cross-gap coupling paths).
- Zreturn: the victim-side return impedance that the injected current must traverse.
- Decision boundary: input threshold and sampling window define whether a transient becomes a counted edge/bit error.
Where the current goes (the return path decides the damage)
The injected current must close a loop. The dominant failure mechanism is often not “too much dv/dt” but a victim-side reference that moves because the return path is long, shared, or inductive.
- Fast edge at a switching node creates a common-mode step.
- Ctotal couples the step into the secondary domain as ICM.
- ICM flows into the secondary reference network (ground/shield/return).
- If the return impedance is high, even modest ICM creates a large Vbounce.
- Inductance dominates at fast edges; loop area matters.
- Shared returns convert a local disturbance into a multi-signal upset.
Design focus: reduce Ctotal, reduce Zreturn, and harden the decision boundary (threshold/window). Later chapters provide layout and validation methods; this chapter locks the mechanism.
What else gets triggered (transient paths inside the device)
A dv/dt event can enter multiple internal nodes. The system-visible symptom depends on which block is disturbed and whether recovery occurs before the next sampling/logic decision.
- Input threshold/comparator upset: a momentary shift changes whether a pulse is recognized as an edge.
- Output stage transient: push-pull recovery and edge shaping determine whether a glitch widens.
- ESD/clamp interaction: fast displacement current can forward-bias transient structures and redirect current paths.
- Bias perturbation: local supply droop or reference bounce can extend the upset into a functional reset/latch.
Diagram: Ctotal displacement current and the complete return loop
The barrier-coupled current forms a loop. The victim-side return impedance converts ICM into Vbounce, which can cross a threshold or land inside a sampling window.
H2-4. Device-Level Knobs: What in the Isolator Actually Improves CMTI
Knob map (device features mapped to system variables)
“Higher CMTI” is not a single magic feature. It is the combined effect of reducing injection, hardening the decision boundary, and improving recovery under repetitive stress.
- Lower effective coupling into sensitive nodes (Ctotal seen by the victim path).
- Control parasitic paths through package and internal partitioning.
- Input conditioning, encoding, hysteresis, and deglitch behavior.
- Timing robustness to prevent window hits (skew/jitter sensitivity).
- Output stage transient recovery and bias resilience.
- Resistance to repetitive bursts without lockup or accumulated upset.
- Multi-channel adjacency, shared-supply bounce, mixed-direction coupling.
- Channel isolation and supply-domain separation reduce cross-channel upset.
Capacitive vs magnetic (system view, not micro-structure)
Different isolation families implement the same immunity objective using different coupling and conditioning strategies. At the system level, the key is how each family shapes injection, decision tolerance, and recovery.
- Capacitive isolators: often optimized for high speed and strong transient immunity when coupling paths and supplies are well controlled.
- Magnetic/inductive isolators: often favored where robustness across temperature and harsh transients is prioritized.
- Opto-replace isolators: often chosen for legacy pin/timing compatibility with improved stability over aging calibration expectations.
Boundary guard: This chapter describes device-level knobs in abstract terms. Safety ratings and insulation classes are handled in the Safety & Compliance page to avoid duplication.
Multi-channel / mixed-direction pitfalls (why only one lane fails)
A system can report “CMTI failure” even when the barrier is adequate, because shared impedance and adjacency couple stress from one lane into another.
- Shared-supply bounce: one channel’s transient perturbs a shared VDD/reference and shifts thresholds across lanes.
- Adjacency coupling: neighboring channels inject into each other through internal/packaging parasitics.
- Direction mix: mixed input/output directions can create asymmetric recovery and window sensitivity.
- Diagnostic clue: failures correlate with activity on a different channel or with enable/state transitions.
Diagram: three isolator families (coupling path + conditioning + supply domain)
Device families can be represented by the same three blocks. CMTI differences usually come from how each block is implemented and how multi-channel coupling is handled.
H2-5. System-Level Spec Writing: Turn “≥50–150 kV/µs” Into Requirements
Why “CMTI ≥ X” is not a requirement
A system requirement must be measurable, reproducible, and auditable. A single number without test conditions turns into lab-to-lab disagreement and ambiguous field decisions.
The 3-part requirement (field-ready)
A complete CMTI requirement binds three elements. If any element is missing, the statement becomes a slogan.
- dv/dt: X kV/µs (edge shape noted)
- VCM range / step: X V (or kV)
- Profile: single-shot or burst at Y kHz
- VDD: min/typ/max; local decoupling defined
- Load model: pull-up / Cload / fixture / cable
- Channels: direction, enable state, default state
- false toggle: 0 edges within the window
- BER: ≤ X over Y seconds (or 0 observed)
- events: reset/latch/UVLO = 0
- All three blocks must be documented for repeatability.
- Comparisons are valid only after condition normalization.
Boundary guard: This chapter defines how to write requirements. Test implementation details appear in the validation chapter, and layout actions appear in the partition chapter.
Frequency & repetition (single-shot is not enough)
A single pulse checks instantaneous immunity. Repetitive stress checks recovery and accumulation effects that can appear only during bursts.
- Goal: no false edge during a defined observation window.
- Useful for: basic mechanism verification and quick screening.
- Risk: may miss recovery weaknesses under burst conditions.
- Goal: no accumulated upset across N pulses at Y kHz.
- Captures: bias perturbation, output recovery, temperature rise.
- Required when: switching environments repeat at high rate.
Margin tiers (design vs validation vs production)
One condition set cannot serve all phases. Separate targets prevent over-testing early and under-testing late.
- Design target: drives architecture and placement decisions; uses conservative environment assumptions.
- Validation target: verifies corner cases and repetition profiles; aligned to acceptance criteria.
- Production screen: fast and repeatable checks to catch assembly/fixture drift without duplicating full validation.
Diagram: requirement template (Environment → DUT config → Pass criteria)
A requirement becomes enforceable only after environment, configuration, and pass criteria are written in a structured form. The placeholders X/Y/N are intentionally explicit for auditability.
H2-6. Layout & Partition: The #1 Determinant You Actually Control
Partition rules (hard boundaries that prevent coupling)
Partitioning controls two dominant variables: effective cross-gap coupling (Ctotal) and victim-side return impedance (Zreturn). A clean partition makes the return path short and predictable while avoiding unintended cross-gap capacitive plates.
- Define two islands: Primary island and Secondary island; keep each island’s return paths self-contained.
- No return across the gap: avoid copper, stitching, or signal routing that creates a hidden cross-gap return.
- Keepout discipline: establish a no-route/no-copper corridor around the isolation gap where required by design rules.
- Reference control: keep sensitive references (receiver ground, comparator reference) away from the gap edge.
Copper strategy (reduce Ctotal without inflating Zreturn)
Copper near the isolation gap increases parasitic coupling. Over-aggressive copper removal can lengthen return paths. The objective is to reduce cross-gap plate area while keeping local returns short.
- Short, local return paths on each side (tight loops).
- Controlled copper boundaries near the gap (no broad facing planes).
- Dedicated return for sensitive lanes where practical.
- Large plane-to-plane facing area across the gap (Ctotal increases).
- “Accidental capacitors” from overlapping copper pours.
- Long return detours created by excessive voiding (Zreturn increases).
Guard ring / slot (control the field and the return)
Slots and guard structures are tools to shape coupling and force current into predictable paths. Used incorrectly, they can create long detours that increase return impedance.
- Slot effect: reduces effective cross-gap coupling by interrupting field paths and facing copper area.
- Guard effect: provides a controlled sink/route for parasitic currents instead of uncontrolled injection.
- Rule: any guard structure must not cause the victim return path to detour or share high impedance with other lanes.
Boundary guard: insulation distance values and safety standards are handled in the Safety & Compliance page. This chapter focuses on coupling and return control.
Routing priority (which nets are most sensitive)
Sensitivity is determined by threshold/window vulnerability and recovery behavior. The most sensitive nets should have the shortest, cleanest local returns and the largest separation from the gap.
- Highest sensitivity: gate-drive control edges, sampling/comparator-related inputs, clock/sync edges.
- Medium sensitivity: fast digital lines where short glitches can be captured by sampling windows.
- Lower sensitivity: slow status lines; still vulnerable when used as enable/reset signals.
Diagram: typical placement & partition (with common mistakes)
A correct partition keeps return paths inside each island and avoids broad copper facing across the gap. Common mistakes create hidden coupling plates or force return detours that amplify Vbounce.
H2-7. Barrier Capacitance, CM Emission, and the Y-Cap Trade
The conflict triangle: quieter, safer, but leakier
Common-mode behavior is a system trade. Improving radiated/conducted emissions can create a stronger common-mode return path, which may increase dv/dt-coupled injection and leakage. The correct choice depends on the stress environment and acceptance criteria.
Barrier capacitance: why C matters at system level
The barrier and everything that faces it behaves like an effective coupling capacitor. Under fast edges, displacement current scales with the effective cross-gap capacitance, and the victim-side return impedance converts that current into bounce.
- Lower Cbarrier (or lower Ctotal): reduces injected ICM and typically helps dv/dt immunity.
- System reality: package and PCB parasitics can dominate Ctotal even when the device barrier is small.
- Edge strategy note (abstract): some systems rely on controlled return paths; changing C and returns can shift where CM energy closes.
Boundary guard: The goal here is to connect C and return paths to injection and emission behavior. Detailed EMC compliance procedures are handled elsewhere.
Y-cap: it is a return-path creator
A Y-cap is not “just a filter.” It deliberately creates a common-mode return path. This often reduces emissions, but it also increases cross-domain coupling and creates measurable leakage current.
- Provides a low-impedance CM return path → EMI can drop.
- Stabilizes floating references in some layouts.
- Raises effective Ctotal → injected ICM can increase.
- Creates leakage path → can conflict with medical/portable limits.
- Placement changes loop geometry → different dv/dt susceptibility.
Minimal closed loop: how much, where, and what to check
The decision can be closed with a minimal engineering loop without expanding into full standards detail.
- How much: choose the smallest value that meets EMI targets under representative system switching conditions.
- Where: place to minimize unintended loop area and avoid coupling into sensitive victim references.
- What to check: verify dv/dt immunity with the chosen return path in place (no false toggles / no event flags).
Practical note: a Y-cap decision should be evaluated against the same requirement structure defined earlier: stress profile + DUT configuration + pass criteria.
Diagram: Y-cap knob — EMI vs leakage vs dv/dt injection risk
Increasing Y-cap tends to reduce EMI by providing a CM return path, while increasing leakage and potentially increasing dv/dt-coupled injection. The risk direction depends on placement and the stress environment.
H2-8. Gate-Drive dv/dt Injection: Where CMTI Fails in Real Inverters
Why half-bridges are the worst dv/dt environment
In a real inverter, the switching node produces large common-mode steps with very fast edges. The combination of high dv/dt, high loop energy, and tight timing margins makes small injected transients visible as false edges or unintended turn-on behavior.
Two dominant injection paths (dv/dt → gate behavior)
Many “CMTI failures” are actually gate-drive injection problems. The dv/dt event couples into the gate network and the driver reference, then appears as a false transition at the isolated control boundary.
- Switch-node dv/dt couples through Cgd (Miller).
- Gate bump can cross the effective turn-on threshold.
- Loop inductance amplifies ringing and extends pulse width.
- Driver local reference moves with the switching transient.
- Reference motion maps into the isolator input/output decision boundary.
- Symptoms look like false edges, enable glitches, or sporadic resets.
Why it looks like a CMTI limit (but often is not)
System logs record an unexpected transition. Without mapping the injection path, the conclusion becomes “CMTI is insufficient.” In reality, the gate loop and the driver reference can amplify the same dv/dt event into a logic-level disturbance.
- Observation: false edge / unexpected state change / sporadic fault.
- Common misread: “the isolator CMTI number is too low.”
- Root mapping: dv/dt couples into gate + reference, then crosses the decision boundary.
Mitigation knobs (dv/dt-focused, minimal set)
The objective is to reduce gate bump amplitude and prevent reference motion from becoming a logic disturbance. Only dv/dt injection knobs are listed here.
- Minimize loops: tighten gate-drive current loops and local returns to reduce inductive amplification.
- Segmented gate resistance: shape edges to reduce Miller-driven gate bump while keeping switching losses controlled.
- Miller clamp: provide a controlled sink for injected current during high dv/dt transitions.
Boundary guard: full protection features (DESAT/SC/UVLO strategies) are outside this chapter. This section focuses on dv/dt injection paths only.
Diagram: half-bridge dv/dt → Cgd → gate bump (false turn-on path)
The switch-node dv/dt couples through the Miller capacitance into the gate network. Gate-loop inductance and reference motion can turn a short transient into a threshold-crossing event.
H2-9. Measurement & Validation: How to Test CMTI Without Fooling Yourself
Testing is a chain, not a point
A “CMTI test” is a full signal chain: dv/dt source → fixture → barrier coupling → victim reference → observation. Many false passes come from unintentional changes to coupling or return paths introduced by fixtures and probes.
Excitation traps: when the dv/dt is not what it claims
The source defines the stress profile. A clean but slow edge can look “safe,” while a realistic edge contains ringing, repetition, and common-mode amplitude that drive real injection.
- Edge realism: specify rise/fall shape and verify the actual dv/dt at the stress node (not only at the generator output).
- Common-mode amplitude: include VCM step range; dv/dt alone is incomplete without the CM swing.
- Repetition: single-shot and burst stress can produce different outcomes due to recovery and accumulation.
- Trigger bias: avoid “only the perfect edge is captured” behavior; worst cases can be phase-dependent.
Common false pass: measuring a slow, well-behaved step while the real system includes fast edges plus ringing and high repetition.
Probe & ground-loop traps: the measurement changes the system
Probe bandwidth, probe ground, and clip geometry can create a hidden return path that diverts common-mode current. This can reduce observed bounce and hide glitches that would occur in the real installation.
- Bandwidth: ensure the monitor can capture narrow glitches and ringing.
- Probe return: minimize ground lead loop area; avoid creating cross-domain “shortcuts.”
- Reference point: measure at the victim’s actual local reference, not a convenient chassis point.
- Glitch disappears when probe is attached or moved.
- Pass/fail changes with cable routing or bench grounding.
- Different labs see different results with “same” setup.
What to observe: waveform → logic → system
A useful validation plan records three layers: waveform artifacts, digital correctness, and system-level events. The pass/fail criteria must be defined before testing.
- Glitch amplitude and width at the decision node.
- Ringing duration and threshold crossings.
- False toggles, bit errors, counter increments.
- Protocol-visible faults under representative traffic.
- Reset, latch/lock events, watchdog triggers.
- State machine stalls and recovery behavior.
- “Ugly waveform” is not a fail unless it violates the defined criteria.
- “System reset” is a fail even if the captured waveform looks clean.
Validation matrix: cover the dimensions that move the boundary
A single condition is only one slice. A minimal matrix targets the variables that change coupling, return impedance, and decision threshold behavior.
- Temperature: shifts thresholds and recovery; include cold/hot corners.
- Supply voltage: include VDD min/typ/max; observe undervoltage susceptibility.
- Load: output structure, pull-ups, Cload, and cable/fixture models.
- Repetition: single-shot and burst profiles; include realistic repetition rates.
- Fixture/cabling: route variants and harness lengths that alter return paths.
Boundary guard: this chapter defines how to avoid measurement bias. The budgeting chapter converts stress into pass/fail margins.
Diagram: test fixture chain (source → barrier → victim monitor)
A trustworthy setup makes the stress profile explicit and keeps the monitor from creating a hidden cross-domain return. The “probe/ground loop” influence is shown as a separate path that can bias results.
H2-10. Budgeting Method: From dv/dt to ICM to Vbounce to Pass/Fail
Turn dv/dt into an auditable pass/fail margin
Budgeting converts an environment stress (dv/dt) into a victim-side disturbance (Vbounce) and compares it against decision thresholds and deglitch windows. This creates an explainable chain from layout and coupling choices to acceptance criteria.
Budget chain (minimal, computable, system-focused)
The chain is intentionally simple and conservative. Each stage maps to a physical knob and a measurable artifact.
- Use the worst-case switching edge rate at the stress node.
- Include ringing if it is present in the system environment.
- Includes barrier + package + PCB facing copper + any intentional Y-cap.
- Device Cbarrier alone rarely equals system Ctotal.
- Injected displacement current is the “attacker.”
- Higher dv/dt or higher Ctotal increases injected current.
- Defined by loop area, return geometry, and shared impedance.
- Fixtures and probe returns can accidentally change Zreturn.
- Victim-side bounce is the disturbance seen by thresholds/windows.
- Same ICM can produce very different Vbounce under different layouts.
- Compare Vbounce to threshold margin and deglitch window behavior.
- Translate into pass/fail using the defined acceptance criteria.
Make failures explainable (map symptoms to a stage)
A useful budget does more than estimate. It localizes the failure mechanism to a stage so changes become predictable and reviewable.
- If failure changes with copper/placement: Ctotal and Zreturn are moving.
- If failure changes with repetition rate: recovery/accumulation is moving the decision boundary.
- If different labs disagree: fixture and probe returns are likely changing the effective chain.
Boundary guard: this chapter stays at a system budgeting level. Detailed device micro-architecture and safety distance rules are not expanded here.
Diagram: budgeting pipeline (dv/dt → Ctotal → ICM → Zreturn → Vbounce → margin)
The pipeline compresses the system into a small number of knobs. The final decision compares disturbance against threshold/window margin to determine pass/fail.
H2-11. Design Checklist: Bring-Up → Pre-Compliance → Production
Quality gates (one-page execution view)
This checklist converts the page into stage-gated actions with explicit outputs: waveforms, counters/logs, matrix coverage, and pass criteria placeholders (X/Y/N). Each stage focuses on the variables that move the CMTI boundary.
Boundary guard: certification details (standards text, CB reports) are referenced as inputs only and not expanded here.
Gate 1 — Bring-Up (board-first-power → first dv/dt stress)
Objective: confirm the stress is real, locate the victim reference bounce, and enable system observability before running wide matrices.
- Stress node verification: capture dv/dt edge shape + ringing at the actual switching node.
- Victim reference: measure bounce at the victim’s local reference (not a convenient chassis point).
- Decision node: capture glitch amplitude/width at isolator input/output decision points.
- Trigger sanity: ensure worst-case capture is not “trigger-selected.”
- Primary/secondary keepout: no copper/return crossing across the isolation gap/slot.
- Return containment: verify no unintended return path “bridges” the barrier (including fixtures).
- Sensitive routing: clocks, gate-control, and sampling lines keep distance from the barrier edge.
- Placement check: confirm the isolator sits on the partition boundary, not inside a mixed copper island.
- Digital counters: false-toggle / CRC / framing / link-error counters enabled.
- System events: reset / lock-up / watchdog / fault flags logged with timestamps.
- Repro key: record the exact stress profile and fixture routing used to reproduce the issue.
- Waveform pack: screenshot IDs or file names (X files).
- Key peaks: Vbounce peak (X), glitch width (Y), event count (N).
- Decision: pass/fail with reproduction steps and fixture notes.
Bring-Up kit — example material part numbers (pick per voltage/speed)
The items below are common building blocks used to reproduce dv/dt stress, instrument victims, and validate isolation choices. Verify ratings, packages, and availability for the specific design.
Use pattern: keep at least one “stuff option” footprint per key knob (Y-cap pad, gate-R pad, RC snubber pad, pull-up pad) to accelerate bring-up debugging.
Gate 2 — Pre-Compliance (prove margin with a minimal matrix)
Objective: run a minimal but boundary-moving matrix to expose failures driven by temperature, supply, load/fixture, and repetition. Results should map failures back to the budgeting chain stages (dv/dt, Ctotal, Zreturn, decision boundary).
- Single-shot: confirm immunity with isolated events.
- Burst / repetition: include burst length (N) and repetition rate (X).
- Ring realism: include ringing if present in the system; do not “sanitize” edges.
- Temperature: cold (X°C) / hot (Y°C) corners.
- Supply: VDD min/typ/max (X/Y/Z).
- Load/fixture: cable/fixture variants that change Ctotal/Zreturn.
- Waveform evidence: Vbounce peak/shape per corner.
- Logic correctness: false toggle count = 0 (N=0) over Y minutes.
- System health: no reset/lock events (N=0) under stress duration X.
- Matrix record: conditions list + pass/fail per cell.
- Failure mapping: tag to dv/dt / Ctotal / Zreturn / decision stage.
- Margin statement: design target (X) / validation target (Y) / screen target (N).
Pre-Compliance fixtures — example material part numbers
Rule: only change one “boundary mover” per sweep (Ctotal OR Zreturn OR repetition), and keep the rest frozen for attribution.
Gate 3 — Production (spot-check + traceability)
Objective: convert the highest-risk CMTI failure modes into quick screens with consistent conditions and traceable records. This is not a re-validation; it is a controlled spot-check plus logging for field diagnostics.
- Stress profile: apply the defined dv/dt + repetition screen (X/Y).
- Logic errors: counters remain zero (N=0) during screen time.
- System events: no resets/locks (N=0) and expected recovery behavior.
- Trace: serial/lot + fixture version + routing note.
- Conditions: VDD (X), temp (Y), repetition (N), cable length (X).
- Signature: pass/fail + retest rule if fail (Y/N).
- Event log: UV/OT/SC/reset markers with clear/latch policy (Y/N).
- Counter snapshot: include before/after screen snapshots for audit.
- Screen report: X samples per lot or per 1000 units.
- Attachment link: record IDs for screen run data (X files).
Production equipment — example part numbers (screen/trace)
Keep scope tight: production screens must reuse the same stress definition used in validation to avoid “new test = new unknown.”
Diagram: stage → tasks → outputs (records + criteria placeholders)
A stage-gated flow ensures each phase produces concrete artifacts: waveforms, counters/logs, matrix coverage, and pass criteria (X/Y/N).
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H2-12. FAQs (Review / Acceptance / Field Rework)
Format & placeholders (X/Y/N)
Each answer uses the same four lines: Likely cause / Quick check / Fix / Pass criteria. Placeholders: X=threshold/limit, Y=time window or duration, N=allowed event count (often 0).
Boundary guard: FAQs only use concepts from this page (dv/dt profile, Ctotal, Zreturn, Vbounce, decision boundary, fixtures/probes, Y-cap trade).
