Isolated ADC for High-Side Sensing: Sync, EMC, and Selection
← Back to: Digital Isolators & Isolated Power
What is an Isolated ADC?
An isolated ADC combines three functions into a single device: analog-to-digital conversion in a floating/high-side domain, a certified isolation barrier, and an isolated digital interface that delivers conversion results to a low-side controller. The integration is mainly valuable when system requirements depend on deterministic timing, predictable EMC behavior across the barrier, and a cleaner verification/compliance evidence chain.
Definition in engineering terms
- Conversion happens on the high-side: the ADC samples and converts signals referenced to the floating domain.
- A barrier separates reference systems: high-side ground and low-side ground remain electrically isolated.
- Data crosses as isolated digital: conversion results traverse the barrier via a defined digital link.
- Behavior under stress is a design input: dv/dt and fast common-mode events can inject noise through the barrier; immunity and failure signatures matter.
Typical placement in real systems
- High-side/floating domain: shunt/phase voltage nodes, floating sensors, or measurement islands with large common-mode swings.
- Low-side/control domain: MCU/FPGA, control loops, logging, and system communications referenced to stable ground.
- Barrier boundary: the only intentional crossings are power (if required) and digital data/clock/sync; uncontrolled return paths must be eliminated by layout.
What “integration” changes vs ADC + external isolator
Why
Easier latency/skew budgeting for sampling-to-data delivery, and more predictable barrier-coupling behavior during dv/dt and EFT/ESD events.
When
High-side sensing needs deterministic timing, stable multi-channel alignment, and a system EMC story that is modelable and testable.
When NOT
If an external digital filter/bitstream pipeline is required, use Isolated ΔΣ Modulator. If flexible analog scaling/gain dominates, use Isolated Differential Amplifier + ADC.
Scope Guard (in-scope vs out-of-scope)
In-scope (this page)
Isolation-driven timing (latency/skew), EMC coupling across the barrier, power/reference partition, layout partition rules, verification/production tests, and selection logic for high-side sensing.
Out-of-scope (handled elsewhere)
ΔΣ bitstream/filter math, isolated amplifier design theory, protocol stack tutorials (SPI/I²C/UART/CAN/USB/Ethernet), and safety standard definitions (VDE/UL/IEC) beyond link-outs.
Where It’s Used: High-Side Sensing Scenarios
Isolated ADCs are most valuable when the problem is not only “conversion,” but a combination of large common-mode swing, fast dv/dt events, and timing alignment that must remain predictable across disturbance conditions. The scenarios below are framed as constraint sets to support fast architecture selection.
Four high-value use cases (constraint-driven)
Goal: Phase current/phase voltage sensing in motor/inverter control loops.
Key constraint: High dv/dt common-mode events + strict timing alignment across phases/channels.
Why isolated ADC helps: Sampling-to-data delivery can be modeled as a single chain, reducing ambiguity in skew/latency budgeting during switching noise.
Goal: High-voltage bus or battery stack monitoring with a floating measurement domain.
Key constraint: Working-voltage lifetime targets + predictable behavior under transient stress and long-term drift.
Why isolated ADC helps: Isolation grade and digital delivery are integrated, simplifying validation planning and reducing interface ambiguity.
Goal: Floating data acquisition modules in noisy industrial cabinets.
Key constraint: Ground potential differences + barrier coupling paths that excite cable/plane antennas.
Why isolated ADC helps: Common-mode injection paths become easier to locate and control (barrier coupling + return paths), improving EMC iteration speed.
Goal: Multi-channel synchronized sampling across isolated measurement islands.
Key constraint: Channel-to-channel skew + deterministic latency + predictable resync behavior.
Why isolated ADC helps: A tighter timing contract enables clearer system-level sync strategy, especially when multiple isolated nodes must align.
Practical selection note (no protocol deep dive)
- Strict alignment + predictable latency: isolated ADC is typically the first option to evaluate.
- High resolution with external digital filtering: route to the Isolated ΔΣ Modulator page.
- Analog scaling/gain before conversion dominates: route to Isolated Differential Amplifier + ADC architectures.
Architecture Options and Trade-offs
Architecture selection should be driven by isolation-related constraints: deterministic timing (latency/skew), predictable common-mode behavior (barrier coupling), and the size of the verification/compliance matrix. The comparisons below intentionally avoid protocol tutorials and ΔΣ/analog front-end theory, focusing only on latency, sync, EMI paths, BOM/area, and compliance effort.
Trade-off cards (mobile-friendly, no wide tables)
Monolithic Isolated ADC (integrated barrier + digital)
Discrete: ADC + Digital Isolator + Isolated Power
Adjacent Alternative: Isolated ΔΣ Modulator (bitstream + external filtering)
For ΔΣ fundamentals and filter/OSR design, route to Isolated ΔΣ Modulator.
Adjacent Alternative: Isolated Differential Amplifier + ADC
For high-linearity front-end and CMTI-focused measurement design, route to Isolated Differential Amplifier.
Isolation-Driven Specs That Actually Matter
These specifications should be interpreted as system behaviors, not just datasheet numbers. Each item below maps a spec to failure signatures (what shows up in the lab/field) and to a verification method that can be executed during bring-up and pre-compliance testing.
Spec → Why → Failure signature → How to verify
CMTI / dv/dt Immunity
Why: Fast common-mode transitions can inject transient currents across the barrier, causing bit errors, code glitches, or resets.
Failure signature: Stable on bench, but switching events trigger sporadic codes, framing errors, or sudden offset jumps.
How to verify: Reproduce dv/dt stress (real switching or controlled injection), log data integrity + supply droop + event correlation; pass within X errors over Y minutes.
Barrier Capacitance (Cbar)
Why: Displacement current scales with Cbar × dv/dt, driving common-mode emissions and injecting noise into reference/threshold nodes.
Failure signature: EMI fails without obvious functional dropouts, or errors appear “random” and sensitive to cable/ground changes.
How to verify: Sweep edge rate and return-path options; compare emission and error-rate deltas; pass when sensitivity is within X dB / X errors.
Digital Timing (Latency / Skew / Determinism)
Why: Control loops and multi-channel alignment require predictable sample-to-data delay and bounded channel mismatch.
Failure signature: Phase mismatch, calibration drift, or alignment that breaks only after resets/resync sequences.
How to verify: Apply common stimulus to channels, measure min/max/σ of delay and skew; verify after power cycles; pass when skew < X and latency spread < Y.
Working Voltage & Lifetime
Why: Long-term field reliability depends on sustained electric-field stress and board-level creepage/clearance execution.
Failure signature: Hi-pot/leakage results vary by build, or humidity/contamination correlates with failures.
How to verify: Define stress class and build cleanliness controls; run hi-pot/leakage consistency checks; pass when leakage < X and yield > Y%.
Power & Thermal (incl. no-load loss)
Why: No-load loss and self-heating shift references and drift, affecting accuracy and long-term reliability.
Failure signature: Values drift after minutes, or temperature changes amplify offset/gain error beyond expectation.
How to verify: Measure drift vs temperature and load states; correlate with device temperature rise; pass when drift stays within X over Y°C.
ESD / Surge / System EMC Coordination
Why: Device ratings must match board-level discharge paths; isolation does not remove the need for controlled return paths.
Failure signature: One lab setup passes while another fails; small grounding changes flip results.
How to verify: Pre-scan with controlled bonding/return configurations; document the pass configuration; pass when results repeat across setups within X margin.
Architecture Options and Trade-offs
Architecture selection should be driven by isolation-related constraints: deterministic timing (latency/skew), predictable common-mode behavior (barrier coupling), and the size of the verification/compliance matrix. The comparisons below intentionally avoid protocol tutorials and ΔΣ/analog front-end theory, focusing only on latency, sync, EMI paths, BOM/area, and compliance effort.
Trade-off cards (mobile-friendly, no wide tables)
Monolithic Isolated ADC (integrated barrier + digital)
Discrete: ADC + Digital Isolator + Isolated Power
Adjacent Alternative: Isolated ΔΣ Modulator (bitstream + external filtering)
For ΔΣ fundamentals and filter/OSR design, route to Isolated ΔΣ Modulator.
Adjacent Alternative: Isolated Differential Amplifier + ADC
For high-linearity front-end and CMTI-focused measurement design, route to Isolated Differential Amplifier.
Isolation-Driven Specs That Actually Matter
These specifications should be interpreted as system behaviors, not just datasheet numbers. Each item below maps a spec to failure signatures (what shows up in the lab/field) and to a verification method that can be executed during bring-up and pre-compliance testing.
Spec → Why → Failure signature → How to verify
CMTI / dv/dt Immunity
Why: Fast common-mode transitions can inject transient currents across the barrier, causing bit errors, code glitches, or resets.
Failure signature: Stable on bench, but switching events trigger sporadic codes, framing errors, or sudden offset jumps.
How to verify: Reproduce dv/dt stress (real switching or controlled injection), log data integrity + supply droop + event correlation; pass within X errors over Y minutes.
Barrier Capacitance (Cbar)
Why: Displacement current scales with Cbar × dv/dt, driving common-mode emissions and injecting noise into reference/threshold nodes.
Failure signature: EMI fails without obvious functional dropouts, or errors appear “random” and sensitive to cable/ground changes.
How to verify: Sweep edge rate and return-path options; compare emission and error-rate deltas; pass when sensitivity is within X dB / X errors.
Digital Timing (Latency / Skew / Determinism)
Why: Control loops and multi-channel alignment require predictable sample-to-data delay and bounded channel mismatch.
Failure signature: Phase mismatch, calibration drift, or alignment that breaks only after resets/resync sequences.
How to verify: Apply common stimulus to channels, measure min/max/σ of delay and skew; verify after power cycles; pass when skew < X and latency spread < Y.
Working Voltage & Lifetime
Why: Long-term field reliability depends on sustained electric-field stress and board-level creepage/clearance execution.
Failure signature: Hi-pot/leakage results vary by build, or humidity/contamination correlates with failures.
How to verify: Define stress class and build cleanliness controls; run hi-pot/leakage consistency checks; pass when leakage < X and yield > Y%.
Power & Thermal (incl. no-load loss)
Why: No-load loss and self-heating shift references and drift, affecting accuracy and long-term reliability.
Failure signature: Values drift after minutes, or temperature changes amplify offset/gain error beyond expectation.
How to verify: Measure drift vs temperature and load states; correlate with device temperature rise; pass when drift stays within X over Y°C.
ESD / Surge / System EMC Coordination
Why: Device ratings must match board-level discharge paths; isolation does not remove the need for controlled return paths.
Failure signature: One lab setup passes while another fails; small grounding changes flip results.
How to verify: Pre-scan with controlled bonding/return configurations; document the pass configuration; pass when results repeat across setups within X margin.
Synchronization & Timing: Sampling, Clocks, and Deterministic Latency
The “integrated isolated digital interface” value shows up only when synchronization is treated as an end-to-end timing contract. This section defines what can be proven deterministically (min/max bounds) versus what remains statistical (jitter/spread), and provides a short budget checklist plus a 3-step sync decision tree.
Latency budget checklist (≤5 lines)
Sync decision tree (3 steps)
Need cross-device phase alignment?
No: prioritize deterministic latency spread (min/max) and stable DATA_READY behavior.
Yes: proceed to Step 2 to choose the reference strategy.
Can the system provide a shared reference?
Yes: shared clock + explicit SYNC is the primary path for provable alignment.
No: proceed to Step 3 (alignment becomes more statistical or calibration-driven).
Accept statistical alignment?
Yes: forwarded clock or DATA_READY alignment + calibration/verification plan.
No: requirements must change or the system must add a stronger shared reference path.
What can vs can’t be guaranteed
Provable (budgetable)
Min/max latency bounds under defined operating corners, channel-to-channel skew bounds within a device family, and repeatability after reset when the sync sequence is controlled and verified.
Typical / statistical
Jitter and spread distributions, drift with temperature/supply, and cross-device phase behavior without a shared reference. These must be handled as margins, not guarantees.
EMC/EMI Reality: Common-Mode Emission, Injection, and Immunity
Isolation breaks DC conduction paths, but high-frequency displacement current can still flow through barrier coupling. EMC success depends on controlling common-mode loops, return-path partitions, and edge-rate behavior. This section uses field-style triage cards: Failure signature → Likely path → First fix.
Failure triage cards (fast debugging language)
ESD hit causes resets or brownout-like behavior
Failure signature: Single discharge triggers reset, UVLO flags, or repeated reboot loops.
Likely path: Barrier injection and return-path bounce lift the secondary reference or pull down local supply decoupling loops.
First fix: Tighten secondary supply/ground loop (short decoupling), define a hard chassis bond point, and make discharge paths intentional; pass when resets = 0 over X hits.
EFT triggers bit errors but no obvious analog faults
Failure signature: Data framing errors or CRC-like symptoms during EFT bursts; conversion value looks plausible between bursts.
Likely path: Digital threshold disturbance and barrier-coupled noise enters the receive latch window.
First fix: Reduce edge rate, harden receive-latch timing margin, and ensure return partitions prevent common-mode loop amplification.
Radiated emissions fail while functionality looks normal
Failure signature: Pre-scan shows peaks that shift with cable length/routing; data remains stable.
Likely path: Cbar displacement current excites cable/plane antennas and couples into chassis loops.
First fix: Minimize loop area, enforce domain partition, and slow the dominant edges; verify that emissions drop by X dB with controlled return paths.
Switching edges create code spikes or conversion artifacts
Failure signature: Narrow spikes or step-like offsets correlate to power-stage transitions, even when the digital interface is stable.
Likely path: Injection reaches the analog reference/input network or modulates the sampling instant via ground/reference bounce.
First fix: Strengthen reference decoupling, add input network damping, and keep sensitive analog loops compact on the high-side.
Pass/fail flips with cable routing or grounding changes
Failure signature: Same DUT behaves differently between setups; moving a ground strap changes results drastically.
Likely path: Chassis bonding and return-path topology redefine the dominant common-mode loop resonance.
First fix: Standardize a single bonding strategy and document the “known-good” configuration; iterate using one variable at a time.
Pre-scan passes, but formal EMC test fails
Failure signature: Good results in bench setup; worse in chamber or with different harness fixtures.
Likely path: Test fixture and cable/plane geometry changes the antenna and return-path behavior, not the core conversion accuracy.
First fix: Build a repeatable harness/fixture recipe and re-run with controlled bonding points; ensure margins remain within X dB.
Power and Reference Strategy Across the Barrier
Measurement quality is frequently limited by power integrity, reference placement, and startup validity, not by the ADC conversion core. The strategy below focuses on selection-level isolated supply options, a practical rule for reference domain placement, and a startup/UVLO validity policy to prevent “false data” from entering control logic.
Isolated supply choices (selection-level)
Iso DC-DC Converter
When: A defined isolated rail is needed with straightforward integration and predictable regulation.
Trade-offs: Switching ripple and layout sensitivity; verify ripple and transient response at the load.
Pass criteria: Ripple at TP1 within X mVpp and load-step droop within Y mV.
Transformer Driver (bias transformer)
When: Compact bias rails are needed and the system can manage transformer selection and rectification details.
Trade-offs: Ripple/EMI control depends strongly on transformer + rectifier + return paths.
Pass criteria: Stable bias across temperature and load; no mode-hopping under burst loads.
Bias Module (integrated)
When: Fast time-to-design and predictable isolation compliance packaging is preferred.
Trade-offs: Cost/size may be higher; limited tuning knobs for ripple and startup shaping.
Pass criteria: Repeatable startup and ripple at TP1/TP2 within X/Y limits.
Selection reminder
Rule: Choose the supply path that keeps the high-side reference and input network stable during dv/dt events.
Verify: Measure at the load (TP points), not at the source, and correlate with conversion integrity.
Reference placement (domain rule)
High-side reference (local)
Why: Shortest loop and strongest control of sampling-time ground/reference bounce under dv/dt injection.
Outcome: Reference noise and ripple are measurable and correctable within the high-side domain.
Transferred/shared reference (use with caution)
When: Cross-board consistency or multi-domain calibration requires a shared baseline.
Risk: Additional coupling paths and verification burden; validity must be proven across reset and EMC stress.
Startup / UVLO validity policy (avoid false data)
POWER_INVALID
Condition: UVLO not released or rails not within window.
Action: force DATA_INVALID and hold safe output policy.
SETTLING
Condition: rail reached nominal but reference/input network still stabilizing.
Action: wait N samples or T ms; validate against TP measurements.
DATA_VALID
Condition: rails + reference stable; data-ready behavior consistent.
Action: release data to control/estimation logic with defined margin.
Layout & Partition Rules for Isolated ADC Boards
The layout objective is to keep primary/secondary domains partitioned, control return paths, and preserve sensitive high-side analog integrity under dv/dt stress. Use the Do/Don’t rules below as a board review checklist.
Do / Don’t checklist (one line each)
Partition & Keep-out
- Do: enforce a clean primary/secondary boundary and a keep-out zone near the barrier Gap
- Do: use slots where helpful to control creepage and to discourage accidental copper bridges Slot
- Don’t: place copper pours, stitching vias, or test pads that can bridge across the barrier region Bridge
- Don’t: route any signal through the keep-out corridor unless explicitly justified and verified Keep-out
Return Paths
- Do: keep digital returns closed within the same domain and controlled to avoid large CM loops Loop
- Do: treat the isolation barrier as the only intentional cross-domain coupling path Barrier
- Don’t: allow a return path to “find” the barrier gap as a shortcut across planes No-cross
- Don’t: place stitching that unintentionally provides high-frequency coupling between domains HF
High-side Sensitive Analog
- Do: use Kelvin sense where applicable and keep the input loop compact Kelvin
- Do: place input RC and reference decoupling close to the sensitive nodes RC
- Do: reserve routing corridors for sensitive analog away from dv/dt edges Corridor
- Don’t: run sensitive inputs parallel to switching nodes or noisy digital busses for long distances Coupling
Connector & Chassis Bond Strategy
- Do: define a single intentional chassis bond point near the connector return path Bond
- Do: keep cable shields and CM return loops tight and repeatable Shield
- Don’t: create multiple uncontrolled bond points that enlarge the CM loop area Area
- Don’t: place the connector such that the return path must cross the barrier corridor Route
Verification & Production Tests (Bring-up → Compliance → Factory)
The verification objective is to prove measurement validity, noise tolerance, and isolation robustness with test paths designed into the board. The test cards below follow a fixed format: Test item → Setup → Pass criteria.
Bring-up sanity checks
Rail sanity (TP1)
Test item: Verify isolated rail stability under idle and load.
Setup: Measure VISO at TP1 with load sweep; capture ripple and load-step droop.
Pass criteria: Ripple < X mVpp and droop < Y mV; no start/stop oscillation events.
Reference sanity (TP2)
Test item: Confirm high-side reference stability and noise floor.
Setup: Measure reference node at TP2 across temperature/supply corners; log drift.
Pass criteria: Reference noise within X (band-limited) and drift within Y over Z minutes.
DATA_READY stability
Test item: Prove DRDY periodicity and repeatability after reset.
Setup: Capture DRDY period and duty; repeat power cycle N times; record min/max.
Pass criteria: DRDY jitter < X and period spread < Y; no missing pulses in N cycles.
Validity gate (TP3)
Test item: Ensure invalid data never reaches control logic during startup/UVLO.
Setup: Force rail ramp and UVLO toggles; observe VALID signal and data acceptance logs.
Pass criteria: DATA_INVALID enforced until conditions met; false-valid count = 0 over N cycles.
Noise injection & pre-compliance logic
dv/dt injection: conversion artifacts
Test item: Detect code spikes/steps correlated with dv/dt events.
Setup: Apply dv/dt edge via coupling capacitor; log samples around the event window.
Pass criteria: Artifact magnitude < X LSB or limited to Y samples; no persistent offset.
dv/dt injection: bit errors
Test item: Verify digital data integrity under common-mode disturbance.
Setup: Inject CM disturbance; monitor CRC/counters; correlate with DRDY timing.
Pass criteria: Error rate < X per 10^N samples; no burst lock-up requiring power cycle.
CM loop sensitivity (bond and shield)
Test item: Identify the dominant CM loop by controlled return/bond changes.
Setup: Sweep bond-point configuration; keep one variable at a time; record peak changes.
Pass criteria: A stable “known-good” configuration exists with margin > X dB.
EFT-like burst: signature classification
Test item: Classify failures: reset vs bit error vs conversion artifact.
Setup: Apply burst disturbance; log resets, counters, and sample anomalies separately.
Pass criteria: Reset count = 0 and bit error rate < X; artifacts within defined window.
ESD-like event: recovery behavior
Test item: Validate recovery without latch-up or persistent invalid state.
Setup: Apply repeatable event; measure time-to-valid and counter stability after each hit.
Pass criteria: Return to DATA_VALID within X ms; no cumulative drift beyond Y.
Isolation tests overview (paths and coverage)
Hi-pot path (board readiness)
Test item: Ensure the board has a clean, controlled hi-pot apply/return path.
Setup: Define HV apply node and return node; remove/disable sensitive loads if required.
Pass criteria: No flashover; leakage within X; test record includes humidity/temperature.
Leakage sanity (measurement hygiene)
Test item: Confirm leakage readings are not dominated by fixture contamination.
Setup: Repeat with known clean board/fixture; log stabilization time and conditions.
Pass criteria: Leakage repeatability within X% across N repeats under same conditions.
Partial discharge awareness (structure hotspots)
Test item: Identify structural hotspots near slots, sharp copper edges, and contamination zones.
Setup: Visual inspection + controlled stress screening; document keep-out and cleaning rules.
Pass criteria: Hotspots mitigated by geometry/cleanliness; evidence captured for review.
Factory tests (coverage and traceability)
Known-code stimulus
Test item: Validate end-to-end conversion consistency with a controlled stimulus.
Setup: Apply a known input level or pattern; capture N codes; compute mean/variance.
Pass criteria: Mean within X and sigma within Y; outliers < Z per N samples.
Data integrity monitor (CRC/counters)
Test item: Detect transport faults independent of analog stimulus accuracy.
Setup: Enable CRC/counters; run at production throughput; record error histograms.
Pass criteria: Errors = 0 in X seconds or < Y per 10^N frames (by policy).
Traceability & logging policy
Test item: Ensure each unit’s isolation/data results are linked to a unique identifier.
Setup: Bind SN to test logs; store voltage/temperature/fixture revision and timestamps.
Pass criteria: 100% units have complete logs; failed bins include reason codes and rework status.
Engineering Checklist (Design → Bring-up → Production)
This checklist summarizes the entire page into actionable review items. Each line is designed to be checkable in schematic review, layout review, firmware/FPGA implementation, and manufacturing test planning.
Schematic checklist
- Domain separation: primary vs high-side domains clearly labeled for rails, grounds, and signals.
- UVLO defaults: defined safe output policy during POWER_INVALID and SETTLING states.
- VALID gating: data release controlled by a clear validity condition (TP3 observable).
- Test points: TP1 (VISO), TP2 (reference), TP3 (valid/DRDY) included and accessible.
- Injection access: provision for CM/dv/dt injection point without rework.
- Reset/re-sync: controlled reset sequencing and repeatability expectations documented.
Layout checklist
- Keep-out: barrier corridor kept free of copper bridges, pads, and stitching vias.
- Slots/geometry: slots used where needed; sharp copper edges near barrier avoided.
- Return paths: no digital return crosses the barrier corridor; loops kept compact.
- Decoupling: rail and reference decoupling placed at the load with minimal loop area.
- High-side analog: Kelvin routing, input RC, and a dedicated analog corridor enforced.
- Connector + bond: single defined chassis bond point and shield return strategy documented.
Firmware / FPGA checklist
- DRDY policy: missing pulse detection and restart behavior defined.
- Re-sync handling: robust recovery after reset, UVLO, or noise events without manual power cycle.
- Invalid-data gating: DATA_INVALID never feeds control loops; state machine is logged.
- Error counters: CRC/counters and timeout reasons recorded with time correlation.
- Timestamping (if needed): alignment definition and measurement method documented.
Manufacturing checklist
- Isolation coverage: hi-pot/leakage screening path defined; conditions recorded.
- Known-code stimulus: controlled stimulus test with thresholds X/Y for mean/sigma.
- Data integrity: CRC/counter test at production throughput with pass rules.
- Traceability: SN binding, fixture revision tracking, and timestamps stored for all units.
- Binning: failure bins mapped to rework/repair decisions and re-test flow.
H2-11. Selection Logic: When to Choose Isolated ADC vs Alternatives
What this section decides (and what it avoids)
Decision goal: select the correct implementation class from system constraints (timing, EMC stress, isolation grade, complexity).
Scope guard: comparisons stop at isolation-driven dimensions (latency determinism, sync contract, EMI paths, compliance effort, BOM/bring-up). Deep device theory belongs to sibling pages.
5-step selection sequence (system constraints first)
-
Define the measurement contract
Input: bandwidth target, dynamic range goal, channel count, simultaneous sampling need.
Output: minimum sampling/throughput class + “must-have” channel alignment requirement. -
Define the timing contract
Input: allowed latency (L), channel-to-channel skew (S), latency jitter (J), timestamping needs.
Output: whether deterministic latency is required (Yes/No) and how it will be verified (DRDY repeatability, alignment). -
Define the isolation & safety contract
Input: insulation class (basic/reinforced), working voltage target (VIORM), lifetime/environment assumptions.
Output: required barrier grade + packaging/creepage constraints that drive PCB and compliance path. -
Define the EMC stress model
Input: dv/dt intensity, common-mode swing, cabling/chassis coupling risk, proximity to switching nodes.
Output: CMTI class and “barrier-coupling risk” level that drives edge-rate control and partition rules. -
Select the implementation class and its top-3 risks to verify
Output: best-fit class + the first three verification items (data integrity signature, DV/DT injection margin, power-up invalid-data gating).
Implementation options (trade-offs + representative part numbers)
Option A · Monolithic Isolated ADC
Best when: sync/latency contract is strict, EMC stress is high, and integration reduces compliance/bring-up complexity.
What is gained: integrated barrier + isolated interface; fewer “unknown couplings” across discrete parts; cleaner test story.
Representative parts:
AMC131M01
AMC131M02
AMC131M03
AMC131M03-Q1
ADE7912
ADE7913
Option B · Isolated ΔΣ Modulator (bitstream)
Best when: system can accept digital filtering latency and wants robust high-side sensing with simple isolated bitstream links.
What is gained: strong isolation + simple output; flexible digital filtering outside the device.
Representative parts:
AMC1306M05
AMC1304L05
AD7403
Option C · Isolated Differential Amplifier + Local ADC
Best when: analog conditioning on the high side is the hard problem; the ADC is preferred to remain local for reuse or performance tuning.
What is gained: strong CMTI analog link; ADC choice stays flexible (resolution/speed/interface).
Representative parts (isolated amp):
AMC1301
AMC1302
AMC1311
ISO224
AMC3301
Option D · Discrete ADC + Digital Isolator + Isolated Power
Best when: the project must reuse a known ADC, or needs maximum flexibility, and can afford higher bring-up + compliance effort.
What is gained: best-in-class ADC freedom; replaceable isolator; scalable architectures.
Representative parts (building blocks):
ADS131M04
ADS131M06
ISO7741
ADuM141E
Si86xx
SN6505A
SN6505B
NXE1S0505MC
DCP020515D
Red flags (when an Isolated ADC is NOT the best answer)
- Deterministic timing is not required and the signal bandwidth is low: an isolated ΔΣ modulator may be a better fit.
- Analog front-end correctness dominates (Kelvin sense, gain/offset drift, reference strategy): an isolated amplifier + local ADC can reduce risk.
- Existing certified ADC platform must be reused: discrete isolation is often the lowest program risk despite higher complexity.
- EMI failures are driven by layout/return paths rather than the converter choice: fix partitions and coupling first; then re-evaluate integration.
- Power-up invalid data cannot be tolerated without strict gating: choose architectures with explicit DRDY/valid handling and a clear startup contract.
Diagram: Decision tree — requirements → best-fit device class (logic-first, minimal text)
H2-12. Applications & IC Selection
Application bundles are templates (goal → architecture → critical specs → validation focus), plus a device-class selection checklist with representative part numbers.
Application Bundle A · Motor / Inverter Phase Current & Voltage
Goal
Simultaneous phase-domain sensing under high dv/dt and large common-mode swing with reliable sync.
Architecture
Shunt / divider → front-end RC + Kelvin → Isolated ADC → SPI/DRDY → MCU/FPGA → isolated power rail.
Critical specs
CMTI class · VIORM target · latency/skew determinism · barrier capacitance (Cbar).
Validation focus
dv/dt injection margin · data-ready repeatability · invalid-data gating at startup · EMI signature vs cable/chassis.
Representative parts (examples)
Isolated ADC:
AMC131M03 AMC131M03-Q1
ADE7913
Alternatives:
AMC1306M05 AD7403
AMC1311
Isolated power (selection-level):
SN6505B NXE1S0505MC DCP020515D
Application Bundle B · HV Bus / Battery Sensing (Floating High-Side)
Goal
High-side voltage/current measurement that stays valid across isolation boundaries and long lifetime constraints.
Architecture
Divider / shunt → input RC + protection → Isolated ADC → SPI/DRDY → controller domain logging.
Critical specs
VIORM & lifetime model · insulation class · input range matching (shunt/divider) · drift contributors (ref + gain).
Validation focus
reference-domain correctness · long-term drift plan · power-up sequencing and “valid window” definition.
Representative parts (examples)
Isolated ADC:
AMC131M01 AMC131M02
ADE7912
Discrete path (if reuse ADC is required):
ADS131M04 + ISO7741 or ADuM141E
Application Bundle C · Floating DAQ Module in Noisy Cabinets
Goal
Stable data integrity in strong common-mode disturbance (EFT/ESD, long I/O, chassis coupling).
Architecture
Sensor → Isolated ADC (or discrete chain) → controller → robust logging; isolation partitions enforced by layout.
Critical specs
barrier coupling (Cbar) · CMTI · interface robustness (CRC/DRDY) · power noise & no-load loss.
Validation focus
pre-scan EFT/ESD signatures · bit errors vs conversion artifacts separation · reset/UVLO policy.
Representative parts (examples)
Isolated ADC:
AMC131M01 ADE7912
Digital isolator (discrete chain):
ISO7741 ADuM141E Si86xx
Isolated DC/DC module (fast-BOM option):
NXE1S0505MC R05P05S DCP020515D
Application Bundle D · Multi-Channel Sync Sampling “Island”
Goal
Simultaneous multi-channel sampling with predictable data-ready behavior and consistent phase relationships.
Architecture
multi-sensor front-end → multi-channel isolated ADC → DRDY-aligned acquisition → timestamped samples in MCU/FPGA.
Critical specs
channel-to-channel skew · DRDY determinism · interface integrity (CRC) · thermal drift vs sampling alignment.
Validation focus
skew characterization across temperature · resync handling · invalid-data gating on transient events.
Representative parts (examples)
Multi-channel isolated ADC: AMC131M03 AMC131M03-Q1 ADE7913
IC Selection Checklist (device-class level, with example part numbers)
1) Isolation rating & lifetime contract
- Choose insulation class (basic/reinforced) and define VIORM target based on lifetime assumptions.
- Confirm package/creepage constraints match PCB keep-out and manufacturing capability.
- Example parts: AMC131M01 AMC131M03 ADE7912
2) CMTI / dv/dt immunity contract
- Map switching dv/dt and common-mode swing to required CMTI class; treat it as a data-integrity requirement.
- Plan a dv/dt injection test that can reproduce worst-case signatures early.
- Example parts: AMC1311 AMC1306M05 ISO7741
3) Barrier capacitance (Cbar) & common-mode emission risk
- Lower barrier coupling generally reduces injected common-mode currents and radiated signatures.
- Keep coupling loops small: connector strategy, chassis bond strategy, and return-path partitions must match device choice.
- Example blocks: AMC131M0x class or discrete isolators ADuM141E/ISO7741 depending on architecture.
4) Timing determinism (latency / skew / DRDY)
- Prefer explicit data-ready / sync mechanisms when deterministic sampling alignment is required.
- Verify worst-case skew across temperature, supply variation, and EMC stress events.
- Example parts: AMC131M03 AMC131M03-Q1 ADE7913
5) Power & thermal budget across the barrier
- Budget both sides: high-side rail noise/no-load loss can dominate measurement integrity.
- Select isolated power strategy at the system level (module vs transformer driver vs integrated isoPower).
- Example parts: SN6505A/SN6505B, NXE1S0505MC, DCP020515D
6) Interface integration needs (needs-level, not protocol deep dive)
- Define whether the controller needs SPI + CRC, DRDY behavior, and resync semantics.
- If an existing ADC must be reused, shift the risk to isolator selection and factory test coverage.
- Example blocks: ADS131M04 + ISO7741 or ADuM141E
Diagram: Application bundle template — sensing front-end + isolated ADC + controller + isolated power (4 bundles, one reusable visual language)
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H2-13. FAQs (10–12) — Field Debug & Acceptance Criteria
Format & data placeholders
Each question uses a fixed 4-line structure for fast field closure: Likely cause → Quick check → Fix → Pass criteria.
Scope guard: only isolated-ADC system topics (CMTI/dv/dt, barrier coupling, timing/sync, power/reference, interface robustness, hi-pot readiness, thermal drift, lab setup consistency).
Bench is stable, but inverter dv/dt causes random codes — first suspect CMTI limit or return-path injection?
Likely cause: dv/dt displacement current across the barrier (Cbar) injects into the secondary reference/IO, or CMTI headroom is exceeded during switching edges.
Quick check: correlate error bursts with switching edges; reduce dv/dt (gate resistor / softer edges) and see whether errors drop without changing sampling settings.
Fix: shrink common-mode loops (partition + return paths), add edge-rate control (series R on fast lines), and ensure high-side reference/decoupling stays local and tight.
Pass criteria: code error rate ≤ X per Y minutes under worst-case dv/dt with N switching transitions (no clustered bursts at edges).
EMC lab fails radiated even with isolation — first check barrier capacitance path or cable/chassis bonding?
Likely cause: barrier capacitive coupling drives common-mode current onto cables/planes that behave as antennas; chassis bonding/termination turns a small CM current into a large radiated signature.
Quick check: repeat the scan with controlled cable routing/length and alternate shield termination; identify whether peaks move with cable/chassis changes.
Fix: minimize CM loop area (connector placement + return partitions), tune shield bonding strategy, and only add safety Y-cap if leakage budget allows.
Pass criteria: radiated peak margin ≥ X dB over Y scans across N cable/termination configurations.
Multi-channel phase mismatch shows up — sync method issue or channel skew spec misunderstood?
Likely cause: the chosen sync method cannot guarantee alignment at the required level, or skew was read as “typical” rather than worst-case for the actual mode/temperature.
Quick check: capture N repeated records using a common stimulus and quantify skew distribution; confirm the datasheet’s skew definition (same device vs multi-device, mode-specific).
Fix: switch to a synchronization approach with a provable contract (shared/forwarded clock + DRDY alignment), and add resync/calibration handling in the receiver domain.
Pass criteria: channel skew ≤ X (time/deg) over Y temperature points with N repeated captures (distribution stays bounded).
Data-ready is periodic but values glitch during switching — power ripple coupling or digital threshold upset?
Likely cause: high-side supply/reference ripple modulates conversion results, or barrier-injected noise upsets digital thresholds causing sporadic bit-level corruption without breaking DRDY timing.
Quick check: time-align glitches with supply/reference ripple and switching edges; slow IO edges (series R / drive strength) and observe whether glitches track the change.
Fix: tighten high-side decoupling/reference placement, reduce coupling loops, and harden the digital interface with edge control and robust sampling margins.
Pass criteria: glitch count ≤ X over Y minutes at worst-case switching with N load/switching steps (no clustered events).
After reset, readings look valid but are offset — reference not settled or invalid-data gating missing?
Likely cause: reference/analog front-end has not settled, or the system lacks an explicit “invalid data window” after reset/UVLO before accepting samples.
Quick check: extend post-reset wait and gate output until DRDY is stable for N consecutive periods; compare offset with and without gating.
Fix: define a startup contract (settling time + DRDY stability + valid flag) and enforce it in firmware/FPGA with clear logging of invalid intervals.
Pass criteria: post-reset offset ≤ X after Y seconds settling across N power/reset cycles (no acceptance before “valid”).
EFT triggers sporadic SPI framing errors — edge rate too fast or isolation interface robustness?
Likely cause: fast edges plus poor return partitions convert EFT bursts into threshold/clocking disturbances, or the receiver sampling margin collapses during common-mode transients.
Quick check: add series resistors and reduce SPI speed/edge rate; check whether framing errors occur only during EFT hits and disappear with gentler edges.
Fix: harden interface margins (edge control, sampling phase, filtering), enforce strict primary/secondary return separation, and validate under pre-scan EFT with realistic cabling.
Pass criteria: SPI framing errors = 0 (or ≤ X) over Y EFT bursts with N hits at the intended cable/ground setup.
Two boards pass, third fails hi-pot — layout creepage margin or contamination/flux residue?
Likely cause: marginal creepage/clearance at a specific spot, or process contamination (flux residue, moisture) lowering surface resistance and triggering leakage/breakdown.
Quick check: inspect and clean suspect areas, bake/dry if needed, then retest; compare leakage localization (which nodes, which corner) across boards.
Fix: increase keep-out/slots where margin is thin, add process controls (wash/bake/coating), and ensure test pads/fixtures do not create unintended creepage shortcuts.
Pass criteria: hi-pot leakage ≤ X at test voltage for Y seconds across N samples (no breakdown/flashover events).
Thermal drift is larger than expected — self-heating on high-side or reference tempco?
Likely cause: high-side self-heating shifts gain/offset, or reference/tempco dominates because the reference is placed near heat sources or lacks a stable thermal path.
Quick check: log drift vs board temperature at defined test points; apply a power step and compare drift time constant to thermal settling behavior.
Fix: reduce dissipation, improve heat spreading/airflow, isolate the reference thermally from hot components, and re-validate drift after steady-state.
Pass criteria: drift ≤ X over Y minutes after steady-state at N ambient points (monotonic and bounded).
Factory test passes, field fails — missing dv/dt stress in validation plan?
Likely cause: validation did not reproduce field dv/dt/common-mode stress, so coupling paths (barrier → cable/chassis) were never exercised at realistic severity.
Quick check: recreate the closest field stress (dv/dt edges, cabling, chassis bonds) and compare failure signatures to field logs.
Fix: add a dv/dt injection / EMI pre-scan gate with data-integrity monitoring (CRC/glitch counters) and define acceptance thresholds before release.
Pass criteria: under worst-case stress, error metrics ≤ X over Y minutes with N events (signatures match “pass” profile).
Adding a Y-cap fixed EMI but leakage limit was exceeded — what’s the next knob?
Likely cause: the Y-cap provides an effective CM return path for emissions, but system leakage constraints (medical/portable/standards) cap allowable capacitance.
Quick check: quantify EMI improvement vs leakage increase with the same setup; test smaller values or alternate placement to see sensitivity.
Fix: prioritize geometry and return-path control (loop area, shield termination, chassis bond point) and edge-rate control; only use minimal Y-cap where leakage budget permits.
Pass criteria: EMI margin ≥ X dB AND leakage ≤ Y (mA/µA) across N operating modes (no regressions).
Long cable to the controller worsens errors — receiver domain grounding or shield termination strategy?
Likely cause: cable/chassis coupling increases CM current and shifts receiver reference during transients; shield termination creates an unintended antenna or return loop.
Quick check: compare short vs long cable using identical routing; switch shield termination (single-end vs controlled chassis bond) and observe whether errors track the change.
Fix: enforce a consistent receiver-domain grounding strategy, keep CM loops tight, and define a repeatable shield termination rule tied to the enclosure architecture.
Pass criteria: error rate ≤ X over Y minutes with cable length N (m) under the intended chassis/ground configuration.
Different lab results for the same DUT — test setup return path or measurement bandwidth mismatch?
Likely cause: differences in return path, fixture/cabling, probe grounding, or measurement bandwidth create different coupling conditions and different “observed” failure signatures.
Quick check: standardize cable routing, shield bonds, probe bandwidth, and pass/fail metric definition; rerun N times to check repeatability before comparing labs.
Fix: lock a golden setup (fixtures, grounding, bandwidth, statistics window) and document it as part of the compliance evidence package.
Pass criteria: inter-lab delta ≤ X for the same metric over Y runs with N repeated measurements (variance bounded).
