Isolated Gate Driver (IGBT/SiC/GaN): Miller Clamp & DESAT
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H2-1. Scope Guard & System Map
This page treats an isolated gate driver as a complete power-stage control block: timing + drive + protection + diagnostics + validation. Content stays inside the gate-driver boundary to avoid cross-page overlap.
- System role: where isolation sits in the control loop (PWM → gate → fault → controller).
- Key specs that map to failures: CMTI/dv/dt immunity, delay/skew, peak source/sink, UVLO behavior, fault signaling.
- Protection mechanisms: Miller clamp strategy, DESAT / short-circuit detection, soft turn-off, safe-state defaults.
- Gate network & layout: Rg_on/Rg_off shaping, Kelvin source/emitter, loop minimization, protection-pin routing.
- Validation & production gates: double-pulse, fault injection, dv/dt stress, golden waveforms, pass criteria placeholders.
- Selection & pairings: decision inputs for IGBT/SiC/GaN and half-bridge use, without duplicating power-topology pages.
- Isolated power topologies (flyback/push-pull/modules) — see Isolated Power (DC-DC & Bias).
Driver-side minimum kept here: supply pins, UVLO thresholds, decoupling and return paths. - Safety & certification deep dive (VIORM/creepage/PD/certificates) — see Safety & Compliance.
Driver-side minimum kept here: which rating names to request and how they constrain layout/spacing. - Isolated modulation / isolated ADC chains — see Isolated Modulation & ADC.
Driver-side minimum kept here: fault/reporting coordination only.
- Start with failure modes: shoot-through, false turn-on, destructive turn-off, nuisance DESAT trips.
- Then map knobs to risks: clamp / Rg shaping / negative bias / DESAT blanking / soft turn-off strength.
- Freeze via validation: double-pulse → fault injection → dv/dt stress → EMI pre-scan knobs → production gates.
- Timing & shoot-through: Is skew/dead-time budgeted with real propagation delays and temperature drift?
- dv/dt & false turn-on: Is Miller injection controlled by clamp placement, Kelvin returns, and gate-off strength?
- Protection & recovery: Is DESAT/SC protection fast enough without nuisance trips, and is soft turn-off tuned to limit overvoltage?
- Bring-up certainty: Are there defined waveforms, logs, and pass criteria to lock settings before production?
H2-2. What Is an Isolated Gate Driver
An isolated gate driver is a combined block that transfers control across an isolation barrier and delivers high-current gate drive while enforcing fast protection and diagnosable safe states in high dv/dt power environments.
- Isolation: control signals cross a barrier that must remain stable under large common-mode transients.
- Gate drive output stage: peak source/sink current shapes Vgs, controls switching speed, and limits ringing through the external gate network.
- Protection & diagnostics: detects dangerous events (DESAT / short-circuit / UVLO) and triggers controlled turn-off with a reportable fault state.
Practical meaning: the driver is not only a “signal isolator” — it is the component that converts PWM intent into a verified switching action while bounding failure energy.
- High-side and half-bridge motion: switch nodes move hundreds of volts; isolation keeps the controller domain stable while the power domain slews.
- Ground bounce and fast current loops: local return paths shift during switching; isolation prevents controller references from being dragged by power-loop noise.
- Fault energy is fast and large: short-circuit events require microsecond-class response and predictable turn-off behavior to prevent destructive overvoltage.
- Integrated isolated gate driver (single package): clean timing boundary and built-in fault paths; simpler to validate end-to-end.
- Digital isolator + non-isolated driver (two-chip chain): flexible, but protection latency, safe-state defaults, and fault reporting can fragment across chips if not designed as one loop.
- Driver with integrated isolated bias (system-level module): reduces supply-interface mistakes and UVLO chatter; selection must still verify dv/dt behavior and fault turn-off shape.
- False turn-on: dv/dt + Miller injection raises Vgs during off-state → unintended conduction.
- Shoot-through: half-bridge timing mismatch or parasitic coupling turns both devices on.
- Destructive turn-off: short-circuit or overcurrent forces abrupt current interruption → overvoltage / ringing.
- Nuisance protection trips: DESAT triggers from coupling, blanking mis-tune, or routing errors.
H2-3. Architecture & Timing Path
Timing is a system chain, not a single datasheet number: input → isolation → logic → output stage → gate network. Dead-time and shoot-through risk are determined by worst-case delay and skew across this full path.
- PWM / IN: switching intent; defines on/off edges that must remain deterministic under dv/dt.
- EN: global enable; should force a defined safe state (off) independent of PWM.
- RST: clears latched faults and returns logic to a known state; must not cause spurious gate edges.
- DESAT / SC sense: fault detection input; must be routed and filtered to avoid dv/dt pickup.
- FAULT / READY: diagnostics outputs; must be observable during bring-up and production tests.
- Input conditioning: threshold & glitch handling → affects false triggers and edge repeatability.
- Isolation transfer: encode/decode delay → sets baseline propagation delay and contributes to channel skew.
- Logic arbitration: fault priority & interlock rules → decides whether PWM can be overridden instantly.
- Output stage: source/sink strength and split paths → controls Vgs slew and off-strength vs Miller injection.
- Gate network: Rg_on/Rg_off + parasitics → determines the real Vgs waveform and effective switching time.
- Dead-time margin must cover worst-case skew + drift + measurement uncertainty.
- Skew sources include channel matching, temperature and VDD variation, output-stage asymmetry, and layout-induced return shifts.
- Pass criteria placeholder: dead-time ≥ X ns, where X is derived from worst-case HS vs LS timing spread (max/min), plus drift and uncertainty.
- UVLO on secondary side (VDD2): must force gate to a defined off state with predictable pull-down strength.
- Fault override priority: DESAT/SC should preempt PWM and enforce a controlled turn-off path (often soft turn-off).
- Half-bridge coordination: a fault on one side must not leave the opposite side in an unsafe state; interlock policy must be explicit.
Scope boundary: this section treats timing determinism in nanosecond-class gate control. Ultra-low-jitter clock isolation design belongs to Low-Jitter Clock Isolator.
- Peak current only: choosing by Ipk alone ignores fault priority, UVLO behavior, and the off-path strength needed to suppress Miller turn-on.
- Typical delay only: using typical tPD while ignoring max/min spread leads to insufficient dead-time and latent shoot-through risk.
- UVLO assumed “rare”: supply ripple or fast load steps can trigger UVLO chatter, creating repeated turn-off/on behavior.
H2-4. Key Specs That Actually Matter (IGBT vs SiC vs GaN)
Specs matter only when they map to failure modes. Each selection item below ties spec → risk → fast validation to prevent false turn-on, shoot-through, nuisance trips, and destructive turn-off.
- Spec: CMTI class ≥ X kV/µs; barrier capacitance low enough to limit common-mode injection.
- Risk if weak: dv/dt pickup raises Vgs or corrupts logic → false turn-on or fault mis-detect.
- Fast validation: dv/dt stress test + log false-trigger count over Y minutes (placeholder).
- Pass criteria: false turn-on events ≤ N across defined dv/dt profile (placeholder).
- Spec: peak source/sink ≥ X A; output impedance and split pull-up/pull-down behavior.
- Risk if weak: insufficient sink strength → Miller turn-on during off; overly aggressive drive → overshoot/EMI.
- Fast validation: double-pulse waveforms (Vds/Vgs/Id) + overshoot and ringing tracking.
- Pass criteria: overshoot ≤ X% of bus, ringing within Y cycles (placeholder).
- Spec: propagation delay (max/min) + channel skew/matching ≤ Y ns.
- Risk if weak: real skew erodes dead-time → intermittent shoot-through under temp/VDD drift.
- Fast validation: measure HS vs LS delay spread across temp and supply corners.
- Pass criteria: worst-case skew + drift ≤ dead-time margin − X ns (placeholder).
- Spec: DESAT blanking X–Y ns; threshold; response time; soft turn-off capability.
- Risk if weak: slow/weak response → destructive turn-off; too sensitive → nuisance trips.
- Fast validation: fault injection (short-circuit) + verify turn-off waveform shape and clamp behavior.
- Pass criteria: no destructive overvoltage; nuisance trip rate ≤ N/1000 operations (placeholder).
- Spec: UVLO threshold + hysteresis; quiescent current; shutdown behavior.
- Risk if weak: UVLO chatter causes repeated turn-off/on, corrupts diagnostics, and stresses the switch.
- Fast validation: sweep VDD2 ripple and load steps; confirm clean state transitions and stable fault outputs.
- Pass criteria: no unintended toggles; fault outputs remain valid over Y seconds (placeholder).
Scope boundary: isolated DC-DC topology selection is covered in Isolated Power (DC-DC & Bias). This page keeps only driver-side supply constraints and UVLO behavior.
- Spec: operating temperature range; driver dissipation under switching frequency; aging-sensitive thresholds.
- Risk if weak: reduced drive strength or shifted thresholds at high temperature increases false turn-on and nuisance trips.
- Fast validation: hot/cold double-pulse plus fault injection repeatability.
- Pass criteria: timing and protection margins preserved at temperature corners (placeholder).
H2-5. Miller Clamp, dv/dt Injection, and False Turn-On Control
False turn-on is usually a current-path problem: dv/dt drives Miller current through Cgd, lifting Vgs during the off-state. The fix is to harden the off-path, clamp gate-to-source at the right reference, and verify with Vgs/Vds correlation.
- Off-state Vgs “bump” aligns with switch-node dv/dt events.
- Half-bridge shoot-through risk increases under high bus voltage, high temperature, or faster edges.
- EMI gets worse after “speed-up” changes, even if switching loss improves.
- Intermittent faults appear only on one leg (HS/LS) or one PCB revision (layout sensitivity).
- Miller coupling: dv/dt across Cgd injects current into the gate node.
- Off-path impedance: injected current creates Vgs across the turn-off path and gate-loop parasitics.
- Trigger condition: if Vgs rises above the effective threshold region, unintended conduction starts.
- Reference stability: a noisy source/emitter reference makes the effective Vgs larger than expected.
- 1) Miller clamp: provides a low-impedance gate-to-source short during off-state.
Key points: clamp enable timing, clamp strength, clamp return reference (Kelvin source/emitter). - 2) Stronger turn-off path: split Rg_on/Rg_off and strengthen sink behavior.
Key points: dedicated Rg_off, diode network, minimize turn-off loop area. - 3) Kelvin source/emitter: separates power loop from gate reference to stabilize the off-state Vgs.
- 4) Negative gate bias (optional): -2 V / -5 V increases off margin but raises layout/ESD/ringing constraints.
- 5) Gate-source RC / ferrite (cautious): can reduce spikes but may introduce ringing or increase loss.
- 6) Edge shaping as a last resort: slow down the transition only after off-path is hardened and verified.
- Rg_off: increase off strength to suppress Vgs bumps (placeholder: Rg_off = X Ω).
- Clamp effectiveness: verify clamp actually conducts and returns to Kelvin reference (placeholder: I_clamp ≥ X A).
- Vneg: apply negative bias only if Vgs still rises under worst dv/dt (placeholder: Vneg = -X V).
- Dead-time: adjust last; it is not the root cure for Miller injection (placeholder: DT ≥ X ns).
- Measure Vgs at Kelvin point while capturing switch-node dv/dt (Vds/Vce).
- Correlate events: off-state Vgs bumps must track dv/dt timing if Miller injection is dominant.
- Corner scan: repeat at higher bus voltage and temperature where false turn-on risk increases.
- Pass criteria (placeholders): Vgs(off) peak ≤ X V; false turn-on events ≤ N per Y minutes.
H2-6. DESAT / Short-Circuit Protection and Soft Turn-Off Tuning
Short-circuit protection is a closed loop: detect → decide → act → report → recover. The goal is fast detection with controlled turn-off to prevent overvoltage and destructive stress without nuisance trips.
- Detect: DESAT/SC sense network reports abnormal VDS/VCE behavior.
- Decide: comparator threshold + blanking window distinguishes switching transient vs real fault.
- Act: soft turn-off path limits di/dt and dv/dt during forced shutdown.
- Report: FAULT output indicates event and may latch until reset.
- Recover: reset policy (latched vs auto) is defined at driver logic level; system retry logic is not expanded here.
- Hard short: fastest current rise; requires minimal detection latency and robust forced turn-off.
- Soft short / overload: may allow a short window; blanking and threshold must avoid false positives.
- IGBT vs SiC: tuning focus differs; the driver must balance fast shutdown with overvoltage control.
- Blanking time: allows normal turn-on transients and diode recovery to settle (placeholder: X–Y ns/µs).
- Threshold level: defines when “desaturation” is declared; too low causes nuisance trips.
- RC filtering: trades false pickup immunity vs response delay; layout dominates for high-impedance nodes.
- Pass criteria placeholder: trip latency ≤ X, with nuisance trip rate ≤ N/1000 operations.
- Why: a forced hard pull-down can create excessive overvoltage and ringing; soft turn-off limits stress.
- How: controlled sink strength or staged discharge pulls Vgs down with a bounded slope.
- Knobs (placeholders): soft-off sink strength = X; soft-off duration = Y; clamp behavior on fault = on/off.
- Waveform checks: VDS/VCE overshoot ≤ X% of bus; VGS returns cleanly without a second bump; FAULT timing is deterministic.
Pass criteria: no trips during normal switching across Y minutes (placeholder).
Fix: shorten loop, reference to Kelvin, add minimal RC at the sense node if allowed.
Fix: adjust RC, clamp behavior, and gate-off strength to reduce ringing.
H2-7. Half-Bridge / High-Side Driving Essentials (Interlock, Dead-Time, DESAT Coordination)
Half-bridge gate driving fails when interlock, dead-time, skew, UVLO safety state, and fault linkage are not defined as a single policy. This section turns those choices into measurable budgets and deterministic behaviors.
- Who inserts dead-time? MCU/FPGA, driver, or both (avoid double-insertion).
- Is FAULT latched or auto-retry? Define reset conditions and minimum off-time.
- What is the UVLO safe state? Gate default + clamp behavior during undervoltage.
- How is the two-channel skew budget written? Include delay spread, drift, and margin.
- Does DESAT link both sides? Fault linkage mode and linkage latency must be explicit.
- Decision: external insertion vs internal interlock/dead-time vs combined.
- Why it matters: too little dead-time risks shoot-through; too much increases loss and EMI side-effects.
- Knobs (placeholders): DT = X ns; rise/fall asymmetry allowed = Y.
- Quick validation: capture HS/LS Vgs (Kelvin) and SW node together; confirm a no-overlap window.
- Pass criteria (placeholder): overlap events ≤ N per 10^6 cycles.
- Decision: FAULT latch until reset, or controlled auto-retry with enforced off-time.
- Why it matters: auto-retry can “re-hit” a hard short; latch requires a deterministic reset sequence.
- Knobs (placeholders): min-off time = X µs; reset gate = RST/EN.
- Quick validation: inject a single-side fault and confirm output shutoff + FAULT timing repeatability.
- Pass criteria (placeholder): fault response latency ≤ X; behavior matches policy 100%.
- Decision: output forced-low, clamp enabled, and whether the opposite side is also forced-off.
- Why it matters: UVLO chatter creates repeated switching and can trigger nuisance protection or overvoltage.
- Knobs (placeholders): UVLO threshold/hysteresis = X/Y; output default = OFF.
- Quick validation: sweep VDD2 with ripple/step load; verify no unintended gate pulses.
- Pass criteria (placeholder): unintended pulses ≤ N per test window Y.
- Decision: write a skew budget that includes delay spread + drift + margin.
- Why it matters: worst-case skew consumes dead-time and is the hidden root of shoot-through risk.
- Budget template (placeholder): skew_wc = (max tPD_HS − min tPD_LS) + drift + margin.
- Quick validation: measure tPD distribution across temperature and VDD corners.
- Pass criteria (placeholder): skew_wc ≤ (DT − X ns).
- Decision: DESAT on one side triggers off-both or isolated behavior.
- Why it matters: unlinked faults can leave the other switch active during an abnormal state; linked faults must avoid harmful transients.
- Knobs (placeholders): linkage mode = OR-link / isolated; linkage latency ≤ X ns.
- Quick validation: force DESAT on one leg; verify opposite leg action matches the chosen mode.
- Pass criteria (placeholder): linkage behavior deterministic over N trials; no policy race conditions observed.
H2-8. Isolated Bias and Supply Interface (What This Page Covers, What It Doesn’t)
This page covers bias from the driver viewpoint: VDD2 operating range, peak/average demand, UVLO behavior, and how decoupling and return paths directly shape gate waveforms. Isolated DC-DC topology design is out of scope and should be handled in the Isolated Power page.
- VDD2 needs: operating range, peak/average demand, and start-up sequencing constraints.
- Dual rails / negative bias: +V / -V interface constraints and safe-state expectations.
- Decoupling & return: placement, loop area, and reference separation that prevent false triggering.
- Isolated DC-DC topology: flyback/push-pull/modules and transformer design.
- System safety standards: VIORM, creepage/clearance, certification details.
- Near-driver HF decoupling (C_HF): place directly across VDD2–GND2 at the driver pins (placeholder distance: < X mm).
- Local bulk (C_BULK): add nearby bulk energy to handle bursts (placeholder: X µF), still within a tight return loop.
- Return discipline: keep the driver’s gate reference tied to Kelvin S/E and separate it from the noisy power return.
- Negative rail (optional): if Vneg is used, provide its own local decoupling and avoid sharing long return paths.
- Noise-to-gate coupling: treat VDD2 ripple and ground bounce as direct contributors to Vgs anomalies and nuisance trips.
Quick check: capture VDD2 and Vgs at the same trigger.
Fix: tighten C_HF loop and clean return reference.
Pass criteria (placeholder): VDD2 ripple ≤ X mVpp under worst switching.
Quick check: scan VDD2 with step load; count UVLO events.
Fix: increase hysteresis or improve local energy/return path.
Pass criteria (placeholder): UVLO events ≤ N per Y steps.
Quick check: measure fast droop at driver pins (not at the supply source).
Fix: move C_HF tighter; shorten return and isolate gate reference.
- VDD2 stability: ripple ≤ X mVpp and no UVLO chatter across operating corners.
- Gate integrity: no unintended pulses during supply steps; Vgs(off) remains stable under worst dv/dt.
- Determinism: FAULT/UVLO behavior matches the defined safe-state policy 100%.
H2-9. Layout, Partition, and EMC Reality (Driver-Centric)
Isolation does not remove common-mode coupling. Layout decides whether gate loops stay quiet, protection signals stay trustworthy, and dv/dt events remain controllable. This section is limited to driver-centric layout rules and EMC realities.
- Primary/Secondary partition: keep a clear isolation gap and force all returns to stay on their own side.
- Gate loop: route a compact loop (OUT → Rg → Gate → Kelvin S/E → driver return) with minimal area.
- Kelvin reference: reference gate control and protection to Kelvin S/E, not to noisy power return.
- DESAT sense: keep high-impedance nodes short; route away from SW dv/dt hotspots.
- Decoupling: place C_HF at VDD2/GND2 pins; keep its loop tight and local.
- No cross-gap return: do not create any return path crossing the isolation slot.
- No long gate loops: avoid large loop areas that turn into antennas and inject noise into Vgs.
- No DESAT near SW node: avoid routing DESAT/FAULT along the switching node or parallel to it.
- No shared noisy return: do not share long power return paths as the reference for sensitive logic/protection.
- No “remote decoupling”: caps far from driver pins behave ineffective for fast transients.
- Barrier capacitance: dv/dt couples through the isolation barrier and can shift local references.
- Y-cap: changes the return path of common-mode currents and can improve or worsen EMI depending on placement.
- Driver impact: false turn-on window, nuisance fault probability, and waveform repeatability.
- Isolation gap is physically clear; no copper/return intentionally or unintentionally bridges the slot.
- Gate loop area is minimized and stays within the secondary (driver) domain.
- Kelvin S/E is routed as a dedicated reference back to the driver (not merged with high-current return).
- DESAT high-impedance node is short, shielded by spacing, and far from SW dv/dt hotspots.
- DESAT/FAULT routing has a defined quiet reference return (Kelvin or dedicated quiet return).
- C_HF is placed at VDD2/GND2 pins; its return loop is tight and local.
- Signal/return are routed as pairs where applicable to prevent antenna-like structures.
- Sensitive lines keep spacing ≥ X mm (placeholder) from the switching node copper.
- Probe/test points exist at Kelvin reference for trustworthy Vgs and protection debugging.
- Any guard/shield does not introduce a cross-gap return path.
H2-10. Bring-Up & Validation (Double-Pulse, Fault Injection, dv/dt, EMI)
Validation converts “it switches” into “it is acceptable and repeatable.” Each test below uses the same engineering format: Purpose / Setup / What to log / Pass criteria (X/Y/N).
- 1 Double-pulse baseline
- 2 Tune gate network
- 3 Short-circuit / fault injection
- 4 dv/dt stress (false turn-on & nuisance faults)
- 5 EMI pre-scan (trend + knobs)
- 6 Freeze settings (configuration snapshot)
- Purpose: establish switching baseline (overshoot, ringing, loss trend) and confirm controllability.
- Setup: defined Vbus/Id corner (placeholders); probe Vgs at Kelvin reference; keep measurement loops minimal.
- What to log: Vgs, Vds/Vce, Id, dv/dt, di/dt, ringing frequency, overshoot percentage, repeatability notes.
- Pass criteria (placeholders): overshoot ≤ X%; Vgs(off) bump ≤ Y V; ringing decays within N cycles.
- Purpose: move waveforms into a stable window before stressing protection paths.
- Setup: adjust one knob at a time: Rg_on/Rg_off, clamp enable, Vneg (optional), dead-time (placeholders).
- What to log: before/after waveform snapshots + extracted values (overshoot, ringing, Vgs bump, dv/dt).
- Pass criteria (placeholders): key metrics stay inside target windows across X repeats and temperature delta Y.
- Purpose: verify DESAT blanking, trip latency, and soft turn-off control under fault conditions.
- Setup: define fault type (hard/soft) and trigger conditions; keep sense routing and references identical to final layout.
- What to log: DESAT threshold crossing time, FAULT timing, Vds/Vce overshoot during turn-off, Vgs fall slope, repetition consistency.
- Pass criteria (placeholders): trip latency ≤ X; turn-off overshoot ≤ Y; nuisance trips ≤ N per 10^k cycles.
- Purpose: quantify false turn-on probability and nuisance fault rate under elevated dv/dt conditions.
- Setup: raise dv/dt via controlled knob changes (Rg, Vbus, load corner); keep dead-time and policy fixed.
- What to log: Vgs(off) bump distribution, false turn-on count, FAULT count, correlation to dv/dt and temperature.
- Pass criteria (placeholders): false turn-on ≤ N per 10^6 cycles; Vgs(off) peak ≤ X V.
- Purpose: verify that driver knobs move EMI in a predictable direction before formal compliance testing.
- Setup: repeatable pre-scan setup (near-field probe / cable pose / supply); do not treat as certification-grade.
- What to log: dominant peak frequencies, amplitude trend versus Rg/edge-rate/clamp, and notes on new peaks.
- Pass criteria (placeholders): peak trend improves monotonically with at least one knob; regressions trigger layout/return review.
- Purpose: convert validated behavior into a reproducible configuration for production and debugging.
- Setup: freeze Rg_on/Rg_off, Vneg (if used), dead-time, DESAT blanking/threshold, soft-off profile, FAULT policy.
- What to log: final parameter list + corner results summary; retest results after rework or board spin.
- Pass criteria (placeholders): configuration passes all required tests for N repeats with no policy deviations.
H2-11. Engineering Checklist (Design → Bring-Up → Production)
This section turns “works on bench” into “repeatable and shippable”. Each checklist item is action-first and ends with a measurable pass/fail placeholder so requirements can be frozen and audited.
- Do: action + instrument/log + boundary condition
- Record: waveform / thresholds / timing / faults
- Freeze: gate-network + protection knobs + recovery policy
- Accept: Pass: X / Fail: Y (placeholders to be replaced by project criteria)
Gate-driver-centric scope: gate loop, protection behavior, timing, and validation artifacts. Isolated power topology and safety standards details are referenced only as interfaces.
Design Gate (Before PCB / Schematic Freeze)
- Write the dead-time and skew budget across PVT (driver delay, skew, controller jitter, layout asymmetry). Pass: DT_margin ≥ X ns across PVT / Fail: DT_margin < Y ns at any corner
- Choose the gate-drive mode (unipolar vs bipolar, -Vg enabled or not) and define safe state on UVLO/power-down. Pass: VGS_off ≤ X V during UVLO / Fail: any measured VGS_off > Y V
- Lock the protection chain (DESAT/SC detection, blanking, soft turn-off current, latch vs auto-retry, reset conditions). Pass: SC response ≤ X µs + controlled VDS/VCE overshoot / Fail: destructive tail or uncontrolled overshoot
- Pre-select gate network (Rg_on/Rg_off split, diode path, optional ferrite/RC) and define the tuning window. Pass: tuning achieves overshoot ≤ X% and ringing ≤ Y cycles / Fail: overshoot > X% or unstable ringing
- Plan Kelvin source/emitter routing as a hard constraint (separate power source vs sense source loop). Pass: Kelvin loop inductance target met (L ≤ X nH) / Fail: shared return causing false turn-on
- Decide the bias interface (VDD2 range, peak/avg current, startup order, decoupling placement rule). Pass: VDD2 ripple ≤ X mVpp at load / Fail: UVLO chatter or repeated toggling
- Define measurement method (probe tips, reference points, bandwidth) before first bring-up. Pass: repeatable VGS/VDS within ±X% across runs / Fail: measurement-dependent conclusions
- Create a “golden waveform spec” (VGS, VDS/VCE, ID, fault timing) as the acceptance baseline. Pass: correlation to golden within X window / Fail: mismatch without documented reason
Bring-Up Gate (EVT / First Power-On to Full Bus)
- Validate OFF behavior first (UVLO, disable, fault) before enabling switching. Pass: VGS stays below X V under all OFF states / Fail: any false pulse above Y V
- Start with low bus + low duty, then step bus voltage and switching energy incrementally. Pass: monotonic trend without new oscillations / Fail: new ringing/overshoot emerges at higher bus
- Run double-pulse tuning loop (Rg_on/Rg_off, clamp, -Vg, dead-time) while logging overshoot and loss proxies. Pass: overshoot ≤ X and stable turn-off / Fail: overshoot spikes or VGS bounce causing spurious turn-on
- Inject short-circuit / DESAT faults at controlled conditions; confirm blanking avoids nuisance trips. Pass: trip on real SC, no trip on normal switching / Fail: nuisance trip or missed SC
- dv/dt stress test (worst switching corner) and measure false turn-on probability. Pass: false turn-on rate ≤ X / Fail: any shoot-through event or repeated false turn-on
- Freeze the “safe recovery” policy (latch/reset conditions, cooldown time) based on measured transients. Pass: deterministic recovery without oscillation / Fail: auto-retry storm or re-trigger loop
Production Gate (PVT / Manufacturing Test & Traceability)
- Parameter freeze + version lock (gate resistors, blanking, soft-off, dead-time, fault mapping). Pass: BOM + firmware + settings versioned and traceable / Fail: uncontrolled tuning drift
- Define test hooks for VDD2, fault pins, enable/reset, and waveform capture points. Pass: test coverage ≥ X% of failure modes / Fail: key faults not observable
- Hi-pot / isolation test interface defined (fixture points, limits, ramp, dwell) without stressing sensitive nodes. Pass: no latent damage + consistent results / Fail: field failures traced to test-induced stress
- Fault code strategy mapped to hardware events (UVLO, DESAT, OT, OCP) with clear latch/clear policy. Pass: unique root-cause code per class / Fail: ambiguous “generic fault” dominating logs
- Golden waveform audit on sample units (AQL) and drift tracking across lots. Pass: drift within X band / Fail: drift exceeds Y band without approved ECO
SVG-11 — Gate-driven engineering “gates” keep driver behavior deterministic: budget → validate → freeze → production audit.
H2-12. Applications & IC Selection Logic
Selection is organized as a driver-centric decision tree: device type → topology → protection level → dv/dt environment → diagnostics → bias interface. This avoids system-level detours while staying directly actionable.
Application Buckets (by gate-driver requirements)
- Motor / Traction inverter (IGBT / SiC) — very high dv/dt, strong protection, robust Miller clamp behavior, clear fault reporting. Examples (drivers): UCC21750 / UCC21750-Q1, ADuM4135, 1ED3461MC12M, ACPL-337J-000E
- Industrial PSU / PFC / UPS (Si MOSFET / SiC) — repeatability, clean disable/UVLO behavior, EMI tuning knobs and stable timing. Examples (drivers): UCC21530 / UCC21530-Q1, ADuM4136, Si8275GBD-IS1
- High-frequency switching (often GaN-class constraints) — tight timing, very low loop inductance, edge-rate control, predictable faults. Examples (drivers): UCC21530, Si8275GBD-IS1 (DESAT may be replaced by fast OCP depending on system policy)
Bias part numbers above are listed only as “driver-side interface examples” (startup, UVLO headroom, ripple, and decoupling constraints). Power-topology details belong to the Isolated Power page.
Selection Decision Tree (driver-centric)
- Step 1 — Power device type: IGBT vs SiC vs GaN-class constraints → decide drive voltage and turn-off strategy (0 V vs -Vg). Pass: VGS_off margin ≥ X V at worst dv/dt / Fail: false turn-on observed
- Step 2 — Topology: single switch vs half-bridge → channel count, interlock requirement, and matching/skew budget. Pass: skew ≤ X ns across PVT / Fail: shoot-through risk due to skew or dead-time deficit
- Step 3 — Protection level: DESAT/SC + soft turn-off required or not; define blanking and recovery policy (latch vs retry). Pass: SC trip within X µs + controlled overshoot / Fail: nuisance trips or missed SC
- Step 4 — dv/dt environment: choose CMTI class and prioritize low injection + solid Miller clamp behavior; enforce Kelvin routing. Pass: no false turn-on at dv/dt ≥ X kV/µs / Fail: repeated clamp events or spurious faults
- Step 5 — Diagnostics: READY/FAULT pins, fault categorization (UVLO vs DESAT), and reset sequencing. Pass: fault root-cause visible in logs / Fail: generic faults dominate without isolation
- Step 6 — Bias interface: VDD2 range, peak/avg current, UVLO headroom, ripple tolerance, and decoupling placement rule. Pass: stable VDD2 with ripple ≤ X mVpp / Fail: UVLO chatter or jittery turn-off behavior
Minimum Selection Inputs (10 fields)
- Device: IGBT / SiC / GaN-class constraints
- Bus voltage class: X V
- Topology: single / half-bridge
- Switching freq: X kHz / MHz
- dv/dt target: X kV/µs
- Gate bias: +Vg / -Vg (Y/N)
- Protection: DESAT (Y/N) + soft turn-off (Y/N)
- Diagnostics: fault/ready pins required (Y/N)
- Thermal budget: ambient + airflow constraints
- EMI constraints: edge-rate knob required (Y/N)
Example Part-Number Shortlists (non-exhaustive)
- Single-channel isolated drivers with DESAT + active Miller clamp + soft turn-off: UCC21750 / UCC21750-Q1; ADuM4135; 1ED3461MC12M; ACPL-337J-000E Use when: SC handling must be deterministic and false turn-on risk is high
- Dual-channel isolated drivers for half-bridge timing/matching focus: UCC21530 / UCC21530-Q1; SI8275GBD-IS1 Use when: interlock/skew budget dominates and DESAT is handled elsewhere
- Isolated bias / driver-side supply examples: MGJ2D051505SC (+15V/-5V, 5V in); MGJ2D151505SC (+15V/-5V, 15V in); R05P15S (15V out, 5V in); UCC14240-Q1 (integrated transformer bias module); SN6505B (transformer driver) Use when: VDD2 ripple/UVLO headroom and startup order are the limiting factors
Suffix/package variants exist. Always cross-check: isolation rating, creepage/clearance, UVLO thresholds, and timing specs against the project budget.
SVG-12 — Decision tree keeps the page vertical: every node maps to a driver-meaningful constraint (timing, protection, dv/dt immunity, diagnostics, bias).
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H2-13. FAQs (Troubleshooting & Acceptance Criteria)
Each FAQ is a field-ready closure: Likely cause → Quick check → Fix → Pass criteria (numeric placeholders X/Y/N). Scope is strictly driver-centric: Miller/clamp, DESAT/blanking, soft turn-off, UVLO, skew/dead-time, layout/gate loop, and logging definitions.
Half-bridge sporadic shoot-through — skew/dead-time or Miller false turn-on first?
Likely cause: Dead-time margin smaller than worst-case skew OR VGS_off bump crosses threshold due to dv/dt injection.
Quick check: Measure HS/LS propagation delay and skew at temperature Y °C; capture HS VGS during LS turn-on to quantify VGS_off bump (peak and duration).
Fix: Increase dead-time by X ns (or tighten matching); strengthen OFF path (lower Rg_off, enable Miller clamp earlier, optional -Vg within safe UVLO headroom).
Pass criteria: Skew ≤ X ns across PVT AND shoot-through events = 0 over N switching cycles at VBUS = Y V (worst dv/dt corner).
DESAT trips immediately at power-up — blanking first or routing coupling first?
Likely cause: Blanking time too short during turn-on/diode recovery OR DESAT node is a high-impedance antenna coupled to the switch node.
Quick check: Scope DESAT pin vs gate command during first pulses; compare nuisance rate with DESAT lead temporarily shielded/shortened and with blanking increased by X ns.
Fix: Increase blanking to cover turn-on transient (set to X ns); add RC filtering per driver guideline; reroute DESAT away from SW node with a quiet reference return (Kelvin/sense return).
Pass criteria: Nuisance DESAT trips ≤ N per 10^6 switching edges at VBUS = X V and T = Y °C; true SC trips still occur within Y µs.
After SC protection triggers, VDS overshoot becomes larger — soft turn-off too weak or too slow?
Likely cause: Soft turn-off profile mismatched: too aggressive current change excites loop inductance OR too weak pull-down prolongs current and raises energy/overshoot.
Quick check: Log VDS/VCE peak and dV/dt during SC event; compare three settings: soft-off strength low/medium/high while keeping bus and load identical.
Fix: Tune soft-off to a two-step profile (fast clamp then controlled ramp); adjust gate discharge path (Rg_off, active pull-down) and minimize gate loop inductance.
Pass criteria: SC trip latency ≤ X µs AND VDS/VCE peak ≤ Y V (or ≤ Y%) with ringing ≤ N cycles; repeated SC tests show variation ≤ X%.
Faster SiC makes EMI worse and false triggers appear — tune Rg first or enable Miller clamp first?
Likely cause: dv/dt peak increased, causing both radiated/conducted emissions and VGS_off bump; clamp not effective early enough or OFF impedance too high.
Quick check: Measure dv/dt (kV/us) and VGS_off bump (V, ns) at the offending condition; correlate false triggers with dv/dt peaks and clamp activity.
Fix: Stabilize first with Rg_on/Rg_off (reduce dv/dt peak), then enforce OFF robustness (Miller clamp + Kelvin source + optional -Vg) once supply headroom is verified.
Pass criteria: dv/dt ≤ X kV/us AND VGS_off bump ≤ Y V; false triggers ≤ N per 10^6 edges while EMI pre-scan trend improves monotonically vs baseline.
Negative gate-off (-Vg) makes the system less stable — UVLO chatter or gate ringing first?
Likely cause: Bias headroom insufficient leading to UVLO toggling OR -Vg increases loop energy and worsens ringing/undershoot with parasitics.
Quick check: Measure VDD2 and -Vg rails at driver pins (mVpp ripple, droop under pulses); capture VGS undershoot/overshoot with Kelvin reference.
Fix: Increase bias headroom and decoupling at pins (lower impedance loop); reduce -Vg magnitude to -X V; add controlled damping (Rg_off, split network) while keeping clamp effective.
Pass criteria: UVLO toggles = 0 over Y seconds at worst load; VGS undershoot ≥ -X V limit and overshoot ≤ Y V; nuisance faults ≤ N per 10^6 edges.
Same settings: room temp OK, high temp trips protection — threshold drift or driver current degradation?
Likely cause: Threshold/reference drift across temperature OR reduced effective drive strength changes switching transient and trips comparators earlier.
Quick check: Repeat the exact test at T = Y °C and compare: DESAT trip point timing, blanking margin, VGS rise/fall time, and VDD2 droop under pulses.
Fix: Re-center thresholds/blanking with margin to worst-case corner; ensure bias rail meets headroom at temperature; adjust gate network to keep transient within comparator immunity.
Pass criteria: Trip threshold stays within ±X% and trip latency within ±Y µs over temperature range; no nuisance trips over N cycles at hot corner.
High-side power-down causes momentary false turn-on — wrong safe-state definition or return path crossing the barrier?
Likely cause: Output not forced to a deterministic safe state during UVLO/power-down OR unintended return path couples across isolation gap and lifts the gate reference.
Quick check: Capture VGS during VDD2 ramp-down at the driver pins; inspect whether gate discharge remains effective and whether any cross-gap return exists in layout.
Fix: Enforce a hard gate-discharge path to safe state; increase UVLO hysteresis margin; remove cross-gap return and keep gate loop strictly local with Kelvin reference.
Pass criteria: During power-down, VGS stays ≤ X V with no pulse > Y ns; safe-off reached within Y ns; false turn-on count = 0 over N shutdown cycles.
False triggers only at a certain bus-voltage range — dv/dt peak window or layout parasitic inductance first?
Likely cause: dv/dt peaks occur in a specific operating window OR parasitic inductance/resonance creates VGS bounce only at certain energy levels.
Quick check: Sweep VBUS from X to Y V and log dv/dt, VGS_off bump, and fault counts per 10^6 edges; compare with a temporary gate-loop inductance reduction (shorter loop test).
Fix: Reduce dv/dt peak via Rg tuning; strengthen OFF robustness (clamp + Kelvin); tighten layout to minimize loop inductance and keep sense lines away from SW node.
Pass criteria: Fault/false-trigger rate ≤ N per 10^6 edges across the full VBUS sweep; VGS_off bump ≤ X V at dv/dt = Y kV/us throughout.
DESAT looks “normal” but the device still fails — wrong sensing point or response-time budget wrong?
Likely cause: DESAT senses the wrong electrical point (or is masked by coupling) OR detection-to-action latency exceeds the safe energy window.
Quick check: Verify DESAT reference point and return path; measure detection-to-gate-action latency (µs) and compare to the device safe SC withstand time at current/temperature.
Fix: Move/clean the sensing point and routing; reduce blanking where safe; strengthen action path (faster clamp/turn-off) while controlling overshoot via tuned soft-off.
Pass criteria: Detection-to-action latency ≤ X µs with correct sensing; repeated SC tests N times show zero catastrophic failures and overshoot ≤ Y V.
A specific production batch is more prone to false triggers — device variation or assembly/loop inductance change?
Likely cause: Layout/assembly shifts loop inductance/grounding OR device parameter spread shifts threshold margins in combination with dv/dt.
Quick check: Compare golden waveform metrics (VGS ringing peak, dv/dt, trip counts) across N units; correlate with assembly indicators (lead length, placement, torque, bonding).
Fix: Tighten assembly controls that affect loop inductance; increase margin via clamp/Rg_off/UVLO hysteresis; lock measurement method so comparisons are apples-to-apples.
Pass criteria: Across N units, false-trigger rate ≤ X per 10^6 edges and waveform metrics remain within ±Y% of golden baseline; no unit exceeds Y VGS ringing peak.
Turn-off ringing is large but efficiency is acceptable — suppress ringing first or protect behavior first?
Likely cause: Parasitic resonance dominates turn-off waveform; suppressing it aggressively may break protection timing or increase losses unexpectedly.
Quick check: Verify protection determinism first: SC injection timing, DESAT stability, and OFF-state immunity; then quantify ringing (peak, frequency, cycles) with a consistent probe setup.
Fix: Preserve protection determinism (do not slow action beyond budget); then apply controlled damping (Rg_off split, targeted ferrite/RC if validated) and reduce loop inductance.
Pass criteria: Protection actions remain within latency budget X µs; ringing peak ≤ Y V and ≤ N cycles while false turn-on rate stays ≤ X per 10^6 edges.
EMI tests pass but field faults still happen — logging definition first or threshold/window first?
Likely cause: Fault counters/logging windows do not match real events OR thresholds are too tight for field dv/dt/temperature distribution.
Quick check: Standardize logging: define denominator/time window (events per Y minutes) and capture raw waveforms at the same time; correlate faults with dv/dt peaks and VDD2 droop.
Fix: Align logging definitions and thresholds to measured distributions; widen margins where safe; ensure clamp/UVLO behavior is deterministic under worst-case field conditions.
Pass criteria: Fault rate ≤ N per Y hours in field-equivalent stress; fault classification consistency ≥ X%; no nuisance trips over N switching cycles at worst dv/dt corner.
