Isolated I²C: Bidirectional Open-Drain, Stretch & Fail-Safe
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Isolated I²C: Bidirectional Open-Drain, Stretch & Fail-Safe
Core idea: Isolated I²C splits one open-drain bus into two RC domains and relies on a bridge to preserve LOW-dominance, release timing, and clock stretching across the barrier.
In-scope: Iso-I²C bridge behaviors, pull-ups/RC rise-time, arbitration/ACK/START/STOP, clock stretching, UVLO & fail-safe defaults, timing/EMI budgets, layout + validation.
Out-of-scope: Isolated power topologies (Isolated Power), isolated RS-485/CAN/LIN PHY details (Isolated RS-485/CAN/LIN), and standards deep dive (Safety & Compliance).
1. What Is Isolated I²C (Scope, Definition, Non-goals)
Definition (why it is hard)
I²C correctness is tied to line-level physics: devices only pull lines LOW (open-drain), while HIGH levels depend on pull-ups and the total bus capacitance. Isolation turns one bus into two buses, and a bridge must mirror LOW states and releases without breaking start/stop detection, ACK timing, and arbitration behavior.
- Open-drain reality: “drive LOW” is active; “go HIGH” is passive through pull-ups.
- RC rise-time: the HIGH transition depends on Rpull-up and Cbus.
- Split-bus effect: isolation creates two RC domains + a bridge delay/asymmetry.
Scope guard (anti-cross-over)
This page focuses on the isolated I²C bridge and bus-level behaviors. Power conversion, differential transports, and certification procedures are referenced only for routing to dedicated pages.
Do not expect: flyback design steps, CAN/RS-485 termination rules, or IEC/UL clause-by-clause explanations.
Do expect: design hooks that keep I²C semantics intact across a galvanic barrier.
2. When to Use It (Ground Shift, Noise, Safety Partition)
Use isolated I²C when these triggers exist
- Ground shift / common-mode noise: switching power stages, motor/inverter environments, or long return paths that inject glitches into SDA/SCL.
- Safety partition required: a galvanic barrier is mandatory for basic/reinforced insulation or defined working voltage (details routed to Safety & Compliance).
- Two-supply domains: sensors/ADC front-ends referenced to a “floating” ground that must not share DC continuity with the MCU side.
Do not use isolated I²C as a “long-cable fix”
I²C is not designed for long-distance cabling. Isolation removes DC ground coupling but does not eliminate rise-time limits and susceptibility to cable capacitance.
Routing rule: If distance/cable capacitance dominates the budget, prefer a differential transport and isolate that interface instead.
Fast routing links: Isolated UART/GPIO · Isolated RS-485/CAN/LIN
Go/No-go checklist (quick decision)
- Safety barrier required? Yes → isolation is mandatory (choose basic/reinforced in the safety page).
- Noise / dv/dt severe? If expected dv/dt ≥ X kV/µs or ground shift ≥ Y V → isolate or keep I²C local and redesign partition.
- Distance / Cbus high? If bus rise-time cannot meet target tR ≤ X ns → switch to differential transport.
3. I²C Electrical Reality (Open-Drain, Pull-ups, RC Rise-Time)
Open-drain means HIGH is a “timed event”
Since devices do not actively drive HIGH, the bus must rise through pull-ups into the bus capacitance. Any isolation bridge effectively creates two rise-time problems: one on each side of the barrier.
- Rise-time budget: target tR ≤ X ns for the chosen mode (100k / 400k / 1M).
- Capacitance sources: device pins + traces + connectors + cable + ESD parts.
- Trade-off: smaller pull-up R improves tR but increases static power and EMI edge energy.
Practical budgeting (simple, repeatable)
Step 1: estimate Cbus per side (Cpin_total + Ctrace + Cconnector + Cesd).
Step 2: choose Rpull-up to meet tR margin (leave ≥ X% timing headroom).
Step 3: verify VOL margin at IOL with worst-case temperature.
4. Isolation Architectures for Bidirectional I²C (How the Bridge Works)
Three practical bridge families
- LOW-mirroring bridge: detects LOW on one side and actively pulls LOW on the other side; release is passive via pull-ups.
- Split-bus controlled domains: each side behaves like an independent bus; the bridge maintains consistent LOW/release behavior.
- Filtered / de-glitched variants: improved noise tolerance, but verify impact on short pulses and arbitration edge cases.
What must be preserved (non-negotiables)
LOW dominance: LOW must propagate fast enough to preserve ACK and arbitration.
Release integrity: release delay/asymmetry must not collapse tHIGH margins.
Stretch support: SCL low-extension must pass through without truncation.
5. Protocol Behaviors the Bridge Must Preserve (Arbitration, ACK, START/STOP)
Why “it toggles” is not enough
Many failures only appear at protocol edges: repeated START, arbitration under contention, and ACK sampling. The bridge must preserve LOW dominance and timing relationships so that both sides observe the same logical bus state.
- Arbitration: if one master drives LOW, every node must see LOW within the arbitration window.
- ACK/NAK: the ACK low pulse must be visible across the barrier with correct hold/release timing.
- Repeated START: short windows and edge ordering are sensitive to delay and filtering.
Verification targets (measurable)
Arbitration pass: no false HIGH observed during LOW dominance in window ≤ X ns.
ACK pass: ACK low width ≥ X ns and sampled correctly at the master input.
Repeated START pass: START/STOP detection remains stable across Y repeats.
6. Clock Stretching Across Isolation (Hard Cases & Pass Criteria)
What must remain true
Clock stretching is a device-driven extension of SCL LOW. An iso bridge must propagate the LOW state quickly and keep it asserted for the full duration. Any internal timeout, filtering, or asymmetric release can break stretching and produce intermittent NAK/timeout behavior.
- Propagation: SCL LOW must mirror across the barrier within ≤ X ns.
- Hold: maximum stretch time supported must exceed worst-case device stretch by ≥ Y%.
- Release: release must not create a short HIGH “glitch” that the master interprets as a clock edge.
Measurement plan (simple)
Quick check: capture SCL on both sides with a common time reference; compare LOW start and LOW end edges.
Fix levers: disable/adjust filters, reduce RC rise-time, confirm the bridge has no stretch timeout.
Pass criteria: no false clock edges during stretch; stretch completes within the master timeout budget.
7. UVLO & Fail-Safe States (Power-Up/Down, Brownout, Bus-Idle)
Fail-safe goal: never trap the bus
The most common field failure is a stuck LOW bus caused by partial power states (one side up, the other side down) or brownout chatter. Define a default line behavior under UVLO and ensure it is diagnosable and consistent.
- Preferred default: Hi-Z on SDA/SCL during UVLO (unless a system-level reason requires forcing LOW).
- Brownout control: add debounce or state windows to prevent repeated pull-down/release oscillation.
- Recovery: document a bus-unlock routine (clock pulses + STOP) and verify it across isolation.
Define pass criteria (testable)
Power sequencing pass: in all (VDD1,VDD2) combinations, bus returns to idle HIGH within ≤ X ms.
Brownout pass: no stuck-LOW after Y brownout events; status logs remain consistent.
Fail-safe pass: UVLO state is detectable (pin/flag) and does not create phantom START/STOP.
8. Timing Budget & Signal Integrity (Delay, Asymmetry, Filters)
Budget the “hidden” delays
Isolation bridges can introduce different delays for pull-down versus release. Release delay is often more harmful because it reduces the effective HIGH time and can distort the sampling window.
- tLOW path: device pull-down + bridge mirror delay + receiver threshold.
- tHIGH path: release delay + RC rise-time + filter latency.
- Filters: improve glitch immunity but can eat short pulses (verify repeated START and arbitration).
Pass criteria (portable across projects)
Margin target: keep ≥ X% slack in tHIGH and tLOW after adding bridge delay and rise-time.
Asymmetry target: |delay_low − delay_release| ≤ Y ns (or a documented budget).
Glitch target: no false START/STOP under injected noise of X V at Y MHz.
9. EMC/ESD & Barrier Coupling (Cbarrier, dv/dt Injection)
Isolation does not mean “no coupling”
Parasitic barrier capacitance can inject common-mode currents across the isolation barrier during fast dv/dt events. The I²C lines may then see glitches or threshold shifts, especially when rise-time margins are already small.
- Primary risk: dv/dt → Cbarrier → CM current → line disturbance.
- Mitigation knobs: reduce loop areas, manage edge rates, and keep a clean return strategy on each side.
- ESD strategy: clamp near the connector/entry, and keep clamp return paths short and controlled.
Pass criteria (system-level)
Noise immunity pass: no false START/STOP under worst-case switching and cable conditions.
ESD pass: after ESD event, bus returns to idle within ≤ X ms and device enumeration remains stable.
EMC pass: error rate ≤ X / hour during defined dv/dt stress test.
10. Pull-up Strategy on Both Sides (Domains, Hot-Plug, Power)
Two pull-up domains, two rulesets
- Rule 1: each side pulls up to its own supply rail (VDD1 / VDD2); avoid cross-domain pull-ups.
- Rule 2: keep rise-time within budget on each side (do not assume one side “fixes” the other).
- Rule 3: consider hot-plug and partial power states; ensure fail-safe Hi-Z during UVLO.
Hot-plug behavior (what to design for)
Risk: insertion/removal can create stuck-LOW or phantom edges.
Quick check: verify that unplugged side does not back-power lines via ESD diodes.
Pass criteria: after hot-plug, bus scan succeeds within ≤ X s without manual reset.
11. Layout & PCB Partition (Keep-out, Return Paths, Routing)
Partition rules for iso-I²C
- Strict split: keep primary and secondary copper regions separated; do not route returns “across” the barrier.
- Short I²C routes: minimize loop area; avoid parallel runs near fast switching nodes.
- Edge shaping: small series resistors near the source can reduce ringing (validate timing budget).
- Clearance language: use the safety page for creepage/clearance and pollution-degree rules.
Bring-up validation (layout-aware)
Quick check: probe SDA/SCL at both ends of each segment; confirm rise-time and ringing.
Noise check: correlate errors with switching events; look for CM injection signatures.
Pass criteria: stable idle levels, no phantom START/STOP, and tR/tHIGH margins meet targets.
12. Applications & IC Selection (Decision Tree + Design Checklist)
Selection dimensions (what to check first)
- Speed mode: 100k / 400k / 1M (confirm true support; do not assume “I²C” means fast-mode-plus).
- Stretch handling: max supported stretch time, whether internal timeouts exist, and whether filters can truncate low holds.
- Fail-safe / UVLO: Hi-Z defaults on partial power states; explicit status indication is preferred.
- Noise environment: CMTI and barrier coupling characteristics (route deeper safety/spec terms to their pages if needed).
- I/O rail ranges: pull-up voltage compatibility on both sides.
Design checklist (bring-up → production)
- Budget: compute tR and tHIGH margins on both sides; reserve ≥ X% slack.
- Scope: probe both sides simultaneously; verify no release asymmetry beyond Y ns.
- Stretch: force worst-case stretch; verify no false edges and no truncation.
- Power states: test all (VDD1,VDD2) combinations and brownout sequences; confirm no stuck-LOW.
- EMC/ESD: inject stress and verify recovery to idle within ≤ X ms with stable enumeration.
- Production: define pass/fail metrics (error rate, scan success, recovery time) and document them.
Quick pairings (example patterns)
Motor/drive sensing: keep I²C local to the sensing island, isolate at the partition, and validate dv/dt injection paths.
Precision sensor island: iso-I²C bridge + controlled pull-ups + stable UVLO/fail-safe defaults.
Service connector: treat hot-plug as a first-class requirement; clamp and route for stable recovery.
13. FAQs (Troubleshooting & Acceptance Criteria)
FAQ intent
This section closes on field troubleshooting and acceptance metrics. It does not introduce new device classes or unrelated interfaces.
Bus stuck LOW after one side powers down — what is checked first?
Likely cause: partial power state back-powering or non-fail-safe bridge pulling lines LOW under UVLO.
Quick check: test all (VDD1,VDD2) states and observe SDA/SCL idle levels on both sides.
Fix: enforce Hi-Z fail-safe under UVLO; prevent back-power paths; add recovery routine.
Pass criteria: bus returns to idle HIGH within ≤ X ms in all power states.
Clock stretching works without isolation but fails with the bridge — why?
Likely cause: internal timeout/filtering truncates long SCL LOW, or release asymmetry creates false clock edges.
Quick check: compare SCL low-hold start/end on both sides; search for brief HIGH glitches.
Fix: select a bridge with explicit stretch support; adjust/remove filters; improve rise-time margin.
Pass criteria: no false edges during stretch; stretch completes within master timeout with ≥ X% margin.
100 kHz is stable, 400 kHz is flaky — is it RC or bridge delay?
Likely cause: rise-time (tR) consumes tHIGH budget, and bridge release delay further reduces margin.
Quick check: measure tR on both sides; measure release delay vs pull-down delay.
Fix: tune pull-ups per side; reduce Cbus; avoid heavy glitch filters; rebudget tHIGH.
Pass criteria: tR ≤ X ns and tHIGH margin ≥ Y% at worst case.
Random NAK spikes during motor switching — is CMTI or layout first?
Likely cause: dv/dt injection through barrier capacitance plus weak rise-time margin creates false edges.
Quick check: correlate NAK bursts with switching events; probe both sides for glitches.
Fix: reduce loop areas and improve return strategy; shape edges; strengthen timing margin.
Pass criteria: error rate ≤ X/hour under defined dv/dt stress test.
Hot-plug causes devices to disappear until reboot — what breaks?
Likely cause: hot-plug transients create stuck-LOW or phantom START/STOP; back-power via protection diodes.
Quick check: unplug/plug while monitoring idle levels; verify no line is held LOW after insertion.
Fix: enforce fail-safe Hi-Z; add bus-unlock routine; improve clamp placement and return.
Pass criteria: bus scan completes within ≤ X s after hot-plug with no manual reset.
Repeated START fails intermittently — could a glitch filter be the culprit?
Likely cause: filter/edge conditioning removes short transitions, altering START/STOP recognition across the barrier.
Quick check: capture SDA/SCL around repeated START; look for shortened pulses or delayed releases.
Fix: reduce filtering, rebudget timing, or use a bridge validated for repeated START behavior.
Pass criteria: repeated START succeeds for Y consecutive cycles at worst case.
Idle looks HIGH, but the decoder reports glitches — what is checked first?
Likely cause: ringing near thresholds, probe loading, or CM injection causing brief crossings.
Quick check: verify probe bandwidth/grounding; check ringing amplitude and threshold crossing time.
Fix: add small series resistors; improve routing; rebalance pull-ups; verify filter settings.
Pass criteria: no threshold crossings beyond X mV for longer than Y ns at idle.
Arbitration fails in multi-master — what is the isolation-specific suspect?
Likely cause: LOW dominance not mirrored fast enough or release asymmetry causes one side to see a false HIGH.
Quick check: force arbitration events; compare LOW propagation delay across the barrier.
Fix: use a bridge rated for arbitration; reduce filters; increase timing margin.
Pass criteria: no false HIGH in arbitration window ≤ X ns; arbitration succeeds for Y trials.
One target behaves, another fails — is it capacitance or stretch profile?
Likely cause: different target pin capacitance or a longer/variable stretch time hits bridge limits.
Quick check: compare Cbus and stretch duration by target; test each target on an isolated segment.
Fix: tune pull-ups; reduce bus loading; ensure bridge stretch capability exceeds worst case.
Pass criteria: stable communication across all targets with tR ≤ X ns and no timeouts for Y minutes.
After ESD, the bus “recovers” but devices return as ghost addresses — why?
Likely cause: partial latch-up or corrupted state causes false responses; line leakage or stuck intermediate levels.
Quick check: confirm idle voltages; power-cycle only the target domain to isolate culprit behavior.
Fix: improve clamping/return path; add reset sequencing; validate fail-safe behavior under UVLO.
Pass criteria: correct device enumeration after ESD within ≤ X s and remains stable for Y scans.
Two pull-ups are present but waveforms look worse — what mistake is common?
Likely cause: pull-ups are too strong (excess edge energy/ringing) or inadvertently cross-domain; Cbus underestimated.
Quick check: verify pull-ups return to local rails; sweep R values and watch tR and ringing.
Fix: select per-side pull-ups for the measured Cbus; add damping; avoid cross-domain pull-ups.
Pass criteria: tR meets target with ringing ≤ X mV and error rate ≤ Y/hour.
Brownout storms cause endless retries — what is changed first?
Likely cause: UVLO chatter toggles the bridge state; lines repeatedly assert/release and confuse the protocol state machine.
Quick check: reproduce with controlled droop; observe whether fail-safe state oscillates near threshold.
Fix: add UVLO hysteresis/debounce window; enforce Hi-Z during UVLO; add recovery before retries.
Pass criteria: no stuck-LOW after Y brownouts; recovery completes within ≤ X ms.
