Card A · When to use an integrated isolated transceiver

Typical triggers are cable-domain risks that cannot be fully controlled by grounding alone:

• Ground potential differences (GPD): long cables or multi-cabinet wiring with unpredictable reference shifts.
• High dv/dt environments: motor drives, inverters, switching cabinets, or dense power stages near the bus.
• Frequent human interaction: service tools, maintenance ports, or field connectors exposed to contact ESD.
• Intermittent field failures: bus-off / CRC spikes / framing errors that do not reproduce on a clean bench.
• Safety boundary needs: a defined isolation barrier between user-accessible wiring and internal electronics.

Card B · Scope guard (what is covered vs excluded)

This page covers RS-485/CAN/LIN isolation at the PHY/port level:

• Two-domain partitioning (logic-side vs bus-side), and “no return across the barrier” rules.
• Fail-safe receiver behavior, default states, and diagnosable fault handling.
• Port stack hardening: TVS/CMC/termination placement principles and verification criteria.

This page excludes (handled by sibling pages):

• Isolation technology deep dive (capacitive/magnetic/opto-replacement internals).
• Isolated DC-DC topology design (flyback, push-pull, bridge converters).
• Protocol-stack topics (CANopen/UDS/Modbus application-layer behavior).
• Full safety-standard tutorials (only datasheet fields and test I/O are referenced here).

Card C · Quick decision rules (integrated vs discrete approach)

1. If the design must pass harsh ESD/EFT/surge with high dv/dt immunity, then an integrated isolated transceiver typically reduces coupling paths and uncontrolled interactions.
2. If field failures are intermittent and grounding is not guaranteed, then isolate the bus domain first to confine disturbances and simplify diagnosis.
3. If CAN-FD timing margin is tight (delay symmetry matters), then integrated solutions often improve predictability—while external TVS/CMC parasitics must still be controlled.
4. If a mature discrete design is already validated in production, then discrete may remain more flexible (cost, sourcing, tunability) without forcing a redesign.
5. If the system requires explicit default states and fault reporting, then prioritize devices with clear fail-safe definitions and diagnosable outputs (FAULT/READY pins or equivalent).

Card A · Block-level partition rules (hard constraints)

• Two grounds by design: define GND1 (logic-side) and GND2 (bus-side). No copper, vias, or “helper” straps may bridge them.
• Connector belongs to the bus domain: protection and termination should be physically placed to keep surge/ESD current loops inside the bus-side region.
• No return across the barrier: any ESD/EFT/surge return path must close on the bus-side, not through the controller ground network.
• Short, direct protection paths: connector → TVS → chassis/bus return should be the lowest-inductance route available.

Card B · Signals and power pins (PHY-visible behavior)

Typical control and status pins (names vary across devices) and what they imply at the system level:

• TXD / RXD: logic-domain data interface. Latency and symmetry matter most for CAN-FD timing margin.
• EN / STB / SLEEP: defines power-down modes and recovery behavior. Default states must be intentional.
• FAULT / READY: enables diagnosable fail-safe behavior. Use for black-box logging and field triage.
• VCC1 / GND1: logic-side supply and reference.
• VCC2 / GND2: bus-side supply and reference. This domain may float, but return/bleed paths must be explicit.

Card C · What changes vs discrete isolation + standard PHY

• Predictability improves: fewer uncontrolled interactions between separate isolator and transceiver blocks.
• External parasitics still matter: TVS capacitance, CMC imbalance, and termination placement remain decisive for waveform quality.
• Diagnosis becomes cleaner: disturbances are more often confined to the bus-side region, making root-cause isolation faster.
• Verification focus shifts: validate return-path integrity, default states, and immunity under realistic cable + injection setups.

Card A · RS-485 design rules (port-level)

• Mode clarity: define Half-duplex multi-drop vs Full-duplex early; termination and bias placement follow that choice.
• Common-mode window: keep the bus common-mode within the receiver range: Vcm_min…Vcm_max (placeholders). Verify Vcm_peak < X under switching/noise.
• Stable idle: implement fail-safe bias so idle differential stays above noise: |Vdiff_idle| > X mV for Y s (placeholders).
• Bias strength trade-off: too strong increases EMI and DC load; too weak causes idle chatter and false transitions.
• Termination: use 120 Ω at the two ends for the trunk. Split termination may help common-mode control, but RC choices must stay consistent (details expanded in the EMC chapter).
• Stub discipline: multi-drop stability depends on controlling stubs: stub length < X (placeholder) and avoid star-like wiring.
• Protection placement: connector-side TVS and optional CMC must preserve A/B symmetry; imbalance converts common-mode noise into differential errors.

Card B · Top field issues → first checks (not FAQ)

1. Idle chatter / framing errors at low traffic
   • Check Vdiff_idle stability: must not hover near threshold (placeholder: > X mV).
   • Check bias duplication: avoid multiple nodes adding bias in uncontrolled ways.
   • Check Vcm_peak does not exceed the receiver window (placeholder: < X).
2. Short cable OK, long cable / multi-drop unstable
   • Measure worst stub length: placeholder gate stub < X.
   • Confirm termination is only at the trunk ends and not accidentally duplicated.
   • Inspect A/B symmetry (routing + protection parasitics) near the connector.
3. Failures mainly during ESD/EFT or hot-plug events
   • Verify TVS is connector-close and the return loop is short and local to the bus-side.
   • Verify no shield/ground return unintentionally bridges the isolation gap.
   • Check whether protection components introduce A/B imbalance (capacitance or layout).

Card C · What not to do (common failure patterns)

• No cross-gap return: do not route copper/grounds/shield returns across the isolation gap; it creates a hidden coupling channel.
• No distant TVS: do not place TVS far from the connector; surge/ESD current will travel through sensitive board area before clamping.
• No A/B asymmetry: avoid mismatched parasitics (routing, TVS capacitance, CMC imbalance); it converts common-mode noise to differential error.
• No multi-point termination: avoid “extra termination” at intermediate nodes; it shifts impedance and increases reflections.
• No uncontrolled bias stacking: avoid multiple nodes each adding bias; idle state drifts and DC loading rises.
• No star wiring for multi-drop: avoid hub-like stubs; reflections become timing-dependent and intermittent.

Card A · Timing budget checklist (propagation + loop delay)

• Loop delay model: treat round-trip timing as t_loop ≈ tPD1 + t_cable + tPD2 (conceptual). Use worst-case datasheet delays for both nodes.
• Isolation adds delay: the barrier path contributes to tPD and may impact symmetry; budget a placeholder skew limit < Y.
• Sample point margin: require a safety margin margin ≥ X (placeholder) after accounting for cable length and worst-case delays.
• CAN-FD sensitivity: data phase is more sensitive to edge shaping and parasitic imbalance; verify margin under the exact port stack used.

Card B · Protection parasitics vs signal integrity (TVS/CMC/ESD)

• Capacitance matters: CAN-FD is sensitive to TVS capacitance Cj; high or unbalanced capacitance distorts edges and shrinks timing margin.
• Symmetry is critical: keep CANH/CANL parasitics and routing as mirrored as possible; imbalance converts common-mode events into differential distortion.
• CMC trade-off: a CMC can reduce common-mode noise, but its impedance and placement can slow edges; confirm it does not collapse data-phase margin.
• Split termination: can improve common-mode behavior but introduces RC choices; keep the physical placement consistent with the port return strategy.

Card C · Field symptoms → first checks (PHY-level)

1. Arbitration OK, CAN-FD data phase fails → check Cj and asymmetry in the protection stack; then re-check margin.
2. Works on bench, fails with +1 m cable → re-budget t_loop with real cable length and worst-case tPD1/tPD2; verify end termination.
3. Bus-off during EFT/ESD testing → first verify return paths stay on the bus-side and TVS is connector-close; avoid any cross-gap return.
4. Swapping TVS/CMC makes it worse → suspect parasitic changes and imbalance; validate waveform symmetry and error counters.
5. Different labs show different results → align cable/fixture/ground reference and injection setup before changing the design.

Card A · LIN physical behavior (PHY-only) + why isolate

• Single-wire semantics: Recessive is defined by the PULLUP path, not by differential balance.
• Dominant action: the transceiver asserts Dominant by pulling the line low; edge shape depends on pull-up impedance and line load.
• Wake / sleep visibility: wake is triggered by line-level activity; the idle state must remain stable across power states (placeholders: Vrecessive > X, Vdominant < Y, Twake > N).
• Why isolation appears in LIN: ground potential differences, isolated service ports, and domain separation (e.g., HV/service isolation) where an external harness must not couple directly into the control domain.

Card B · Pull-up path + default states (what breaks first)

• Pull-up ownership: define where PULLUP is implemented (bus-side vs harness-side). Isolation changes which reference the pull-up returns to.
• Default line state: specify the line behavior under UVLO / power-down (placeholder: default = recessive/dominant) and verify it is stable and diagnosable.
• First failure mode: unstable idle (threshold-hover) causes false edges; incorrect pull-up return path creates slow edges and inconsistent wake behavior.
• Protection placement: connector-side protection must keep surge/ESD currents local to the harness domain; avoid any unintended cross-gap return path (details expanded in the EMC chapter).

Card C · Pitfalls (bridge to EMC chapter)

• Surge/ESD return loops: keep high-current returns on the harness side and away from the logic domain boundary.
• Hot-plug sensitivity: if wake is triggered during plug/unplug, suspect the pull-up path and protection placement before changing software.
• Hidden coupling: any shield/ground connection crossing the isolation gap defeats the isolation intent.

Card A · Spec map (what to find → why it matters → placeholder gates)

Isolation CMTI Immunity Timing Fail-safe

• Isolation ratings (datasheet fields): look for working voltage and safety/withstand fields (basic vs reinforced). Use them to set the isolation class requirement (placeholders).
• CMTI / dv/dt: find positive/negative CMTI and test conditions. Map it to the system dv/dt source (inverter, motor cabinet). Gate placeholder: CMTI ≥ X kV/µs.
• ESD / EFT / Surge: compare device ratings to system-level expectations; layout determines real performance. Use placeholder gates: ESD ±X, EFT X, Surge X.
• Timing (tPD / skew): find max delay and channel symmetry. For CAN-FD: protect data-phase margin. For RS-485: avoid shrinking distance/baud margin. Placeholders: tPD_max < X, skew < Y.
• Fail-safe / defaults / diagnostics: check receiver default state, UVLO/power-down line state, and status/FAULT outputs. Gate placeholder: default stable for N ms.

Card B · Selection flow (3-step decision tree)

1. Step 1 — Bus type: RS-485 / CAN (HS/FD) / LIN.
   • CAN-FD: prioritize timing + symmetry first.
   • RS-485: prioritize termination + stub + failsafe.
   • LIN: prioritize pull-up + default states.
2. Step 2 — Environment: dv/dt, surge exposure, cable length, service/hot-plug.
   • High dv/dt → raise the CMTI gate.
   • Harsh surge/ESD → raise the immunity gate and enforce connector-side protection placement.
   • Long cable/high data rate → tighten tPD and margin gates.
3. Step 3 — Isolation class + timing + fail-safe: confirm basic/reinforced need, then verify worst-case timing and default/diagnostic behavior.
   • Output: a “must-pass” list with placeholders X/Y/N before choosing final part numbers.

Card C · Red flags (selection pitfalls)

• Only “typical” values: CMTI or tPD provided only as typical without max/worst-case across temperature.
• No test conditions: CMTI listed without supply/load/test setup context.
• Ambiguous defaults: UVLO/power-down line state is not clearly defined (unpredictable bus behavior).
• No diagnostics: no status/FAULT pin while claiming “robust” behavior (hard to debug in the field).
• Timing not aligned to CAN-FD: data-phase support is unclear, or delay/skew limitations are not specified.
• Parasitic risk hidden: no guidance on barrier coupling or EMI considerations while parasitics are likely large.
• Supply constraints mismatch: bus-side supply requirements are strict but system cannot guarantee stable VCC2 behavior.

Card A · Topology rules (Do / Don’t)

bus star stub termination

• DO: keep a single trunk bus with short stubs per node.
• DON’T: build a star unless every branch is extremely short (placeholder: branch < X).
• DO: terminate only where the trunk truly ends (placeholder: end-to-end TERM = 120Ω class).
• DON’T: add “extra” terminations at intermediate nodes; it reshapes impedance and creates reflections.
• Stub gate (placeholder): keep stub length < Y to prevent echo energy from landing inside the decision window.

Card B · Placement rules (connector-side / board-side)

Conn TVS CMC TERM Shield

• Outside → inside order (preferred): Connector → TVS → CMC → Split TERM → Transceiver.
• TVS: place directly at the connector to keep the discharge loop short.
• CMC: place near the connector when used for common-mode suppression; keep the differential pair symmetric to avoid mode conversion.
• Split termination: keep the RC loop compact and referenced to the intended port return (avoid creating a hidden cross-gap return).
• Shield: prefer a short, continuous chassis bond at the entry when possible; avoid long pigtails for high-frequency returns.

Card C · Quick check (minimum instrument set)

• Scope (time-domain): look for edge symmetry, ringing, overshoot, and idle stability near thresholds.
• TDR (reflection scan): confirm termination exists only at true ends; detect hidden branches and star-like junctions.
• VNA (optional): use return-loss trends to spot mismatch regressions after TVS/CMC/connector changes.
• Pass placeholders: error frames / CRC < N per Y minutes; reflection echo amplitude < Z.

Card A · Port protection stack (outside → inside)

TVS CMC TERM return gap

• ESD / Surge first stop: TVS at connector with a short discharge loop to the intended return/chassis node.
• EFT containment: keep high-frequency return currents out of sensitive regions; avoid routing/placing discharge paths near the isolation boundary.
• Common-mode control: use CMC when common-mode noise dominates, and keep the differential pair symmetric to avoid mode conversion.
• Signal stability: use termination (and split termination where appropriate) to control reflections without creating hidden return bridges.
• Hard rule: discharge/return currents must not cross the isolation gap.

Card B · Parasitics trade-offs (Cj / ESL / layout inductance)

• TVS Cj: higher capacitance can reshape edges and reduce timing margin; differential symmetry matters for CAN/485 pairs.
• ESL + loop inductance: long TVS loops slow clamping and increase peak stress; prioritize shortest geometry over “stronger” parts.
• Asymmetry: imbalance converts common-mode events into differential disturbances, raising CRC/error frames.
• CMC interactions: choke + protection + termination parasitics can form resonances; keep placement consistent and routing symmetric.

Card C · Pass criteria placeholders (immunity + system behavior)

• Immunity level placeholders: ESD ±X, EFT Y, Surge Z.
• System tolerance placeholders: error frames / BER < N per Y minutes; unintended resets = 0 (or ≤ N).
• Recovery placeholders: link down time < T; no persistent bus-off after stress removal.
• Diagnosis placeholders: faults must be observable via status/FAULT indications (if available) and repeatable under controlled injection.

Card A · Define defaults (power-down / UVLO / thermal)

Power-down UVLO OT Fail-safe RX

• Power-down (VCC1 or VCC2 off): bus pins must not hold the bus in an unsafe state; receiver output must remain stable (placeholder: no spurious toggles < N within Y ms).
• UVLO entry/exit: define deterministic behavior to avoid oscillation near threshold (placeholders: enter after X ms, recover after Y ms stable supply).
• Thermal warning vs shutdown: separate OT flag (warning) from shutdown (output disable). Keep transitions monotonic (placeholders: OT at X°C, shutdown at Y°C, hysteresis ΔT).
• Fail-safe receiver meaning: idle/open conditions should produce a stable default logic level consistent with system safety goals (placeholder: default = IDLE).

Card B · Fault matrix (fault → symptom → first checks)

SC Open Line-to-GND Line-to-V OT UV

• Line-to-line short (SC): dominant stuck / heavy errors → first check: harness/connector damage + differential pin DC levels + protection heat.
• Line-to-GND: one line pinned low → first check: pin-to-chassis resistance + TVS placement + return path geometry.
• Line-to-V: one line pinned high → first check: supply leakage into bus + wiring polarity + connector contamination.
• Open / broken wire: intermittent link / idle instability → first check: termination presence at true ends + TDR branch detection + idle bias behavior.
• Thermal shutdown (OT): works then drops after load → first check: OT/FAULT flag timing + package temperature rise + supply droop correlation.
• UVLO oscillation (UV): flapping / repeated resets → first check: VCC2 transient capture + UV flag + inrush/hold-up capacity (placeholders: Vmin X, droop Y ms).

Card C · Recovery policy (latch vs auto-retry)

Latch Retry Backoff Black-box

• Latch (recommended): for clear hard faults (persistent short, repeated OT shutdown). Require explicit clear (placeholder: clear via command or power-cycle).
• Auto-retry (allowed): for transient events (EFT/plug events). Use bounded retries (placeholders: max retries N, backoff T ms).
• Recovery conditions: only retry when supply and temperature are stable (placeholders: VCC2 > X, temp < Y).
• Black-box fields (interface-level): last fault code, count, duration, last VCC snapshot, last temperature snapshot (placeholders for field names).

Card A · Lab validation steps

Bring-up Loopback Waveform BER Corners

1. Wiring + termination sanity: confirm termination at true ends; verify idle stability (placeholders: TERM = X, idle drift < Y).
2. Functional link / loopback: establish a clean baseline; record error counters at low load.
3. Waveform snapshot: capture edges/ringing/symmetry at defined probe points (placeholder: ringing < Z).
4. Statistics under load: run BER/error frames for Y minutes; set baseline thresholds (placeholders: BER < X, errors < N).
5. Boundary sweeps: repeat at voltage/temperature corners (placeholders: VCC2 min X, temp range Y).

Card B · Production gates

Hi-pot Fixture Traceability Sampling

• Gate 1 · Insulation / hi-pot: test voltage and time (placeholders: X V for Y s), leakage limit N.
• Gate 2 · Functional fixture: fixed harness + fixed termination; verify link and counters within thresholds (placeholders: errors < N).
• Gate 3 · Corner sampling: sample temperature/voltage corners (placeholder: sample rate X%).
• Traceability fields: board SN, test version, measured counters, pass/fail code (placeholders for field names).

Card C · Acceptance criteria placeholders

BER Errors No reset Recovery Diagnostics

• Communication quality: BER < X over Y minutes; error frames / CRC < N.
• System stability: unintended resets = 0 (or ≤ N); no lock-up; no stuck-dominant.
• Recovery behavior: link recovery time < T; no persistent bus-off after stress removal.
• Diagnostics visibility: FAULT/READY/OT/UV observable and logged with timestamp (placeholder: log fields).