Magnetic / Inductive Digital Isolators (CMTI, Timing, Layout)
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Magnetic/Inductive digital isolators are preferred when wide-temperature stability and harsh dv/dt transients demand deterministic, long-term reliable isolation.
This page turns “robust isolation” into measurable acceptance gates—CMTI/dv/dt, timing margin, EMC coupling paths, and layout rules—so selection and validation can be proven in the lab and repeated in the field.
H2-1. Scope Guard & Decision Map
This section locks the page boundary, aligns measurement language (CMTI / timing / EMI), and routes readers to the right device class without drifting into sibling topics.
In scope
- Magnetic/inductive isolator behavior in high-dv/dt industrial environments (robustness first).
- Unified definitions for CMTI, dv/dt stress, propagation delay, skew, and barrier-coupling EMI paths.
- Selection order that avoids wasted screening: insulation → CMTI → timing → channel/direction → power/temp.
Out of scope (linked only)
- Capacitive isolator internals and trade-offs (see sibling page).
- Opto-drop-in timing/pin compatibility specifics (see opto-replace page).
- Isolated interface protocol/PHY details (SPI/I²C/UART/RS-485/CAN/Ethernet/USB pages).
- Isolated DC-DC topologies and transformer design (isolated power pages).
Three core questions this page answers
Why is inductive coupling often more stable under high dv/dt?
Delivers a concrete injection-path model and failure signatures that match field behavior (false pulses, latch, glitches).
How to keep CMTI, timing, and EMI language consistent?
Defines pass/fail in the same measurement conditions so lab results and field acceptance do not contradict.
Which 5 specs should be screened first?
Prioritizes what constrains feasibility (insulation/CMTI/timing) before “nice-to-have” channel count or data rate.
Quick decision (rule-only, no deep explanation)
- If the environment is high dv/dt + harsh transients (industrial drives/cabinets), start with Magnetic/Inductive.
- If the primary constraint is ultra-low jitter / tight skew, route to Capacitive / Clock Isolator families.
- If the hard constraint is legacy drop-in (pin/timing compatibility), route to Opto-Replace isolators.
Target environment (data placeholders)
dv/dt target
X kV/µs
Temperature range
Tmin ~ Tmax
Working voltage
VIORM ≥ Vx
Execution rule: any content that starts to explain capacitive/opto specifics is out of scope here and must be converted into a link.
H2-2. Definition & Where It Fits (Magnetic/Inductive Digital Isolator)
A magnetic/inductive digital isolator transfers encoded digital information across an isolation barrier using micro-transformer (inductive) coupling, targeting stable behavior across wide temperature and harsh transients.
What it is
- Signal isolation: logic is encoded into high-frequency patterns, coupled across the barrier, then reconstructed.
- Barrier-aware design: channel behavior, defaults, and recovery are defined for power-up, power-down, and input-open cases.
- Industrial fit: commonly used for control links near switching nodes where dv/dt and EFT events are routine.
What it is not (to avoid misuse)
- Not an isolated DC-DC: it does not deliver regulated isolated power to the secondary rail.
- Not a protocol solution: it is a digital barrier; PHY/protocol compliance belongs to interface-specific pages.
- Not “EMI-free by default”: barrier capacitance still forms a common-mode emission path that must be managed.
Typical forms (system-relevant axes)
Channel count & direction
1–8 channels, unidirectional or mixed direction. Direction choices affect timing alignment and default-state strategy.
Supply style & defaults
Independent vs shared supplies, with defined UVLO/power-off outputs. Default states must match system safety expectations.
Data-rate vs determinism
Maximum Mbps is not the only constraint; deterministic delay, channel skew, and recovery behavior often dominate real designs.
Robustness signals
Look for explicit transient-immunity claims and test conditions (dv/dt, EFT) aligned with the intended environment.
Key placeholders (data fields)
Channel count
Nch = 1 ~ 8
Data rate
R = X Mbps
Propagation delay
tpd ≤ Y ns
CMTI target (optional)
≥ Z kV/µs
Where it fits (role in a system)
- Controller ↔ power stage control: isolate PWM/EN/FAULT style signals between low-voltage logic and noisy switching domains.
- Cabinet I/O separation: protect PLC/MCU logic from ground potential differences and transient events on field wiring.
- Board-to-board domain split: enforce functional separation (safety, noise containment, service boundaries) across the barrier.
Misuse prevention: if the real goal is an isolated bus/port (CAN/RS-485/Ethernet/USB) or isolated power, jump to the corresponding page before picking the isolator class.
H2-3. How It Works: Inductive Coupling Architecture
Inductive digital isolation achieves robustness by converting logic into controlled high-frequency patterns, coupling them across a micro-transformer barrier, then reconstructing logic with defined decision rules and fail-safe behavior. This chapter focuses on the signal path only (no isolated power topology).
Signal-chain view (what is happening end-to-end)
- Input conditioning prevents slow edges and local noise from becoming “valid events” that the encoder would amplify.
- Encoding / modulation moves information to a controlled frequency band so slow drift and common-mode disturbances are rejected.
- Micro-transformer coupling transfers energy through magnetic coupling while barrier capacitance remains the dominant CM emission path.
- Demod / decision uses thresholds, windows, and glitch rejection to keep outputs deterministic under transient stress.
- Diagnostics & fail-safe define output states for power-down, input-open, and fault detection so system behavior is predictable.
A. Input conditioning (before encoding)
What it protects against
Slow edges, ringing, ground bounce, and short glitches that would otherwise be interpreted as valid transitions.
What to verify
Glitch immunity and minimum input pulse width behavior are aligned with system noise and switching edges.
B. Encoding / modulation (why logic becomes HF patterns)
- Drift tolerance: the decision relies on pattern presence/absence rather than DC level accuracy across separated grounds.
- Noise rejection: the receiver can filter around the intended band; slow common-mode movement is less likely to pass as data.
- Deterministic reconstruction: windowing + hysteresis + pulse-shape checks reduce “random flips” under harsh transients.
C. Micro-transformer coupling (k, leakage L, and parasitics)
Coupling coefficient (k)
- Sets link margin under worst-case temperature and process variation.
- Low margin manifests as missing pulses, delayed edges, or “works on bench, fails in cabinet”.
Leakage inductance (Llk) & pulse shape
- Shapes bandwidth and ringing; too much ringing can trigger incorrect decisions.
- Pulse shaping impacts both timing determinism and emissions (fast edges ≠ always better).
Barrier capacitance (Cb) — the CM emission path
- Cb forms the primary common-mode current path across the barrier.
- Lower Cb typically reduces CM injection, but system EMI still depends on return paths, enclosure bonding, and edge-rate control.
- Manage CM loops at the PCB level; do not expect the isolator alone to “solve EMI”.
D. Demod / decision + fail-safe behaviors (why it stays predictable)
Decision mechanisms (conceptual)
Threshold + hysteresis, timing windows, pulse-count / consistency checks, and glitch rejection avoid noise-as-data.
Fail-safe expectations
Defined output state on UVLO/power-down; defined behavior for input-open; stable recovery without oscillation.
Field failure signatures (what to recognize quickly)
- False pulse: a short unintended toggle during dv/dt / EFT events.
- Latch / stuck output: output freezes until reset or power cycle.
- Wrong default: power-down or input-open state does not match system safety assumption.
- “Timing drift” that is actually power/noise: apparent delay changes correlate with supply noise or local heating.
Data placeholders (fill with project targets)
Internal carrier / switching
fc = X MHz
Barrier capacitance (CM path)
Cb ≤ Y pF
Glitch ignore (optional)
tGLITCH < N ns
Scope lock: isolated DC-DC / bias generation details are intentionally excluded here and should be handled in the Isolated Power pages.
H2-4. Wide-Temp Stability & Aging Immunity (What “Stable” Really Means)
“Stable” must be measurable: it means predictable timing, predictable decision behavior under stress, and predictable recovery across temperature and lifetime. This chapter converts stability claims into verifiable metrics and design knobs.
Define “stable” in engineering terms
- Timing stability: bounded Δtpd and Δskew across temperature and supply variation.
- Decision stability: low false-pulse probability under specified dv/dt/EFT stress and noise conditions.
- Recovery stability: defined power-up/power-down behavior and repeatable recovery without oscillation or latch.
Drift sources → what they affect
Oscillator / timing reference drift
Shifts internal windows and pattern timing; shows up as Δtpd/Δskew and reduced margin at temperature corners.
Comparator threshold & hysteresis drift
Moves decision boundaries; increases susceptibility to ringing and CM injection if margin is thin.
Bias / gain drift
Changes drive amplitude and receive sensitivity; may look like “timing drift” but correlates with supply noise or heating.
Package stress & thermo-mechanical effects
Couples temperature cycling into parasitics and margins; impacts repeatability after thermal cycling or vibration.
Aging immunity (paradigm-level, without detouring into opto details)
- Opto aging is typically dominated by long-term transfer changes; inductive isolation aging is more often reflected as margin erosion in timing and stress robustness.
- Therefore, lifetime validation should track Δtpd over life, false-pulse rate under stress, and insulation lifetime (handled in Safety & Compliance pages).
- Do not accept “no aging” as a slogan; require explicit lifetime conditions and measurable drift bounds.
System impact (why small drift matters)
- Timing margin collapse: Δtpd/Δskew reduces setup/hold or interlock margin in control links (especially multi-channel).
- Error-rate growth: lower decision margin turns rare events into intermittent faults during dv/dt bursts.
- Validation mismatch: lab “pass” can fail in the field if thermal environment and stress waveforms were not comparable.
Industrial field playbook (temperature + derating)
Hot cabinet
- Use system Tj (self-heating + nearby heat sources), not ambient-only assumptions.
- Budget additional margin for CMTI and decision stability at Tmax.
Cold start & thermal cycling
- Verify defaults and recovery at Tmin; confirm no oscillation around UVLO thresholds.
- After thermal cycles, re-check Δtpd/false-pulse behavior to catch stress-coupled drift.
Data placeholders (fill with acceptance targets)
Operating temperature
-40 ~ 125/150 °C
Timing drift over temperature
Δtpd ≤ X ns
Long-term drift
≤ Y% (of baseline)
Life drift (optional)
Δtpd_life ≤ X2 ns
Practical rule: treat stability as a system budget item (timing + CM injection + recovery), and verify it under realistic thermal and transient waveforms.
H2-5. Transient Robustness: CMTI, dv/dt, EFT/Surge Reality
This chapter turns CMTI from a marketing number into a testable acceptance rule: under specified dv/dt and stress conditions, the output must remain deterministic—no false toggles, no indeterminate state, no latch, and predictable recovery.
CMTI (engineering definition, used across the whole page)
- CMTI is conditional: it is valid only under a defined dv/dt waveform, input state, supply/decoupling, load, and temperature.
- Pass meaning: output does not toggle incorrectly, does not enter an unknown window, and does not lock until reset.
- Comparison rule: two CMTI numbers cannot be compared unless the test conditions are aligned.
Common transient failure signatures (what to label and capture)
Transient toggle
A short incorrect pulse during dv/dt/EFT events; often appears as a narrow glitch or a single extra edge.
Indeterminate output
Multiple flips, pulse-width distortion, or brief uncertainty while the receiver decision window is disturbed.
Latched / stuck state
Output freezes until reset or power cycle; indicates receiver or state machine enters a faulted condition.
Retrain / recovery storm
Repeated self-recovery attempts cause system interruptions; looks “alive” but never becomes stable.
System-level injection path (what actually causes the output to misbehave)
- Source: dv/dt at a nearby switching node or cable/EMI stress.
- Coupling element: barrier capacitance (Cb) provides the cross-barrier common-mode path.
- Carrier: common-mode current loop injects into the secondary reference and front-end.
- Victim: ground bounce and threshold/window disturbance create false decisions or fault latch.
Design knobs (actions that directly reduce transient-induced errors)
Bandwidth & edge management
- Use input/output filtering and edge-rate control to avoid turning noise into valid “events”.
- Keep thresholds and decision windows away from ringing and short glitches.
Reference & return-path control
- Keep primary and secondary return paths local; do not allow hidden return across the isolation gap.
- Minimize loop area for decoupling and output return to reduce injected bounce.
Across-gap routing discipline
- Avoid high dv/dt traces near the barrier; avoid parallel routing that increases capacitive coupling.
- Use slots/keepouts/guarding where needed to maintain separation integrity.
Supply decoupling as a loop problem
- Decoupling is effective only when the loop is tight (cap placement + return point).
- Separate noisy loads from the receiver/reference nodes when possible.
Practical test & debug flow (to make results reproducible)
- Define pass criteria: no toggle / no latch / recovery time bound under a specified dv/dt waveform.
- Fix input state: test static-0, static-1, and toggling separately to find the worst sensitivity.
- Validate the loop: adjust return-path and reference points; observe event-rate changes to confirm injection path.
- Apply knobs: tighten decoupling loops and limit bandwidth; measure whether error probability drops.
- Record conditions: dv/dt shape, repetition, temperature, load, and event counters for lab-to-field alignment.
Data placeholders (fill with project targets)
CMTI target
≥ X kV/µs
EFT level
Y kV
Surge level
Z kV
No false pulse (optional)
glitch < N ns
Scope lock: this chapter focuses on isolator behavior and injection paths; compliance standard details should live in Safety & Compliance pages.
H2-6. Timing: Prop Delay, Skew, Jitter, and Determinism
Timing numbers only help when measurement definitions are consistent. This chapter standardizes the meaning and test conditions of tpd, skew, and (when relevant) jitter, with an industrial focus on determinism.
Measurement definition (the “one ruler” used for selection and acceptance)
- Edge definition: specify input and output thresholds (and whether rising/falling are measured separately).
- Load condition: define pull-up/pull-down, output current, and capacitive load so tpd is comparable.
- Supply & decoupling: record VDD1/VDD2 and local decoupling placement as part of the test condition.
- Temperature points: Tmin / room / Tmax; timing must be validated at corners, not only typical.
tpd (propagation delay): what matters for real systems
Why tpd is not only “smaller is better”
Industrial control needs bounded worst-case delay and predictable recovery, especially on shutdown or fault paths.
What to track
tpd_typ and tpd_max under aligned thresholds, loads, supplies, and temperature corners.
skew (channel-to-channel mismatch): the multi-channel trap
- Skew is often the real limiter in multi-channel interlocks and synchronized control.
- Track both static skew and Δskew over temperature; corners amplify mismatch.
- Shared supply noise can create correlated timing movement; treat power integrity as part of timing determinism.
jitter (only when the isolated signal is a clock / sync)
- For most industrial control links, determinism is dominated by tpd/skew rather than fs-class jitter.
- When isolating a clock/sync, define whether jitter is RMS or p-p, and whether it is additive.
- Ultra-low-jitter requirements should route to the dedicated low-jitter clock isolator page (link-only rule).
Bi-direction and mixed-direction pitfalls (what to sanity-check)
Direction asymmetry
Forward and reverse paths can have different tpd; budget both when using handshakes or tight synchronization.
Load & pull-up differences
Different pull-ups/cap loads can look like “device skew”; align loads before concluding mismatch.
Shared-supply coupling
Noise on a shared rail can move multiple channels together; treat PI as part of timing validation.
Corner amplification
Room-temp pass can fail at Tmin/Tmax; validate Δtpd/Δskew at corners for real acceptance.
Data placeholders (fill with acceptance targets)
Propagation delay
tpd ≤ X ns
Channel skew
skew ≤ Y ns
Temp drift (tpd)
Δtpd ≤ Xt ns
Temp drift (skew)
Δskew ≤ Ys ns
Jitter (if clock/sync)
≤ Z ps/fs
Scope lock: ultra-low-jitter clock isolation belongs to the dedicated clock isolator page; this page prioritizes timing determinism for industrial control.
H2-7. Power & Thermal Behavior (Especially at High Temp)
High-temperature instability often looks like a timing or CMTI problem, even when logic signals appear correct. The root cause is frequently a chain: power → junction temperature → margin shrink → threshold/delay drift → false decisions or intermittent faults.
Power breakdown (budgetable, not vague)
- Static current (Iq): baseline consumption that typically rises with temperature and supply conditions.
- Dynamic current: additional current that scales with data rate / toggle activity and output loading.
- Why it matters: at high ambient, small increases in Iq and activity can push Tj across a stability edge.
Supply noise becomes “pseudo timing” (how it turns into decision jitter)
- Receiver thresholds and decision windows are supply-referenced; VDD ripple can modulate effective thresholds.
- When thermal margin is thin, the same ripple produces larger error probability: glitches, edge wander, or rare toggles.
- Debug rule: correlate error events with VDD2 ripple and with toggle activity before blaming timing numbers.
Self-heating risks (multi-channel density and corner behavior)
Multi-channel concentration
- More channels + higher switching density concentrates dynamic power into localized hot spots.
- Hot spots amplify Δtpd and Δskew and thin decision margins under transient stress.
Corner amplification
- Room-temperature pass can fail at Tmax due to drift + ripple sensitivity.
- Track not only tpd/skew, but also event rate and recovery behavior at temperature corners.
Industrial cabinet reality (thermal environment is not “ambient”)
- Nearby heat sources (drivers, power stages) raise local board temperature well above cabinet air.
- Airflow uncertainty changes with cabinet layout; stability must be validated under worst-case flow.
- Copper & keepouts interact with both heat spreading and coupling; thermal fixes must not create cross-gap coupling paths.
Practical debug flow (separating heat vs noise vs activity)
- Fix the pattern: test static-0, static-1, and a fixed toggle rate to control dynamic current.
- Sweep temperature: compare event counts and timing drift at Tmin / room / Tmax.
- Sweep activity: reduce data rate/toggle density; if stability improves, dynamic power is implicated.
- Correlate ripple: measure VDD2 ripple and align it with event timestamps to validate the “pseudo timing” mechanism.
- Close the chain: confirm improvements by lowering Tj (thermal) and tightening ripple/loop (PI), not by guessing.
Data placeholders (fill with project targets)
Static current
Iq = X mA
Dynamic slope
ΔI/Mbps = Y
Junction limit
Tj ≤ N °C
VDD2 ripple (optional)
≤ R mVpp
Scope lock: isolated power topology details belong to the Isolated Power pages; this chapter focuses on isolator power/thermal effects on determinism.
H2-8. PCB Layout & Barrier Implementation (Do/Don’t)
A digital isolator only behaves as specified when the barrier is implemented correctly on the PCB. This chapter provides executable rules for partition, keepouts, return paths, and across-gap routing so cross-domain coupling does not steal CMTI and timing margin.
Partition rules (the non-negotiables)
- Primary and Secondary must be separate domains: independent reference planes and local return loops.
- No hidden return across the gap: do not allow signals to “borrow” a reference plane across the barrier.
- Keepout discipline: maintain a clean no-copper / no-test / no-bridge zone around the isolation gap.
Clearance & creepage: PCB reality (implementation, not standards text)
Distance is physical
- Use slots/keepouts to increase effective creepage where needed.
- Prevent solder mask bridges and silkscreen intrusion that reduce real creepage.
Environment effects
- Pollution, coating, and altitude can change the required distance margins.
- For full mappings and certificates, link to Safety & Compliance pages (link-only rule).
Routing discipline (across-gap coupling and CM emission control)
- Keep high dv/dt traces away from the barrier; avoid long parallel runs near the gap.
- Keep critical signals tightly paired with their local return paths inside each domain.
- Protect the secondary RX/reference region from noisy copper and from large loop areas.
Copper and test traps (the most common real-world mistakes)
Bad: copper near the gap
Copper facing across the gap increases coupling and can create an unintended CM injection path.
Bad: test points crossing domains
Probe ground clips and cross-domain test pads can force return currents across the barrier during debug.
Bad: silkscreen / mask bridging
Manufacturing artifacts can reduce creepage/clearance; treat these as distance stealers.
Good: clean keepout + local loops
A clean keepout and compact local return loops preserve both transient robustness and timing determinism.
Quick self-check (10 items, field-friendly)
- Primary/Secondary planes are clearly separated; no copper “bridges” in the keepout.
- No signal forces its return across the gap; return loops close locally.
- Slots/keepouts are implemented where needed to meet distance targets.
- No large copper plates face each other across the barrier near sensitive nodes.
- Secondary RX/reference region is away from noisy switching copper.
- Decoupling caps are placed for minimum loop area with correct return points.
- Test pads do not cross domains; measurement strategy avoids cross-gap ground clips.
- Silkscreen/mask do not intrude into creepage paths or create unintended bridges.
- Connector shield/chassis bonding does not create cross-domain coupling paths.
- After layout, re-check CMTI and timing under realistic stress waveforms.
Data placeholders (fill with target distances)
Clearance
≥ X mm
Creepage
≥ Y mm
Slot (optional)
width = S mm
Coating (optional)
thickness = T
Scope lock: standards mapping and certification details should live in Safety & Compliance pages; this chapter focuses on PCB execution rules.
H2-9. EMI/EMC: Barrier Capacitance, Edge Rate, and CM Emission
Magnetic/inductive isolators can still contribute to EMI because the isolation barrier has capacitance. Fast edges and high dv/dt drive common-mode current (iCM) through Cb, and the current then flows through chassis, cable harnesses, and return paths—creating both conducted and radiated emissions.
Mechanism (emission view, not immunity)
- Barrier capacitance (Cb) provides a cross-barrier common-mode path.
- Fast edges / dv/dt convert into iCM that flows through system-level loops.
- EMI outcome: loop area drives radiation; path impedance sets conducted current magnitude.
Where the current goes (map the loop before “fixing EMI”)
Loop segments
- Cb (inside the isolator)
- Chassis / shield (connector shell / PE)
- Harness (long cable = strong antenna)
- Return path (system ground / supply loop)
Fast diagnostics
- Emission changes strongly with cable length → harness dominates.
- Emission changes with chassis bond strategy → chassis loop dominates.
- Emission changes with edge-rate control → source spectrum dominates.
Knobs that work (source spectrum, not just “more filtering”)
Edge rate control
- Increase tR or reduce drive strength to lower high-frequency energy in iCM.
- Use a series resistor where SI allows to reduce di/dt and ringing.
Signal integrity trade
- Slower edges consume timing margin; verify against the timing budget (H2-6).
- Over-damping can distort waveforms and shift thresholds; validate at temperature corners.
Packaging / shielding options (if available)
- Lower Cb and shielded structures can reduce cross-barrier iCM coupling.
- Compare only under aligned dv/dt, loads, and the same loop geometry.
Y-cap coordination (do-not-trip rules)
- Use Y-caps to steer iCM to a controlled path, not to enlarge antenna loops.
- Respect leakage limits (medical/portable); detailed limits belong to Safety pages (link-only rule).
Data placeholders (fill with targets)
Barrier capacitance
Cb ≤ X pF
Edge rate target
tR ≥ Y ns
Series resistor (opt.)
Rs = N Ω
Emission delta (opt.)
Δ = M dB
Scope lock: this chapter focuses on emission mechanisms and knobs; transient output immunity behavior is covered in H2-5.
H2-10. Reliability & Validation: What to Measure and How to Prove It
Reliability is not a belief in datasheets. It is a set of repeatable tests with explicit pass/fail criteria, executed across stress, temperature corners, and long-run time, with logs and waveforms that make failures reproducible.
Pass criteria first (define what “proven” means)
- No false pulse: zero incorrect toggles under specified dv/dt and stress waveforms.
- No latch: zero stuck-state events; recovery must be bounded if a defined recovery mode exists.
- Correct default state: power-down / UVLO behavior must match the system safe-state definition.
- Event-rate limit: long-run false-event rate below the project threshold, at temperature corners.
Test matrix (what must be swept)
Corners
- Temperature: Tmin / room / Tmax
- Supplies: VDD1/VDD2 min / nom / max
- Load: pull-up/down, Cload, line length
- Pattern: static-0/1, fixed toggle, random
Stress groups
- CMTI dv/dt, EFT, Surge, ESD (system-level behavior)
- Temperature cycling, burn-in (drift and event-rate)
- Long-run monitoring (flip-rate, latch count, recovery)
- Ripple sweeps (prove “pseudo timing” sensitivity)
Failure definitions (triggerable and measurable)
False pulse
Any unexpected output transition; optionally threshold by glitch width > N ns.
Latch / stuck
Output remains frozen beyond a defined time T or requires reset/power-cycle to recover.
Default-state mismatch
Power-down/UVLO output state violates the system safe-state requirement.
Recovery bound
If recovery exists, it must complete within Tr and remain stable afterward.
Record everything needed to reproduce (logs + captures)
- Stress waveform parameters: dv/dt shape, repetition, EFT/Surge/ESD levels.
- Corner conditions: temperature, soak time, VDD1/VDD2, load configuration.
- Evidence: scope trigger captures and black-box logs with timestamps and event counters.
- Correlation: align event times with VDD ripple and input pattern state.
Data placeholders (fill with project acceptance numbers)
Flip-rate limit
≤ X / hour
Latch events
0
No false pulse proof
dv/dt = Y → Z min
Glitch threshold (opt.)
> N ns
Recovery bound (opt.)
Tr ≤ T
Scope lock: hi-pot/partial-discharge standards and certification workflows belong to Safety pages; this chapter focuses on system-level proof and evidence.
H2-11. Applications (Industrial Drives-First, No Protocol Deep-Dive)
This chapter explains where magnetic/inductive digital isolators are used and the engineering hooks that make them survive high dv/dt cabinets and wide-temperature operation—without diving into any interface protocol details.
Industrial Drives (control board ↔ power stage)
Typical isolation links are control-to-power commands and power-to-control fault/status returns. The key requirement is
no false switching under fast common-mode transients, across temperature.
Isolation link types (function-level)
- Control → Power: PWM / EN / MODE (few lines, deterministic behavior)
- Power → Control: FAULT / READY / OC-OT status (safe-state and diagnosable)
- Optional: sensor/status strobes (keep names generic to avoid protocol scope creep)
Failure signatures to watch (field-realistic)
- False pulse / momentary flip: an unexpected transition during dv/dt events
- Short “unknown window”: output becomes briefly indeterminate (glitch-width matters)
- Latch / stuck state: output freezes and needs reset/power-cycle to recover
- Thermal drift symptom: “looks logic OK” but system becomes unstable at high temp
Design hooks (actionable knobs)
- Fail-safe default: define power-down/UVLO output state (system-safe meaning)
- Edge control: series R / drive strength (reduce EMI + reduce mis-trigger risk)
- Partition & return path: no return across barrier gap; keep loops compact
- Validation gate: prove “no false pulse” under specified dv/dt and temperature corners
Example material numbers (drive control chain)
- Magnetic/inductive digital isolator (signal): Analog Devices ADuM1201 (2-ch) :contentReference, ADuM1401 (4-ch) :contentReference; NVE IL710 series (GMR-based) :contentReference
- Isolated gate driver (companion, link-out for details): Analog Devices ADuM4121 :contentReference
- Isolated bias (companion, link-out for topology): Analog Devices isoPower ADuM5020 :contentReference
Note: part numbers are examples only; verify insulation class/VIORM, package creepage/clearance, and temperature grade for the target standard.
PLC / Field I/O (low latency, diagnosable fail-safe)
Isolation is commonly used to break ground loops and survive burst/surge environments. The core requirement is predictable default states
and bounded event rates across temperature and supply variation.
Selection hooks (scope-safe)
- Default state: define High/Low/Hi-Z behavior under UVLO and power-down
- Input floating handling: ensure deterministic states with biasing strategy (no protocol logic)
- Noise margin: prioritize hysteresis and robust edge behavior for cabinet wiring realities
Example material numbers (field I/O companion chain)
- Magnetic/inductive digital isolator: ADI ADuM1201 :contentReference / ADuM1401 :contentReference; NVE IL710 :contentReference
- RS-485 transceiver (non-isolated, interface page for details): TI SN65HVD75 :contentReference
- CAN transceiver (non-isolated, interface page for details): TI TCAN1051 family :contentReference/li>
High-noise cabinets (harness + chassis coupling)
In real cabinets, emissions and false-trigger risks often correlate with cable length, chassis bonding, and return-path geometry.
The fastest way to stabilize behavior is to control the loop and validate under realistic stress.
Practical hooks
- Loop control first: keep CM current loop area small; avoid accidental cross-gap returns
- Edge shaping: series R where SI allows; reduce ringing and high-frequency energy
- Evidence-driven debug: triggered scope captures + event counters to reproduce flips/latch
Application target placeholders (fill per project)
dv/dt target
dv/dt ≥ X kV/µs
Temperature corner
Tmax = Y °C
Reliability goal
MTBF ≥ N hours
Proof gate
no false pulse @ X for Z min
Scope lock: interface protocol electrical details belong to the “Isolated Interfaces” cluster; isolated power topology belongs to “Isolated Power (DC-DC & Bias)”.
H2-12. IC Selection Logic & Quick Pairings (This Page Only)
Selection is a five-step gate: insulation target → CMTI/dv/dt → timing budget → channels/default state → power/package/Cb. Quick pairings provide minimum viable combinations using concrete material numbers, without expanding into power topology or interface deep-dive.
Five-step selection order (do not reorder)
Step 1 — Insulation target
Gate on basic/reinforced, working voltage (VIORM), and package creepage/clearance.
Step 2 — CMTI / dv/dt goal
Gate on “no false pulse / no latch” under the specified dv/dt stress, not just a headline number.
Step 3 — Timing budget
Gate on tpd and skew under aligned conditions (edge definition, load, temperature points).
Step 4 — Channels / direction / default state
Gate on Nch, direction mix, and UVLO/power-down defaults that match the system safe-state.
Step 5 — Power / temp / package distance + Cb
Gate on high-temp power behavior, package spacing reality, and Cb impact on common-mode emission.
CMTI
≥ X kV/µs
tpd
≤ Y ns
skew
≤ Z ns
Cb
≤ N pF
Quick Pairings (minimum viable combos, concrete BOM)
Pairing A — Industrial drive control
Use when: PWM/EN/FAULT must remain deterministic under dv/dt and wide temperature.
- Signal isolation: ADI ADuM1401 :contentReference (4-ch) or ADI ADuM1201 :contentReference (2-ch); NVE IL710 :contentReference
- Gate-drive isolation: ADI ADuM4121 :contentReference
- Isolated bias (if a small isolated rail is needed): ADI ADuM5020 :contentReference
Pairing B — Field I/O (RS-485 / CAN style chains, no protocol deep-dive)
Use when: cabinet wiring and ground shifts require isolation + robust transceiver behavior.
- Signal isolation: ADI ADuM1201 :contentReference} / ADuM1401 :contentReference; NVE IL710 :contentReference
- RS-485 transceiver (non-isolated): TI SN65HVD75 :contentReference
- CAN transceiver (non-isolated): TI TCAN1051 family :contentReference
Pairing C — Noisy cabinet / long harness stabilization
Use when: link flips correlate with cable/harness changes or chassis bonding strategy.
- Isolator (signal): ADI ADuM1401 :contentReference or NVE IL710 :contentReference
- Edge control (passive, example value placeholder): series resistor Rs = N Ω at the victim net (verify timing margin)
- Proof gate: dv/dt = X → no false pulse over Z minutes + latch events = 0
Scope lock: these pairings list concrete material numbers as examples; detailed interface requirements and power topology design remain link-only to the corresponding cluster pages.
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H2-13. FAQs (Field Debug & Acceptance Criteria)
Scope: close out long-tail field debugging and acceptance criteria only. No new domains, no protocol deep-dive, no power-topology expansion. Each answer uses the same 4-line structure: Likely cause / Quick check / Fix / Pass criteria (X/Y/N placeholders).
Project threshold template (fill once, reuse everywhere)
X (stress)
dv/dt = X kV/µs · EFT = X kV · Temp = X °C
Y (duration)
run time = Y minutes/hours · cycles = Y
N (event limit)
false pulses ≤ N · latch events = 0 · flip rate ≤ N/hour
Counting rule recommendation: define a “false pulse” as width > N ns (or per system sensitivity).
▸ CMTI is high on the datasheet, but rare field flips still happen—check coupling path or default state first?
Likely cause: System CM injection loop (barrier capacitance → chassis/cable return) or floating/undefined input/default behavior masquerading as flips.
Quick check: Trigger-capture the “flip” while logging event count; force input to a hard 0/1 and repeat under the same dv/dt to separate coupling vs default-state issues.
Fix: Shrink CM loop (partition/return control), add edge shaping (series R where margin allows), define input bias and power-down/UVLO default explicitly.
Pass criteria: At dv/dt = X kV/µs, no false pulse (>N ns) over Y minutes; latch events = 0; flip rate ≤ N/hour.
▸ Unstable only at high temperature—suspect tpd drift or supply noise/self-heating first?
Likely cause: Timing margin eaten by tpd/skew drift at Tmax, or supply ripple/self-heating shifting thresholds and decision stability (“pseudo timing failure”).
Quick check: At room vs Tmax, measure tpd/skew under the same load/edge definition; in parallel measure VDD ripple and junction proxy (package temp) during worst-case activity.
Fix: Re-budget timing margin (tpd/skew), reduce ripple at the isolator pins (local decoupling + return hygiene), reduce toggling density or edge strength if thermal headroom is tight.
Pass criteria: At T = X °C for Y hours, tpd ≤ X ns and skew ≤ X ns (project budget); false pulses ≤ N; latch events = 0.
▸ EFT hit causes latch/stuck output—ground bounce/threshold error or reset policy?
Likely cause: EFT-induced ground bounce or supply dip drives a mis-decision window; recovery logic/default handling may not return to a safe deterministic state.
Quick check: Capture VDD + input + output around the EFT event with a consistent reference; compare “same EFT, input forced stable” vs “input floating/active” behavior.
Fix: Harden local supply at the isolator pins, tighten return paths, define a deterministic reset/default behavior at brownout/UVLO, and avoid inputs left floating during stress.
Pass criteria: EFT = X kV, Y bursts: latch events = 0; if recovery is allowed, recovery time ≤ N ms and no false pulse (>N ns).
▸ Only one channel fails in a multi-channel device—check skew or cross-gap routing/crosstalk?
Likely cause: Layout-specific coupling (one net closest to noisy return or crosses the barrier keep-out) or direction/load differences making that channel’s decision margin smaller (apparent “skew issue”).
Quick check: Swap the failing channel’s source/receiver to a known-good channel (same stimulus, same load); measure skew simultaneously under the same edge definition.
Fix: Re-route to respect barrier keep-out, add separation/guarding, equalize loads/edge shaping across channels, and reserve the tightest timing channel for the cleanest net.
Pass criteria: Under dv/dt = X and max activity, failing-channel event count ≤ N over Y minutes; skew ≤ X ns (project gate).
▸ EMI got worse after changing package—barrier capacitance or edge rate first?
Likely cause: Higher effective barrier capacitance increases CM current, or stronger/faster edges raise high-frequency energy even if Cb is similar.
Quick check: Keep layout/loads unchanged; add a controlled series R at the noisiest output and re-measure EMI. Large improvement suggests edge-dominated; small change suggests Cb/loop-dominated.
Fix: Edge-shape where timing allows, reduce CM loop area (chassis/return management), and prefer package options that support the required creepage/clearance without unintended coupling.
Pass criteria: EMI meets project limit at X conditions; CM-related false pulses ≤ N over Y minutes; functional timing margin remains ≥ X%.
▸ dv/dt test “passes,” but long-run field flip rate is still high—what is the first accounting check?
Likely cause: Test waveform/fixture differs from field CM loop reality, or event counting is inconsistent (pulse width threshold/denominator mismatch).
Quick check: Normalize the metric: define false pulse width threshold (>N ns) and observation window Y; reproduce with a fixture that matches field return-path geometry.
Fix: Align stress definition to field dv/dt and loop, add triggered captures + counters, then apply the smallest effective knob (edge shaping, return control, bias/default tightening).
Pass criteria: With the field-matched setup at dv/dt = X, false pulses ≤ N over Y hours; latch events = 0; flip rate ≤ N/hour.
▸ Adding series R reduces EMI, but timing starts failing—what should be adjusted first?
Likely cause: Edge shaping increased rise/fall time enough to violate the receiving threshold/window, or increased delay/skew beyond the allocated margin.
Quick check: Measure tpd/skew before/after series R under the same load; verify logic threshold crossing timing at the receiver input (not only at the driver pin).
Fix: Reduce R to the minimum that still improves EMI, move shaping closer to the aggressor, or reassign the tightest-timing net to the cleanest/shortest route.
Pass criteria: EMI meets limit and tpd ≤ X ns, skew ≤ X ns; no false pulse (>N ns) over Y minutes at dv/dt = X.
▸ Output “safe state” is not what the system expects during brownout—where is the first fix?
Likely cause: UVLO/power-down default state is undefined for the system, or external biasing allows inputs to float into ambiguous thresholds during supply ramps.
Quick check: Ramp VDD slowly and capture output state vs VDD; repeat with inputs forced (strong pull-up/down) to isolate “default state” vs “input floating” behavior.
Fix: Define deterministic defaults (external bias if needed), enforce input state during ramps, and ensure reset policy matches the required system-safe meaning.
Pass criteria: For VDD ramps and dips at X profile, output stays in the defined safe state for Y cycles; unintended transitions ≤ N; latch events = 0.
▸ Same DUT, different labs give different results—first align dv/dt definition or fixture return path?
Likely cause: Different dv/dt waveform definition (edge rate, reference points) and different fixture/chassis return geometry dominate the outcome.
Quick check: Record dv/dt waveform at the same reference nodes in both labs; document fixture bonding and cable routing; compare event counting rules (width threshold, window).
Fix: Standardize the stress spec and fixture return geometry; reuse the same counting rule and reporting template for flips/latch and recovery behavior.
Pass criteria: Under the standardized dv/dt = X and fixture, results match within N events over Y runs; latch events = 0.
▸ “Scope looks clean,” but flips still occur—what is the first measurement sanity check?
Likely cause: Probe reference/ground lead injects or hides the real transient; observation point is not the victim threshold node (receiver-side sees different waveform).
Quick check: Re-measure at the receiver pin with short ground/appropriate probing; use trigger on event counter to capture the exact pre-flip window.
Fix: Move observation to victim nodes, tighten probing method, then apply loop/edge/default fixes only after the event is reproducible and measured correctly.
Pass criteria: With validated measurement method, false pulses (>N ns) = 0 over Y minutes at dv/dt = X; latch events = 0.
▸ Passed once, but later becomes “more fragile”—what is the fastest degradation check?
Likely cause: Marginal loop/EMI/thermal condition that drifts over time; fixture/cable/bonding changes alter CM loop, raising event rate even if “pass” was once achieved.
Quick check: Run a long observation with fixed stress (dv/dt/temp), log event rate per hour, and compare “before/after” on a single controlled change (bonding or edge shaping).
Fix: Lock down bonding/return geometry, reduce high-frequency energy (edge shaping), and add a production validation gate (stress + long-run logging).
Pass criteria: Over Y hours at X stress, event rate ≤ N/hour; latch events = 0; acceptance report includes waveform + counter logs.
▸ Errors appear only when cabinet door is open—shield continuity or chassis bonding first?
Likely cause: Chassis bonding/return path changes with door state, reshaping the CM loop and increasing injection into the isolator threshold nodes.
Quick check: Correlate event rate with door states; temporarily enforce a controlled bonding path and repeat the same dv/dt activity to see if events collapse.
Fix: Make bonding/return path deterministic (mechanically and electrically), reduce loop area near the barrier, and apply edge shaping where timing allows.
Pass criteria: For both door states over Y minutes at X stress, false pulses ≤ N and latch events = 0; results are repeatable across Y toggles.
Scope lock: FAQs only close out field debug and acceptance criteria for magnetic/inductive digital isolators.
Interface protocol details and isolated power topology remain out of scope for this page.
