Context — why this stack is hard

Motor inverters combine extreme dv/dt at the switching node with high fault energy; the isolation stack must keep sensing truthful while making protection deterministic.

• dv/dt injection couples through parasitics and the isolation barrier, creating false triggers, false measurements, or logic upset.
• Fault events (short-circuit / desaturation / shoot-through) compress time budgets; microseconds decide device survival.
• Co-design requirement: isolated gate driver, isolated ΔΣ modulator, and small isolated bias must be treated as one coupled system.

Boundary — what is included / excluded

This page focuses on the three-piece isolation stack used in motor inverters: isolated gate drive + isolated ΔΣ sensing + small isolated bias, with system-level constraints on dv/dt immunity, timing determinism, layout partitioning, and verification gates.

System map — domains, barriers, and critical signals

The isolation barrier splits control from high-voltage domains; dv/dt at the switching node can inject into both drive and sensing unless return paths and bias distribution are engineered as one system.

Intent — make barrier placement a decision, not a habit

Isolation barriers can be centered on drive, sensing, or power. Each placement changes the trade-offs across noise coupling, timing determinism, EMI, and safety evidence.

• Noise: which parasitic path dominates (barrier capacitance, return-path shortcuts, bias ripple coupling).
• Timing: propagation delay / skew / filter latency stack-up and its effect on protection windows.
• EMI: common-mode currents and where they close the loop.
• Compliance: which component becomes the “hard gate” for creepage/clearance and insulation rating.

Key decisions — three questions with engineering meaning

1. Single barrier vs multi-barrier: should fault paths and measurement paths be separated to reduce single-point failure impact?
2. Modulator on high-side vs front-end on high-side: can dv/dt-induced input recovery and bitstream integrity be bounded with testable criteria?
3. Per-phase bias vs shared isolated bias: does a single rail disturbance propagate across phases, or can faults be contained?

Architecture options — stacked for mobile

Diagram — three barrier placements at a glance

The same functional blocks appear in each option. The only changes are the barrier position and the dominant coupling/timing risks.

Budget card — turn specs into pass/fail budgets

In motor inverters, specifications matter only when they close a failure loop: dv/dt injection can corrupt drive or sensing, and timing drift can break protection determinism. Budgets below use placeholders (X/Y/N) to be replaced with project limits.

Trade-off card — faster edges always move another limit

• Faster switching increases dv/dt stress and shifts risk into CMTI/Ciso coupling and EMI.
• Heavier filtering cleans measurement outputs but adds latency that can narrow protection time windows.
• Lower Ciso reduces injection but still requires controlled return paths; layout must enforce where CM currents close.

Selection logic — a 7-step executable flow

Gate-driver selection must bind together switch behavior (Qg and dv/dt), bias headroom, protection policy, insulation rating, and layout hooks so the system stays deterministic under stress.

Protection features — place each feature on the fault timeline

• DESAT: detects abnormal VCE/VDS rise; blanking must prevent dv/dt-induced false trips while still catching real shorts.
• Miller clamp: prevents dv/dt-driven false turn-on; effectiveness depends on gate loop geometry and Kelvin referencing.
• Soft turn-off: shapes current/voltage stress during faults; ties directly to bias capability and drive strength.
• UVLO: defines safe behavior during bias dips; must avoid chatter and guarantee a known off-state.

Signal chain card — what each stage does and what can fail under dv/dt

A truthful sensing chain must remain stable under switching dv/dt and fault stress. Each stage below is defined by its role, its dominant dv/dt failure mode, and a verification hook.

Filter & latency card — budgets that must be owned (placeholders)

Filtering creates latency. Protection timing must budget the end-to-end sensing delay and its worst-case drift.

• Total sensing latency ≤ X (placeholder) from physical signal change to estimator output.
• Worst-case latency drift ≤ Y (placeholder) across voltage/temperature and switching stress.
• Bitstream burst tolerance: allowable error rate ≤ X/Y window (placeholder); beyond that, protection must enter a defined safe policy.

Requirements card — define bias as an engineering contract

Small isolated bias rails are the stability base for both driver and sensing domains. Requirements below turn “a bias supply” into measurable acceptance criteria using placeholders (X/Y/N).

Architecture card — independent vs shared bias, module vs transformer driver

Interference paths card — four coupling paths with executable closure

The isolation stack behaves as a coupled system: dv/dt, barrier parasitics, bias dynamics, and return paths can corrupt sensing, destabilize gating, or trigger non-deterministic protection. Each path below closes with Cause → Symptom → Fix → Pass criteria.

Budget card — unify all delays into one executable timing contract

Determinism requires owning worst-case delay addition across drive, switching response, and sensing/filter latency. The total budget must protect dead-time margin and the protection window under stress.

Alignment card — PWM edges, sampling windows, and protection windows

• Sampling alignment: sample windows must avoid the most violent dv/dt region; alignment error ≤ X (placeholder).
• Protection window: decision time jitter must be bounded; timing jitter ≤ Y (placeholder).
• Cross-phase determinism: mismatch across phases must not break consistent gating and protection; Δphase ≤ N (placeholder).

Scope guard — layout rules that directly control the isolation stack

This section focuses only on layout and EMC behaviors that directly impact the isolated gate driver, isolated ΔΣ modulator chain, and small isolated bias: partition discipline, return closure, creepage/clearance geometry, hot-loop containment, and controlled Y-cap usage.

Evidence chain — three gates that convert a design into cert-ready production

The goal is an evidence chain, not a standards encyclopedia. The gates below define what must be proven, what artifacts must be collected, and what acceptance placeholders (X/Y/N) should be owned.

Milestone strip — what each gate must lock

Design Gate (6–10 checks)

Goal: eliminate coupling paths on paper, own creepage geometry, and define the timing/power contracts before bring-up.

• Partition domains and mark the isolation boundary (HV hot / Drive / Sense / Control)

  Evidence: annotated PCB partition snapshot; Pass: cross-gap copper violations = 0 (N=0 placeholder).

  Gate driver (iso) TI UCC21750 ADI ADuM4135 Infineon 1EDC20I12MH

• Define “no cross-gap return” rules and prohibited items (gap-bridge blockers)

  Evidence: DRC/review checklist items; Pass: prohibited structures count = 0 (N=0 placeholder).

  ΔΣ mod (iso) TI AMC1306 TI AMC1336 ADI AD7403

• Minimize gate-drive hot loop area and enforce Kelvin return routing

  Evidence: hot-loop highlighted layout; Pass: loop length/area ≤ X (placeholder), no parallel run beside dv/dt corridor.

  Driver support Bourns CDSOT23-SM712 Würth 744231091 TDK ACM series

• Define a timing contract (delay, skew, and total latency budget) with placeholders

  Evidence: Δt_total budget card; Pass: dead-time margin ≥ X, skew ≤ Y, protection latency ≤ N (placeholders).

  Clock / sync (if needed) TI ISO7741 ADI iCoupler iso series Silicon Labs Si86xx

• Define isolated bias contract (rails, no-load loss, startup, UVLO headroom)

  Evidence: bias contract card; Pass: Vbias_min > UVLO + X V; no-load loss ≤ Y (placeholders).

  Isolated bias options Murata MGJ2D051505SC RECOM R15P215S TI SN6505B

• Own creepage/clearance geometry (slots, keep-outs, guard structures) as a signed constraint

  Evidence: creepage map + drawings; Pass: minimum creepage/clearance meets target class (X/Y placeholders).

  Barrier-rated packages UCC21750 (DWK) ADuM4135 AMC1336

• Decide Y-cap usage as a deliberate common-mode path (not an EMI patch)

  Evidence: decision record (value/placement/target); Pass: emissions gain ≥ X while bitstream/UVLO remain deterministic (placeholders).

  Safety Y-cap examples KEMET R46 TDK/EPCOS B3202x Murata DE2 series

Bring-up Gate (6–10 checks)

Goal: reproduce worst-case dv/dt and fault stress, then backfill measured delay/latency evidence into the budgets.

• Lock reproducible dv/dt stress conditions (X kV/µs at Y conditions)

  Evidence: scope captures with trigger definition; Pass: dv/dt ≥ X kV/µs at Y conditions (placeholders).

  Gate driver under test TI UCC21750 ADI ADuM4135 Infineon 1EDC20I12MH

• Validate ΔΣ bitstream integrity under dv/dt stress (burst / missing pulses / jitter)

  Evidence: bitstream statistics (windowed); Pass: burst rate ≤ X/Y window; missing pulses = ≤ N (placeholders).

  ΔΣ mod under test TI AMC1306 TI AMC1336 ADI AD7403

• Prove bias rail headroom and eliminate UVLO chatter during switching and fault events

  Evidence: rail dip capture + UVLO event counters; Pass: UVLO events ≤ N; dip amplitude ≤ X V and duration ≤ Y µs (placeholders).

  Isolated bias under test Murata MGJ2D051505SC RECOM R15P215S TI SN6505B

• Measure and record drive delay and channel skew (PWM → driver output)

  Evidence: timing captures + worst-case summary; Pass: delay ≤ X ns, skew ≤ Y ns (placeholders).

  Reference isolators (if separate) TI ISO7721 Silicon Labs Si8641 ADI ADuM110N

• Measure and record sensing latency (physical current change → filter output)

  Evidence: aligned waveforms; Pass: Δt_sense ≤ X and drift ≤ Y across corners (placeholders).

  ΔΣ chain examples AMC1306 + SINC AD7403 + decimator AMC1336

• Enable protection (DESAT/SC) with fault injection; verify latch/clear policy and recovery determinism

  Evidence: fault injection logs; Pass: false trip ≤ N, recovery success ≥ X%, retry ≤ N with interval ≥ X ms (placeholders).

  Drivers with protection TI UCC21750 Infineon 1EDC20I12MH Silicon Labs Si8239

Production Gate (6–10 checks)

Goal: freeze what matters, define change triggers, and run sampling tests that prevent silent regressions.

• Freeze BOM and define substitution triggers that mandate dv/dt + timing re-test

  Evidence: change-control rule; Pass: any change to isolator/driver/bias module triggers Gate-2 regression (rule must be enforced).

  Parts that must trigger re-test UCC21750 ADuM4135 AMC1306 MGJ2D051505SC

• Run dv/dt and timing regression on each ECO (minimal but sufficient suite)

  Evidence: regression report; Pass: dv/dt ≥ X, skew ≤ Y, Δt_total within N (placeholders).

  Regression anchors dv/dt condition card delay/skew capture bitstream stats

• Define production sampling tests (hi-pot; partial discharge if applicable)

  Evidence: sampling plan; Pass: failures ≤ N per Y units (placeholders); documentation stored for audit.

  Evidence artifacts Hi-pot record PD record unit trace

• Zero-tolerance events: UVLO chatter, bitstream corruption during defined stress

  Evidence: event counter snapshot; Pass: UVLO chatter = 0; bitstream missing pulses ≤ N (placeholders).

  Monitored blocks UCC21750 UVLO AMC1306 bitstream MGJ2 bias rail

• Lock compliance evidence pack (CTI/materials/CB report) and datasheet clause mapping

  Evidence: audit-ready pack; Pass: missing items = 0 (N=0 placeholder).

  Barrier evidence references UCC21750 datasheet ADuM4135 datasheet AMC1336 datasheet

Part-number note (usage boundary)

Listed part numbers are example anchors for checklists and change-control triggers. Use local qualification rules to decide equivalents, but treat any isolator/driver/bias substitution as a mandatory dv/dt + timing regression event.