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Power & Thermal Budgeting for Isolation: No-Load Loss and Qg Heat

← Back to: Digital Isolators & Isolated Power

Power and thermal limits are the real bottleneck in isolation systems: no-load loss, bias efficiency, and gate-driver dissipation decide temperature rise and reliability margin. This page provides a repeatable way to budget losses, predict ΔT, validate measurements, and select parts without overdesign.

Scope & Center Thesis

No-load loss Bias efficiency Qg·Vg·f driver heat Thermal rise Selection margin

Power and thermal limits are the hidden bottleneck in isolation systems: no-load loss, bias efficiency, and gate-driver dissipation often decide temperature rise, reliability, and compliance margin.

This page provides a repeatable way to budget losses, predict temperature, validate measurements, and pick parts without overdesign.

In scope (must be fully covered)

  • Bias efficiency / light-load / no-load loss: where it comes from, how to quantify it, system impact, and practical loss-reduction knobs (principle level).
  • Gate-driver dissipation vs Qg: core model, sensitive variables, tuning knobs, and typical thermal runaway paths in fast switching systems.
  • Thermal: resistance-chain thinking, heat paths, PCB-level thermal techniques that respect the isolation boundary, and validation/production gates.
  • Selection logic: how to pick isolators / isolated drivers / isolated power when temperature rise or standby power is the primary constraint.

Out of scope (mention only as a link)

  • Isolated power topology implementations (Flyback / Push-Pull / Half-Bridge / etc.) → link to Isolated Power.
  • Driver protection deep-dive (DESAT, short-circuit strategy, Miller clamp tuning) → link to Gate Drivers.
  • Regulation clauses and standard-by-standard interpretation (VDE/UL/IEC text walkthrough) → link to Safety & Compliance.

Deliverables (what this page enables)

Budget template

A loss-tree structure that separates constant, load-dependent, and frequency-dependent terms.

Driver loss floor

A Qg-based lower bound that converts switching targets into a realistic thermal requirement.

Thermal path plan

A partition-safe heat-flow approach that does not violate the isolation boundary or creepage/clearance intent.

Validation gates

Measurement checkpoints that prevent false “passes” caused by light-load mode behavior or unstable windows.

Scope Map for Isolation Power & Thermal Three major domains—Bias loss, Driver loss, Thermal rise—feed a margin and selection outcome. Sibling-page details remain linked but not expanded. Scope Map: Power & Thermal in Isolation Systems Bias loss No-load loss Light-load efficiency Standby power Driver loss Qg·Vg·f Shoot-through Quiescent + bias Thermal rise Rθ path Hotspot mapping Airflow & copper Output: Temp margin & selection decisions Budget (constant/load/freq) Validate (stable windows) Linked details only Isolated Power Gate Drivers Safety & Compliance
Scope map: three domains (bias loss, driver loss, thermal rise) feed temperature margin and selection—implementation details remain in sibling pages.

Spec Glossary (Power & Thermal Terms)

Power and thermal decisions fail most often due to mismatched definitions: different operating states, unstable measurement windows, and datasheet conditions that do not match real duty cycles. The terms below standardize what each metric means, why it matters, and the most common trap.

Power terms

No-load loss
Definition: Input power consumed at zero output load in the steady operating mode.
Why it matters: Sets standby heat and battery drain even when “nothing is happening.”
Typical trap: Reading power before burst/skip mode settles; unstable windows inflate results.
Light-load efficiency
Definition: Efficiency in the operating band where output is small but nonzero (idle/keep-alive).
Why it matters: Dominates average heat in systems that spend most time at idle.
Typical trap: Using peak efficiency to estimate average dissipation; idle dominates in reality.
Standby power
Definition: Total system input power in “ready but inactive” state (incl. bias rails and keep-alives).
Why it matters: Drives enclosure temperature rise and compliance margin in long-duration operation.
Typical trap: Omitting auxiliary rails (LDOs, sensors, pull-ups) from the standby budget.
Iq / housekeeping current
Definition: Bias current drawn to keep control blocks alive (regulators, references, logic).
Why it matters: A constant loss term that becomes dominant at low output power.
Typical trap: Comparing Iq numbers across different VIN/VOUT and mode settings.
Pout / Pin (measurement pairing)
Definition: Output power and input power measured over the same stable time window.
Why it matters: Enables meaningful efficiency and dissipation numbers.
Typical trap: Mixing averaged Pin with instantaneous Pout (or different sampling windows).

Driver terms

Qg (gate charge)
Definition: Charge required to move the gate from off to on under defined VDS/IDS conditions.
Why it matters: Sets a hard lower bound on per-cycle gate energy.
Typical trap: Using Qg at a different Vg/VDS than the real operating point.
Vg (gate drive voltage)
Definition: Driver output swing that charges/discharges the gate each cycle.
Why it matters: Gate energy scales with Vg; lowering Vg often reduces driver heat.
Typical trap: Lowering Vg without re-checking switching loss/EMI side effects.
fsw (switching frequency)
Definition: Effective switching events per second for the driven device.
Why it matters: Gate-drive power rises linearly with switching rate.
Typical trap: Ignoring burst/PWM patterns that increase effective event count.
Rdriver / output stage loss
Definition: Conduction loss inside the driver during charge/discharge pulses.
Why it matters: Converts peak gate currents into junction heating, especially at high Qg.
Typical trap: Estimating only Qg·Vg·f and forgetting output-stage pulse dissipation.
Shoot-through (driver overlap)
Definition: Internal overlap current when high/low devices in the driver stage conduct simultaneously.
Why it matters: Adds a frequency-dependent heat component that worsens at fast edges.
Typical trap: Assuming overlap is negligible; it can dominate in small packages at high fsw.

Thermal terms

RθJA (junction-to-ambient)
Definition: Effective thermal resistance from silicon junction to ambient under stated PCB/airflow conditions.
Why it matters: Converts dissipation into temperature rise for first-order margin checks.
Typical trap: Using datasheet RθJA without matching board copper and airflow.
RθJC / ψJB (package paths)
Definition: Junction-to-case (RθJC) and board-coupling indicators (ψJB) that describe where heat flows.
Why it matters: Guides whether copper, vias, or case conduction matters most.
Typical trap: Treating ψ values as resistances; they are correlation parameters, not design constants.
ΔT (temperature rise)
Definition: Hotspot temperature minus ambient temperature for a defined steady-state condition.
Why it matters: Directly ties to reliability derating and compliance headroom.
Typical trap: Reporting peak transient temperature instead of steady-state with a stability criterion.
Hotspot
Definition: The location with maximum temperature, often not the largest component by size.
Why it matters: Reliability is set by the hottest point, not by the average board temperature.
Typical trap: Measuring a convenient surface point and missing the true hotspot region.
Derating curve
Definition: Allowed operating limit vs temperature (current, switching rate, duty, or output power).
Why it matters: Converts thermal estimates into safe operating rules for the product.
Typical trap: Using a curve without specifying airflow and enclosure conditions.
Metric-to-Decision Map Common power and thermal metrics map to system impacts and to practical design knobs and validation checks. Metric → Impact → Knob / Check Metric System impact Knob / check No-load loss Pin @ steady mode Standby heat Battery drain Enable gating Stable window check Light-load η Idle operating band Average dissipation Enclosure ΔT Weighted profile Idle-first tuning Qg·Vg·f Driver loss floor Driver heating Thermal margin Reduce Vg or fsw Verify edge trade-offs Rθ + airflow Board conditions ΔT prediction Derating rules Copper + vias plan Hotspot mapping
Metric-to-decision map: each metric is tied to a system impact and to a concrete knob or validation check.

System Power Tree (From Input to Heat Sources)

Isolation-system heat is rarely concentrated in a single block. A usable budget starts by mapping losses into a power tree: primary-side supply overhead, barrier-related dynamic costs, and secondary-side bias/driver/sensing loads. Each branch is then tagged as Constant, Load-dependent, or Frequency-dependent, so the correct tuning knob becomes obvious.

What this section delivers

Loss-map clarity

A complete view of where power is consumed across primary, barrier, and secondary partitions.

Loss type tags

A consistent classification that separates always-on costs from load- and event-driven costs.

Budget fields

A budget template with fields only (no numbers) for repeatable design and review.

Measurement anchors

Where each branch is verified (Pin, Vbias rails, driver supply, hotspot points).

Power-tree decomposition (principle level)

  • Primary side: controller/isolator supply overhead (often constant-dominant).
  • Barrier coupling: dynamic current and internal refresh cost (event/frequency-dominant).
  • Secondary side: isolated bias DC-DC + LDO + gate driver + sensing front-end (mixed types).

Loss type tags (how to think)

Constant

Stays near-fixed in a given state (e.g., housekeeping, static supplies). Dominates at light load.

Load-dependent

Scales with output current or rail load (e.g., LDO drop loss, secondary loads).

Frequency-dependent

Scales with switching or event count (e.g., Qg·Vg·f, data activity, barrier dynamics).

Budget template (fields only, mobile-safe)

Primary side

P_primary_ctrl (controller supply)

Type: Constant

Depends on: VIN, mode/state, temperature

Measured at: input Pin (state-stable window)

P_iso_primary (isolator VDD)

Type: Constant + Frequency

Depends on: channel count, toggle rate, VDD

Measured at: isolator rail (VDD × IDD)

Barrier coupling

P_barrier_dynamic (dynamic coupling)

Type: Frequency

Depends on: dv/dt, edge rate, switching events

Measured at: incremental Pin vs event rate (steady windows)

P_refresh (internal refresh/encode)

Type: Frequency

Depends on: activity factor, channel direction mix

Measured at: isolator rails under defined toggle profiles

Secondary side

P_bias_dcdc (isolated bias DC-DC)

Type: Constant + Load

Depends on: no-load mode, load profile, VIN/VOUT

Measured at: secondary rail Pin/Pout pairing

P_LDO (post-regulation drop loss)

Type: Load

Depends on: (Vin−Vout), rail current

Measured at: LDO (ΔV × I) or thermal rise correlation

P_driver (gate driver supply)

Type: Frequency + Load

Depends on: Qg, Vg, fsw, output-stage pulses

Measured at: driver rail (VDD × IDD) + hotspot

P_sense (sensing front-end)

Type: Constant or Frequency

Depends on: sampling rate, channel enable, bias rails

Measured at: front-end rails per state

How to use this tree (fast workflow)

  1. Fill the tree by block: Primary → Barrier → Secondary.
  2. Tag each field as Constant / Load / Frequency to reveal the correct knob.
  3. Identify the top two contributors in the target state and prioritize them for deeper chapters (no-load, Qg model, thermal path).
Isolation System Power Tree Power is decomposed across primary side, barrier coupling, and secondary side branches. Each branch is tagged as Constant, Load-dependent, or Frequency-dependent to guide tuning and validation. Isolation Power Tree: Input → Heat Sources C Constant L Load F Frequency/events Measure Pin / rails / hotspot Input Pin Primary side Controller supply C Isolator VDD C F Barrier coupling Dynamic current F Internal refresh F Secondary side Bias DC-DC C L Post LDO L Gate driver F L Sensing front-end C F Measurement anchors Pin (steady) Rails (V×I) Driver VDD Hotspot T
Isolation power tree: primary, barrier, and secondary branches tagged by loss type (C/L/F) to guide budgeting and tuning.

No-Load Loss (The Most Overlooked Heat Source)

Many isolation systems run hot even with near-zero load because no-load and light-load behavior dominates average dissipation. The root cause is usually a mix of housekeeping, minimum-energy maintenance, and light-load control modes that change ripple, emissions, and temperature rise.

Problem (symptoms)

  • Standby is hot: enclosure and hotspot temperatures rise with “no workload.”
  • Standby power fails: measured Pin exceeds the standby budget.
  • Light-load ripple grows: burst/skip behavior increases low-frequency ripple.
  • Mode jumps: power and noise change abruptly across operating states.

Cause (principle-level anatomy)

  • Housekeeping: controller bias, references, internal drivers (constant-heavy).
  • Magnetizing / maintenance: energy needed to keep regulation alive (state-dependent).
  • SR / minimum-load needs: behavior changes near zero load (load-sensitive).
  • Burst / skip modes: event clustering increases ripple and can stress EMI margin.

Knobs (principle-level, with trade-offs)

State-based enabling (sleep/idle/active)

Helps: removes constant losses in inactive states.

Hurts: wake latency and sequencing complexity.

Use when: standby time dominates total mission time.

On-demand secondary rails

Helps: avoids powering drivers/AFEs when not needed.

Hurts: rail ramp and load-step stability requirements.

Use when: secondary loads are intermittent or bursty.

Rail partitioning + load switches

Helps: isolates always-on small rails from high-pulse rails.

Hurts: added parts and validation effort.

Use when: one sub-rail dominates standby dissipation.

Post-reg strategy (LDO vs switch vs gating)

Helps: prevents LDO drop loss from dominating at light load.

Hurts: noise or complexity depending on approach.

Use when: (Vin−Vout) × I becomes the largest idle heat term.

Validation (avoid false reads)

  • Stable-window rule: measure Pin only after mode settles (use a defined stability criterion).
  • State table: record sleep/idle/active Pin separately to isolate constant losses.
  • Event sensitivity: vary event rate or toggling and observe Pin slope to expose frequency-driven terms.
  • Thermal correlation: confirm that reduced Pin produces reduced hotspot ΔT in steady-state.
No-load loss anatomy A zero-load power path highlights housekeeping, maintenance energy, SR/min-load behavior, and burst/skip events. Symptoms include temperature rise, battery drain, and ripple/EMI risk. No-load loss anatomy (0-load path) Input Pin Controller Power stage Secondary rails Housekeeping Maintain energy SR / min-load Burst / skip Symptoms Temp rise Battery drain Ripple / EMI risk Key guardrail Measure only after modes settle (stable window), then correlate Pin to hotspot ΔT.
No-load loss anatomy: constant housekeeping and light-load control behavior can dominate standby heat and ripple.

Bias Efficiency Across Load (Peak Is Not the Target)

Peak efficiency usually occurs at a mid-load point that does not represent real operation. For isolated bias selection, the meaningful metric is the efficiency and dissipation in the operating band and the weighted outcome under the system’s load profile.

Card A · Peak-η myth

  • Peak-η ≠ average heat: idle/light-load often dominates time.
  • No-load matters: constant loss sets baseline temperature rise.
  • Mis-selection risk: a great peak number can still fail standby power or enclosure ΔT.

Card B · Weighted-η view

  1. Write a load profile: sleep / idle / active / peak shares.
  2. Mark the operating band on the η vs load curve for each state.
  3. Prioritize the band that contributes most to average dissipation and enclosure ΔT.

Card C · Light-load mode side effects

  • Ripple increase: burst/skip modes can amplify low-frequency ripple.
  • Mode switching jumps: noise and Pin can change abruptly across states.
  • Sensitive rails: measurement or clock-related rails may need extra margin checks.
Efficiency vs Load (Operating Band Highlight) Efficiency curve is shown versus load. The operating band is highlighted and contrasted with the peak efficiency point. Efficiency vs Load: focus on the operating band Load η Peak-η Operating band Sleep Idle Active Peak Selection should optimize the operating band, not the single peak point.
Efficiency curve: highlight the operating band (sleep/idle/active/peak) and judge average dissipation accordingly.

Gate-Driver Dissipation vs Gate Charge (Qg Sets the Floor)

Gate-drive power has a hard lower bound: charging and discharging the gate each cycle moves a fixed charge. The core term is P_gate ≈ Qg × Vg × fsw. Additional components (quiescent and overlap/output-stage losses) can raise real dissipation above the floor, especially at high switching rates and in small packages.

Formula card (minimal)

Core floor

P_gate ≈ Qg × Vg × fsw

Meaning: energy-per-cycle times events-per-second sets the minimum.

Add-ons (concept-level)

P_quiescent: driver bias and housekeeping.

P_overlap / P_output: output-stage overlap and pulse conduction losses.

Variable card (what changes what)

  • fsw / events: effective events per second can exceed the “PWM frequency” under burst patterns.
  • Vg: raising Vg increases gate energy; lowering Vg reduces driver heat but requires system checks.
  • Qg@V: Qg depends on operating point and temperature; use the correct condition for budgeting.
  • Rdriver / waveform: output-stage pulse losses grow with peak currents and overlap behavior.

Design knobs (with trade-offs)

Reduce Vg

Helps: lowers P_gate linearly.

Hurts: switching behavior and margins may change.

Use when: thermal margin is the primary constraint.

Reduce fsw / event count

Helps: lowers the frequency-driven floor.

Hurts: may shift ripple and control behavior.

Use when: switching events dominate the budget.

Select lower-Qg devices

Helps: reduces per-cycle gate energy.

Hurts: cost and conduction trade-offs may appear.

Use when: driver loss sets hotspot temperature.

Tune gate resistance / edge rate

Helps: can reduce overlap and pulse losses in some cases.

Hurts: switching transitions and margins must be re-verified.

Use when: overlap/pulse loss is suspected to exceed the Qg floor.

Substitution template (fields only)

  • Qg@V (nC): Qg at the intended Vg and operating point
  • Vg (V): gate-drive swing
  • fsw (Hz) / events/s: effective switching events
  • Nswitches: number of driven devices per cycle path
  • Duty / pattern: burst / PWM patterns that change event count
  • P_quiescent: driver bias term (placeholder)
  • P_overlap / P_output: overlap/pulse term (placeholder)
Qg energy per cycle Gate charge is represented as a bucket filled and emptied each cycle. Per-cycle energy is approximated as E≈Qg·Vg, and multiplying by fsw yields power. Quiescent and overlap add-ons are shown as additional blocks. Qg model: per-cycle energy → power Gate bucket Qg charge discharge Energy / cycle E ≈ Qg · Vg Power P ≈ E · fsw fsw / events Quiescent Overlap / output Qg sets the floor; overlap and output-stage losses can raise real dissipation above the floor. Budget with fields: Qg@V, Vg, fsw, Nswitches, pattern, P_quiescent, P_overlap.
Qg bucket model: per-cycle energy (Qg·Vg) multiplied by event rate sets the gate-drive power floor; add-ons raise real dissipation.

Trade-Off Knobs (Reduce Heat Without Surprise Failures)

Thermal fixes are rarely “free.” Each knob that lowers one heat source can relocate stress to EMI, switching loss, or control stability. This section lists practical knobs in a consistent, review-friendly format: Knob / Helps / Hurts / When to use.

Knob cards (matrix without wide tables)

Knob · Reduce Vg

Helps: lowers gate-drive floor roughly linearly (Qg·Vg·events).

Hurts: margins and transition behavior may shift; re-check operating window.

When to use: driver/bias hotspot dominates enclosure ΔT.

Knob · Staged drive (sleep/idle/active)

Helps: removes constant losses during long idle/sleep periods.

Hurts: wake sequencing and state transitions must be validated.

When to use: duty-cycle is mostly idle with short active bursts.

Knob · Disable non-essential channels

Helps: reduces isolator/interface activity power and secondary rail load.

Hurts: diagnostic/monitor coverage can drop if not planned.

When to use: multi-channel systems where not all lanes are required in every state.

Knob · Edge-rate shaping

Helps: often reduces EMI and dv/dt-driven injection paths.

Hurts: can increase switching loss; heat may relocate to the power device.

When to use: EMI/injection margin is tight and power-device thermal headroom exists.

Knob · Reduce event count (effective switching events)

Helps: lowers frequency-driven losses across driver and dynamic coupling terms.

Hurts: can change ripple and transient behavior; re-check output quality window.

When to use: frequency/event-driven terms dominate the power tree.

Knob · Rail partitioning (always-on vs pulsed rails)

Helps: prevents pulsed loads from forcing always-on rails to stay enabled.

Hurts: adds parts and sequencing validation work.

When to use: one secondary rail dominates standby dissipation.

Heat relocation guardrail

  • Driver heat ↓ can mean switch loss ↑ if edges are slowed or margins shift.
  • EMI ↓ can come with efficiency ↓ if transitions move away from the optimum window.
  • Any knob change should be tied to a before/after record of Pin and hotspot ΔT in the same steady-state window.
Knob → Heat relocation Knobs can reduce driver heat but may relocate loss to switching heat or affect EMI and control stability. Diagram uses arrows from knob blocks to outcome blocks. Knob → Heat relocation (what moves where) Knobs Vg ↓ Staged drive Disable channels Edge-rate shaping Event count ↓ Rail partitioning Relocation Outcomes Driver heat ↓ Bias loss ↓ Switch loss ↑/↓ Hotspot may move EMI ↓/↑ dv/dt injection shifts Control risk ↑ State transitions matter
Knob changes often relocate constraints. Track “driver heat,” “switch loss,” “EMI,” and “control risk” together in the same steady-state window.

Thermal Model (From Power to Temperature Rise)

Power budgets become actionable only when translated into board temperature rise. A minimal thermal model uses a thermal resistance ladder (junction → package → PCB spreading → ambient) to estimate ΔT ≈ P × Rθ, then refines the estimate with a small number of steady-state measurements.

Thermal resistance ladder

  • Junction → Package: device internal path (hot die region).
  • Package → PCB: copper contact and vias set spreading efficiency.
  • PCB → Ambient: airflow, enclosure, and nearby heat sources dominate.

Typical hotspot candidates

  • Driver die: small package + frequency-driven loss.
  • Transformer / magnetics: core/copper loss + limited convection.
  • Rectifier / LDO: conduction or drop loss on secondary rails.

Thermal design inputs (collect before estimating)

Ambient

Ta: ambient temperature (state-specific)

Airflow: none / weak / strong

Enclosure: sealed / vented / metal conduction path

PCB spreading

Copper area: small / medium / large

Layers: low / mid / high

Thermal vias: sparse / moderate / dense

Neighbor heat

Distance: near / mid / far from other hotspots

Shared copper: shared plane vs isolated copper

Power inputs

P_total: total dissipation in the target state

P_hotspot: dominant branch from the power tree

Minimal estimation (3 steps)

  1. Pick the hotspot branch and record P_hotspot for the target state.
  2. Select a conservative Rθ_effective based on PCB spreading and airflow class.
  3. Estimate ΔT ≈ P × Rθ and compare to the temperature margin (pass window).

Calibration (steady-state, short and practical)

  • Measure a steady-state hotspot ΔT in the same operating state used for the power budget.
  • Back-calculate Rθ_effective and reuse it for nearby states/load points.
  • Re-check after any knob that relocates heat (driver ↓ but switch/magnetics ↑).
Thermal resistance ladder Thermal path is shown as a ladder from junction to ambient with Rθ labels. Hotspot candidates are highlighted: driver die, magnetics, rectifier/LDO. Thermal resistance ladder: power → temperature rise Junction Hot die RθJC Package Leadframe ψJB PCB spreading Copper + vias Ambient Ta + airflow RθJA Hotspot markers Driver die Transformer / magnetics Rectifier / LDO Inputs: Ta · airflow · copper area · vias · neighbor heat · enclosure
Thermal ladder: translate the dominant power branch into ΔT with an effective Rθ, then calibrate using a steady-state measurement.

Layout for Thermal Without Crossing the Barrier

The isolation gap breaks copper continuity. Thermal optimization must respect partition boundaries: heat spreading should stay inside each domain, return paths must not jump the barrier, and creepage/clearance margins must not be reduced by “helpful” copper extensions near the gap.

Hard partition rules

  • Thermal closed-loop per domain: primary heat spreading stays on primary copper; secondary stays on secondary copper.
  • No barrier bridging: no copper bridge, no “mesh copper,” no accidental reference-plane continuity across the gap.
  • Thermal + return reviewed together: any copper added for heat must be checked for unintended return shortcuts.

Do (thermal within partitions)

Copper spreading inside the same domain

Goal: enlarge local copper area for hotspot spreading without approaching the barrier edge.

Typical moves: local copper island, wider pour, short-and-wide connections.

Thermal vias into same-domain planes

Goal: push heat into internal copper where spreading is stronger.

Typical moves: via arrays under hotspots, plane coupling within the same side.

Local “heat islands” + placement strategy

Goal: keep hotspots away from sensitive nodes and away from the barrier edge.

Typical moves: place hot parts closer to airflow paths; keep distance from low-level sensing.

Don’t (common failure patterns)

Don’t extend copper toward the barrier for “extra area”

Risk: creepage margin shrinks silently; gap edge becomes a contamination hot zone.

Don’t create hidden bridges

Risk: thin traces, stitching copper, guard fills, or test pads can unintentionally bridge domains.

Don’t treat “thermal fixes” as electrically neutral

Risk: added copper changes return paths and coupling, impacting EMI and isolation behavior.

Review checklist (fast pass)

  • Gap edge scan: confirm “no copper bridge” and no fills near the barrier edge.
  • Creepage sanity: verify heat copper did not encroach on the separation margin.
  • Return path sanity: confirm no new return shortcut was introduced by thermal copper.
Partitioned thermal islands Two thermal islands are shown on primary and secondary sides separated by an isolation barrier gap. Each side has hotspot, copper island, via field, and plane spreading. The barrier is labeled no copper bridge. Partitioned thermal islands (no copper bridge) Isolation barrier NO copper bridge Primary domain Hot device Copper island Via field Plane spreading Secondary domain Hot device Copper island Via field Plane spreading Creepage Return
Thermal spreading must remain partitioned: build thermal islands inside each domain and keep the barrier edge free of copper bridges.

Measurement & Bring-Up Validation (Avoid False Readings)

Power and temperature measurements can be misleading when operating modes change, when sampling windows include burst events, or when measurement points are inconsistent across isolation domains. This section uses an engineering-friendly flow: Trap → Quick check → Fix.

No-load / light-load

Trap

Pin appears unstable or differs significantly between instruments or runs.

Quick check

Confirm the state is settled (sleep/idle) and the sampling window excludes mode-entry transients.

Fix

Use a defined steady-state window; record sleep/idle/active as separate rows (no mixing).

Trap

Burst/skip behavior creates large instantaneous power swings that bias averages.

Quick check

Observe whether power is event-clustered (periodic bursts) rather than continuous.

Fix

Keep the same event pattern during comparisons; note the pattern class in the test log.

Driver dissipation vs Qg

Trap

Qg·Vg·f estimate is far below measured driver/bias dissipation.

Quick check

Verify that “f” is the effective event rate, and that Vg swing matches the Qg condition used.

Fix

Log fields consistently: Qg@V, Vg, events/s, Nswitches, pattern; compare only within the same state window.

Trap

A knob change does not produce the expected power trend.

Quick check

Check whether quiescent or overlap/pulse losses dominate in the current operating point.

Fix

Run a single-variable A/B (e.g., Vg ↓ only) and verify whether driver power follows the expected direction.

Temperature rise (ΔT)

Trap

Temperature differs across runs because measurement points or airflow conditions drift.

Quick check

Confirm fixed sensor placement and a consistent airflow/enclosure condition.

Fix

Define and record fixed points: T1 driver, T2 magnetics, T3 rectifier/LDO (same locations every run).

Trap

Instant temperature is used as pass/fail, before reaching steady state.

Quick check

Check whether temperature slope is still rising (not stable).

Fix

Use a steady-state criterion and log ΔT only inside the stable window.

Bring-up evidence chain (minimal and repeatable)

  • Baseline row: Pin, Pout (if applicable), Vg, events/s, T1/T2/T3 in the same stable window.
  • Single-variable change: adjust one knob only, then re-log the same fields.
  • Pass logic: temperature rise and standby power return to the target window (thresholds as placeholders).
Measurement points map Diagram shows primary side Pin measurement, isolation barrier, secondary side Pout and driver Vg measurement, and temperature points T1 T2 T3. Stable window is highlighted. Measurement points map (Pin / Vg / T1-T3) Primary side Input supply Pin measurement Vin + Iin State: sleep/idle/active Isolation gap Secondary side Secondary rails Pout (optional) Vout + Iout Vg measurement events/s T1 Driver T2 Magnetics T3 Rect/LDO Stable window (steady-state)
Keep comparisons honest: use the same operating state and stable window, measure Pin consistently, and log Vg/events plus fixed T1–T3 locations.

H2-11. Engineering Checklist (Design → Bring-Up → Production Gates)

Goal: convert power-and-thermal knowledge into an executable gate checklist with repeatable evidence.

ScopeLoss budget fields, measurement proof, hotspot mapping, configuration lock, and change-trigger retest rules.
Out of scopeTopology implementation details, deep protection strategy design, and clause-by-clause safety standard interpretation.

Checklist pattern (keep each item short): Item → Evidence → Pass criteria (use X/Y/N placeholders).

Milestone Gates → Evidence Chain → Stable Production Window DESIGN Budget Fields Profile • Limits Worst-Case Ta • Airflow Targets ΔT • Margin BRING-UP No-Load Test Stable Window Qg Alignment Model ↔ Meas Hotspots T1/T2/T3 PRODUCTION Config Locked Retest on Change

Design Gate (6–10 check items)

  • Loss budget template complete — Evidence: filled fields for Pin, branch losses, hotspot loss. Pass: no blank fields.
  • Load profile defined — Evidence: state table (sleep/idle/active/peak) with duty share. Pass: totals = 100%.
  • Worst-case environment fixed — Evidence: Ta, airflow class, enclosure state. Pass: consistent across tests.
  • Temperature targets assigned — Evidence: T1/T2/T3 locations and target windows (X/Y). Pass: windows documented.
  • Knob policy recorded — Evidence: allowed knobs (freq/Vg/channel enable) + side-effect checks. Pass: acceptance items listed.
  • Barrier-safe thermal feasibility — Evidence: partitioned thermal islands plan. Pass: no copper bridge across barrier.

Bring-Up Gate (6–10 check items)

  • No-load power measured with stable window — Evidence: settling time + averaging window. Pass: within X mW.
  • Light-load mode identified — Evidence: mode label (burst/skip/forced PWM). Pass: expected mode achieved.
  • Gate-driver loss aligned to Qg model — Evidence: Qg@V, Vg, switching events/s, measured bias draw. Pass: delta within Y%.
  • Hotspots located (T1/T2/T3) — Evidence: temperature map + airflow condition. Pass: ΔT within X°C.
  • Knob A/B results logged — Evidence: one-variable change log. Pass: trend consistent and repeatable.
  • Failure signature archived — Evidence: state + window + measurement points. Pass: reproducible steps exist.

Production Gate (6–10 check items)

  • Key temperature points audited — Evidence: sampling plan for T1/T2/T3. Pass: within window X°C.
  • Standby/no-load power window locked — Evidence: pass/fail thresholds (X mW). Pass: stable across units.
  • Configuration frozen — Evidence: frequency, driver strength, channel enable policy. Pass: versioned and locked.
  • Change-trigger retest rule defined — Evidence: what changes force retest (layout copper, mode policy, event rate). Pass: rule published.
  • Evidence artifacts stored — Evidence: same template fields for every build. Pass: cross-batch comparison possible.

H2-12. Applications & IC Selection (Power/Thermal-first)

Structure: Applications (where power/thermal is the #1 constraint) + a 5-step selection flow with concrete part-number pools.

A) Applications (power/thermal dominates)

  • Motor / inverter gate drive (high event rate + large Qg)
    Thermal bottleneck: gate-drive bias + driver output stage.
    First checks: Qg@V, Vg, switching events/s, standby draw.
    Example parts: TI UCC21520A, TI UCC21750, ADI ADuM4135.
  • BMS / HV nodes (standby power and enclosure heat)
    Thermal bottleneck: no-load + light-load behavior over long dwell time.
    First checks: standby/no-load window (X mW), load-profile duty share.
    Example parts: ADI LTC6820 (isoSPI link), TI ISOW7841 (integrated isolated power + isolator), ADI ADuM5020 (isolated 500 mW class).
  • High-precision sampling (noise ↔ efficiency sensitivity)
    Thermal bottleneck: light-load modes can inject ripple/EMI while still heating the enclosure.
    First checks: weighted efficiency in operating band, ripple/EMI checks at light load.
    Example parts: ADI ADuM5020 (isolated power), TI SN6505B (transformer driver for isolated bias), Murata NXE1S0505MC (1 W isolated module).
  • Medical HMI / service ports (temperature + standby + leakage constraints)
    Thermal bottleneck: always-on rails and compact enclosures.
    First checks: standby/no-load, enclosure hotspot, leakage-current budget impacts (system-level).
    Example parts: ADI ADuM4160 / ADuM3160 (USB isolation), RECOM R05P05S (1 W isolated module), ADI ADuM5020.
Selection hygiene: treat part numbers as example pools; final choice must match the required isolation rating, approvals, and working-voltage lifetime model.

B) IC Selection Logic (5 steps)

  • Step 1 — Define the load profile
    Output artifact: a 4-state duty-share table (sleep/idle/active/peak) and “events/s” for switching.
  • Step 2 — Pass the no-load / standby gate first
    Output artifact: standby/no-load window (X mW) + measurement window definition.
    Example parts (low-BOM isolated power pools): ADI ADuM5020, TI ISOW7841, Murata NXE1S0505MC, RECOM R05P05S, TRACO TEN 3.
  • Step 3 — Compute the gate-drive loss floor (cannot be cheated)
    Minimal floor: P_gate ≈ Qg × Vg × events/s (per switch leg).
    Output artifact: template fields (Qg@V, Vg, events/s, number of switches, duty).
    Example parts (isolated drivers): TI UCC21520A, TI UCC21750, ADI ADuM4135.
  • Step 4 — Check thermal feasibility at the package + PCB island level
    Output artifact: hotspot list + assumed inputs + “thermal island” placement that does not cross the isolation barrier.
  • Step 5 — Write knob side-effects into acceptance
    Output artifact: verification items for EMI/ripple/timing when knobs change (freq, Vg, channel enable, light-load mode).
Power/Thermal-first Selection Flow (5 Steps) 1) Load Profile Output: duty table 2) No-Load / Standby Gate Output: X mW window 3) Driver Loss Floor (Qg × Vg × events) Output: fields filled 4) Thermal Feasibility → 5) Validate (EMI/Ripple/Timing) Output: pass items

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H2-13. FAQs (Power & Thermal) — Field Troubleshooting & Acceptance

How to use these FAQs

Each answer is fixed to four lines for fast review and consistent acceptance: Likely cause / Quick check / Fix / Pass criteria. Thresholds are placeholders (X/Y/N) so they can be aligned to system targets and lab methods.

X_mW Y_s N_runs ±Y_% X_°C Airflow_Class Enclosure_State events_per_s
Data fields to log (recommended): state (sleep/idle/active/peak), stable window, Pin, optional Pout, Vg, events_per_s, and fixed temperature points T1/T2/T3.
No-load power is 3× higher than expected — what is the first accounting check?
Likely cause: constant losses were added/omitted (controller housekeeping, isolated-bias no-load, always-on loads) or the wrong state window was measured.
Quick check: confirm the device is in the intended state (sleep/idle) and average Pin only inside a defined stable window (exclude mode-entry transients).
Fix: split measurements by state, log constant-loss contributors explicitly, and update the loss budget fields before changing hardware.
Pass criteria: no-load PinX_mW over Y_s stable window, repeatability within ±Y_% across N_runs.
Standby runs hot even at light load — did burst/skip bias the average?
Likely cause: burst/skip clusters energy into short events, making average power sensitive to the sampling window and “settling” assumptions.
Quick check: observe whether power is event-clustered (periodic bursts) and whether the averaging window covers whole burst periods.
Fix: standardize the stable window and record the mode class (burst/skip/forced PWM); compare only like-for-like windows and modes.
Pass criteria: standby temperature rise ΔTX_°C and standby Pin within X_mW when measured with the same mode and window definition.
Efficiency curve looks great in the datasheet, but system power is high — what was omitted?
Likely cause: datasheet efficiency is often measured at a specific load point; system power includes constant losses, bias rails, LDO drops, and non-ideal operating states.
Quick check: compare the datasheet test conditions (Vin/Vout/load/mode) to the real operating band and list all always-on rails and post-reg stages.
Fix: switch to a state-based budget (sleep/idle/active/peak) and compute a weighted average that includes constant-loss terms.
Pass criteria: measured weighted system power matches the budget within ±Y_% over N_runs using the same state definitions.
Peak efficiency is high, but enclosure temperature is still too high — what perspective is missing?
Likely cause: peak-η was optimized while the dominant dwell time is at light/idle loads where no-load and light-load losses dominate heat.
Quick check: quantify dwell time in each state (sleep/idle/active/peak) and identify which state contributes most to energy over time.
Fix: optimize for weighted efficiency in the real operating band; enforce a no-load/standby gate before chasing peak-η.
Pass criteria: weighted power ≤ X_mW (or budget target) and enclosure hotspot ΔTX_°C under Airflow_Class and Enclosure_State.
Driver case runs hot but switching loss seems fine — Qg model mismatch or non-Qg loss?
Likely cause: the effective event rate differs from nominal frequency, or non-Qg terms (quiescent draw, overlap/pulse loss) dominate in this operating point.
Quick check: log Vg, events_per_s, and the Qg@V condition used; verify the waveform and operating state are consistent with the estimate.
Fix: align the model inputs to measured conditions, then run a single-variable A/B (e.g., Vg ↓ only) to identify whether losses scale as expected.
Pass criteria: measured driver/bias power matches the Qg-based estimate within ±Y_% at the same events_per_s and state window.
Driver power does not scale with Vg as expected — what dominates first?
Likely cause: quiescent or overlap/pulse losses dominate, so reducing Vg only changes a smaller share of total dissipation.
Quick check: measure driver/bias power at two Vg settings with identical events_per_s and identical state; compare the delta to the expected proportional change.
Fix: separate “Qg-proportional” from “constant/overlap” components in the log; address the dominant component with a knob that targets it (enable policy / driver strength / event rate).
Pass criteria: A/B test shows a consistent trend (direction correct) and repeatability within ±Y_% across N_runs.
Lower Vg reduces driver heat but EMI fails — what knob should change next?
Likely cause: edge-rate and switching transitions moved the EMI balance; the “heat knob” changed timing/spectral content and violated the acceptance margin.
Quick check: compare EMI results and power/thermal logs under the same state window; confirm only one knob changed (single-variable rule).
Fix: adjust a knob that shapes emissions without undoing the thermal target (driver strength step, enable policy, or event clustering control), then re-validate in the same window.
Pass criteria: thermal target met (ΔT ≤ X_°C) and EMI acceptance passes with the updated knob set; record knob set version = N.
Same Qg and nominal frequency, but different boards show different driver heat — what is inconsistent?
Likely cause: effective events_per_s, Vg swing, or waveform shape differs due to state logic, dead-time behavior, or measurement point inconsistency.
Quick check: verify identical state definitions and log events_per_s, Vg, and the same measurement points across boards.
Fix: lock configuration (freq/driver strength/enable policy) and rerun with fixed T1/T2/T3 placement and stable-window averaging.
Pass criteria: board-to-board driver/bias power variation ≤ ±Y_% over N_runs with configuration version locked.
Thermal passes on the bench, fails in the enclosure — what airflow assumption broke first?
Likely cause: airflow class and boundary conditions changed (restricted vents, different orientation, recirculation), invalidating the assumed Rθ to ambient.
Quick check: verify Airflow_Class and Enclosure_State match the design assumptions; confirm test orientation and nearby heat sources.
Fix: re-baseline thermal with enclosure conditions, then adjust only the knob set needed to meet ΔT while keeping acceptance checks intact.
Pass criteria: enclosure hotspot ΔT ≤ X_°C under the declared Airflow_Class and Enclosure_State, repeated across N_runs.
Hotspot location keeps changing — measurement error or real heat migration?
Likely cause: inconsistent T-point placement or non-steady measurement; alternatively, a knob moved dissipation to another component (heat relocation).
Quick check: confirm fixed T1/T2/T3 locations and that temperature is recorded only in the stable window; note any knob changes since baseline.
Fix: standardize the measurement map and rerun a single-variable A/B; if relocation is real, update the acceptance list to include the new hotspot.
Pass criteria: hotspot identity stable across N_runs, and all monitored points (T1/T2/T3) remain within ΔT window ≤ X_°C.
ΔT does not match P×Rθ on paper — which boundary condition is usually wrong?
Likely cause: Rθ boundary mismatch (board copper, airflow, enclosure, neighboring heat sources) or power was averaged over a non-equivalent window.
Quick check: confirm the Rθ definition used (ambient vs board vs case) and verify the measured power window aligns with the thermal steady state.
Fix: calibrate the thermal model with one measured baseline under controlled conditions, then reuse the calibrated inputs for comparisons.
Pass criteria: calibrated model predicts ΔT within ±Y_% (or ±X_°C) for the baseline and remains consistent across N_runs.
After adding thermal copper, isolation review fails — what layout rule was violated?
Likely cause: thermal copper encroached near the barrier edge, shrinking separation margin or creating an unintended bridge/coupling path.
Quick check: scan the barrier edge for copper extensions, thin “mesh” fills, stitching patterns, or any geometry that approaches the separation boundary.
Fix: restore partitioned thermal islands (no cross-gap copper) and re-run the thermal plan within each domain’s closed loop.
Pass criteria: “no copper bridge” verified; separation margin unchanged from the approved baseline; thermal targets still met (ΔT ≤ X_°C).