Propagation Delay / Skew / Jitter for Isolation Timing
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Propagation delay, skew, and jitter in isolation are system timing terms: they must be defined at the correct reference plane, budgeted end-to-end, and verified under frozen measurement context. This page turns datasheet numbers into audit-ready gates—so JESD/ADC/DAC clock and data paths pass consistently across benches, labs, and production.
H2-1 · Scope & Timing Relevance
Isolation is not a transparent wire. The barrier turns timing into a combination of mean delay, channel mismatch, and edge-time dispersion. Once a system enters clocked sampling or synchronized multi-channel control, these terms become the limiting budget that decides whether links, sampling, and protection behavior remain deterministic.
This page is a system-level timing anchor: it defines how propagation delay, skew, and jitter are interpreted, budgeted, and validated across an isolation barrier.
It avoids datasheet repetition and focuses on the engineering question: where timing margin is consumed first and how to keep it measurable and controllable.
When it matters
Timing becomes a first-order constraint when any of the following is true:
clock isolation
high-speed data
multi-channel sync
high dv/dt switching
field wiring variability
Clock isolation
- Where timing goes: additive jitter and deterministic delay through encode/decode and edge restoration.
- What breaks first: sampling aperture margin and phase-noise/jitter budget at ADC/DAC/FPGA clock pins.
- What must be budgeted: RMS jitter + drift with PVT; correlation between clock lanes and SYSREF-like strobes.
- What to read next: clock vs data rules (later chapter), then budget methodology.
High-speed data
- Where timing goes: edge displacement and asymmetry (rise/fall) through barrier and receiver conditioning.
- What breaks first: eye opening (UI margin) and error-rate tail under temperature, VDD noise, and dv/dt events.
- What must be budgeted: deterministic components (bounded) vs statistical jitter; lane-to-lane skew for alignment.
- What to read next: jitter decomposition, then measurement pitfalls.
Multi-channel sync
- Where timing goes: channel-to-channel skew and skew drift from shared/independent supplies and internal path mismatch.
- What breaks first: phase alignment, simultaneous sampling, dead-time matching, or interlock timing margins.
- What must be budgeted: worst-case skew + skew drift; direction mix effects (uni/bi-directional lanes).
- What to read next: skew mechanics and production validation gates.
Scope guard (non-overlap contract): This page covers timing terms across the isolation barrier (delay / skew / jitter), their budgeting, measurement, and validation.
It does not define protocol details or ADC/DAC architectures; those topics should link here for timing definitions.
H2-2 · Timing Taxonomy: Delay vs Skew vs Jitter
Timing terms are often mixed because they look similar on a scope. For isolation design, the difference is non-negotiable: delay is a mean shift, skew is a channel mismatch, and jitter is a distribution width that consumes eye/aperture margin.
Propagation delay (mean)
- What it is: input edge to output edge time difference on one lane.
- Statistic: typical/mean vs max (center vs boundary).
- Conditions: VDD, temperature, edge rate, load, direction.
- Impacts: handshake timing, loop latency, deterministic alignment offset.
- Not this: not channel mismatch; not edge-time spread.
Skew (Δ between channels)
- What it is: delay difference between lanes under the same stimulus.
- Statistic: max skew vs RMS skew (must be stated explicitly).
- Conditions: shared vs independent supplies; direction mix; loading asymmetry.
- Impacts: multi-channel sampling, phase alignment, dead-time matching.
- Not this: not single-lane jitter width.
Jitter (distribution width)
- What it is: edge-time variation across repeated transitions.
- Statistic: RMS vs p-p vs bounded (reporting must match the budget method).
- Conditions: bandwidth, trigger method, measurement window, power noise.
- Impacts: eye opening, sampling SNR, clock phase-noise budget.
- Not this: not mean delay drift with temperature (drift is separate).
Datasheet term mapping (normalize wording)
- tPD / tPLH / tPHL → propagation delay (lane mean shift)
- ΔtPD / channel-to-channel skew → skew (lane mismatch)
- additive jitter / RMS jitter → jitter (distribution width)
- rise/fall asymmetry → deterministic edge distortion (can appear as DJ)
- temp drift → delay/skew drift (treat as slow variation, not random jitter)
The same label can hide different statistics. Always check whether a number is RMS, p-p, or bounded, and under what bandwidth/window.
Common misuse patterns (quick corrections)
- Skew treated as jitter: mismatch between lanes is not stochastic edge spread; it must be aligned or budgeted separately.
- p-p used as RMS: mixing statistics makes budgets non-portable across teams and labs.
- Drift treated as jitter: temperature/VDD drift is slow variation and should be handled as a separate margin term.
- Window mismatch: jitter measured with different time windows cannot be compared directly.
- Probe/trigger artifacts: measurement method can create “fake jitter” that disappears in a proper setup.
Next-step reading path: After terms are normalized, the page can expand each item independently:
delay fundamentals → skew mechanics → jitter decomposition, then budgeting and measurement gates.
H2-3 · Propagation Delay Fundamentals
Propagation delay across an isolation barrier is not a single constant. It is a mean shift with environment-driven drift and lifecycle drift. Treating delay as a fixed number can silently consume timing margin in synchronized sampling, closed-loop control, and safety interlocks.
Delay should be handled as three engineering terms: Mean delay (static offset that can be aligned),
PVT drift (voltage/temperature dependence that must be budgeted), and Aging drift
(slow, long-term shift that reduces lifetime margin). This separation keeps timing closure measurable and portable across labs.
Mean delay
- Meaning: average input-edge to output-edge time shift per lane.
- Origin: encode/decode, edge restoration, internal buffer paths.
- System effect: fixed alignment offset; affects static timing closure and deterministic latency.
- Control: compensate with alignment/phase offsets when the drift terms are separately bounded.
PVT drift
- Meaning: delay change with Voltage and Temperature (and load/edge rate).
- Behavior: continuous and often monotonic; may be correlated across channels or not.
- System effect: consumes guard band; can turn “passing at room” into “failing at corners”.
- Control: budget worst-case across conditions; avoid mixing with jitter statistics.
Aging drift
- Meaning: slow shift over months/years; not a random variation term.
- Behavior: moves the envelope; reduces long-term timing margin.
- System effect: calibration assumptions degrade; multi-year sync tolerance shrinks.
- Control: include lifetime margin and production re-validation triggers.
Practical rule: mean delay can be compensated; drift must be budgeted; aging must be covered by lifetime margin and test gates.
Treating drift as “jitter” creates non-portable budgets and inconsistent lab results.
H2-4 · Channel-to-Channel Skew Mechanics
In multi-channel isolators, skew is the first timing limit that breaks synchronization. Skew is a lane-to-lane mismatch (Δt) and must be handled separately from jitter, which is edge-time dispersion on a single lane. Treating skew as jitter hides deterministic misalignment and leads to fragile timing closure.
Skew typically comes from three mechanisms: internal path mismatch, supply coupling (shared vs independent), and
rise/fall asymmetry. Each mechanism creates a different failure signature and requires a different control knob.
Internal path mismatch
- Source: non-identical encoder/decoder and buffer chains across lanes.
- Signature: stable Δt that persists across repeated captures.
- Risk: consumes multi-lane alignment margin even when jitter is low.
- Control: choose matched lanes; keep directions and loading consistent.
Shared vs independent supplies
- Source: supply-induced delay modulation that can correlate or de-correlate across lanes.
- Signature: Δt grows at corners or under switching noise; may track VDD/Temp.
- Risk: skew drift breaks “once-calibrated” assumptions.
- Control: keep supply domains consistent; reduce supply impedance and noise coupling.
Rise / fall asymmetry
- Source: asymmetric edge conditioning and threshold behavior through the barrier.
- Signature: polarity-dependent timing; direction mix amplifies mismatch.
- Risk: appears like “random timing issues” but is deterministic distortion.
- Control: standardize edge rates and logic polarity; avoid mixing lane directions where possible.
Separation rule: Skew is measured between lanes under the same stimulus; jitter is measured within one lane across repetitions.
A correct budget keeps them as independent terms with explicit statistics.
H2-5 · Jitter Decomposition (RJ / DJ / Bounded)
Jitter becomes engineering-grade only after it is split into components that can be budgeted and validated consistently. RJ is statistical noise, DJ is deterministic distortion tied to patterns and edges, and Bounded jitter is set by the isolation modulation/recovery mechanism.
The decomposition below separates statistical additivity from bounded behavior. This prevents mixing RMS numbers with
p-p envelopes and avoids lab-to-lab disagreements caused by window, bandwidth, and pattern dependence.
RJ
Noise-dominant
Nature
Unbounded statistical edge-time variation driven by thermal/noise-like processes.
What it looks like
Symmetric “edge cloud” around the mean transition; expands with bandwidth and noise.
Budget rule
Use RMS-based aggregation (variance-like). Keep bandwidth and measurement window explicit.
Validation rule
Declare instrument bandwidth, time window, and trigger method; compare like-for-like settings only.
DJ
Edge / pattern
Nature
Deterministic timing displacement tied to edge shape, thresholds, encoding, and supply modulation.
What it looks like
Asymmetric or multi-peak timing; depends on data pattern and operating conditions.
Budget rule
Treat as bounded contributions per mechanism; avoid replacing it with a single RMS value.
Validation rule
Use defined stress patterns and corner conditions; record the pattern set as part of the test report.
Bounded
Mechanism-limited
Nature
Timing error limited by the isolation modulation / recovery mechanism and its internal state behavior.
What it looks like
Steps or ceilings: transitions land inside a bounded window rather than spreading indefinitely.
Budget rule
Use envelope-style allocation; ensure the worst-case bound is covered under defined conditions.
Validation rule
Define recovery modes, corner cases, and stress sequences; validate the bound across them.
Reporting rule: A jitter number is incomplete unless its statistic (RMS / p-p / bounded), bandwidth, window, and pattern context are declared.
Mixing RJ-style RMS with bounded envelopes produces non-portable budgets.
H2-6 · Isolation Barrier Sources of Timing Error
Jitter components map back to specific timing-sensitive blocks inside the isolation path. Without process detail, timing error can be traced to modulation/encoding, demodulation/recovery, and common-mode dv/dt injection. Different isolator classes shift which block dominates, but the same mechanism map remains valid.
The mechanism view below links each block to the most likely jitter class behavior. This keeps selection and validation aligned:
statistical terms remain statistical, while mechanism-limited behavior is verified by coverage and bounds.
Modulation / encoding
- Timing variable: encoding edge placement and internal state-dependent timing.
- Often appears as: DJ or bounded behavior under certain patterns/modes.
- System symptom: pattern sensitivity; lane-to-lane differences on specific transitions.
Demodulation / recovery
- Timing variable: edge restoration thresholds and recovery latency.
- Often appears as: DJ (edge asymmetry) and bounded steps under recovery modes.
- System symptom: eye closure under corners; mode-dependent latency changes.
Common-mode dv/dt injection
- Timing variable: barrier coupling injects disturbances into edge timing and thresholds.
- Often appears as: RJ-like spread or bounded steps depending on recovery design.
- System symptom: jitter spikes during switching events even with clean bench signals.
Non-overlap rule: This section explains where timing error enters the path. Measurement setup details and acceptance gates belong to the later validation chapter.
H2-7 · Clock vs Data Isolation: Different Rules
Clock isolation and data isolation use different timing rulers. For clocked sampling (JESD, SYSREF-like strobes, and ADC/DAC clocks), jitter maps into sampling phase error with near zero tolerance. For data paths, jitter consumes eye opening and is judged against UI-level margin.
Mixing clock and data criteria is a common root cause of “works on bench, fails in system” outcomes. A correct review separates
sampling-performance metrics from link-margin metrics and validates them with different pass criteria.
Clock isolation
fs–ps class
- What jitter means: sampling phase/time error at the clock pin.
- First failure mode: SNR/ENOB loss, spurs, degraded aperture margin.
- Metric style: RMS/additive jitter with explicit bandwidth/window.
- Validation style: clock-jitter and phase-noise aligned to the sampling performance budget.
Data isolation
UI class
- What jitter means: edge displacement that reduces eye opening.
- First failure mode: BER tail, intermittent training/lock loss, margin collapse at corners.
- Metric style: UI-based budget terms and bounded envelopes for deterministic behavior.
- Validation style: eye/BER with defined patterns, temperature corners, and receiver settings.
Non-overlap rule: Clock isolation is validated against sampling performance; data isolation is validated against link margin.
The same “jitter number” is not portable across these two rulers.
H2-8 · System Budgeting for JESD / ADC / DAC
System timing closure requires budgeting across Source, Isolation, and Receiver. A correct budget separates RMS-additive terms from bounded envelopes and keeps measurement context explicit so that results remain comparable across labs and builds.
The budgeting template below turns datasheet numbers into system ownership buckets (“who consumes margin”)
and ties each bucket to a budget style and pass-criteria placeholder. This supports fast root-cause isolation when margins collapse.
| Bucket | Main term | Budget style | Pass criteria |
|---|---|---|---|
| Source | Clock tree noise / launch edge quality | RMS add for noise-like terms; bound deterministic launch distortion | X (RMS) within Y window |
| Isolation | Additive jitter + bounded recovery behavior | Split RJ vs DJ vs bounded; do not collapse into a single RMS | X (RMS) + Y (bound) |
| Receiver | Sampling aperture / threshold sensitivity | RMS add where appropriate; include receiver-mode dependent bounds | X margin at corner |
| Skew | Lane-to-lane mismatch and drift | Worst-case envelope across PVT and mode; separate from jitter | Δt ≤ X at corners |
| Delay drift | Mean delay change with PVT / aging | Worst-case drift + lifetime margin; align mean only after drift is bounded | Δdelay ≤ X over Y life |
Budgeting rule: RMS-only budgets apply to noise-like terms. Mechanism-limited behavior must keep a bounded envelope and be validated with mode coverage.
Skew and delay drift are separate from jitter and should not be “absorbed” into an RMS number.
H2-9 · Measurement & Correlation Pitfalls
Lab numbers can disagree with system behavior when measurement context is not normalized. Timing metrics are only comparable when bandwidth, window, trigger reference plane, and traffic pattern are declared and matched.
The pitfalls below focus on correlation breakers that frequently mis-assign ownership in system budgets. Each item includes a fast sanity check
and a normalization fix that makes results portable across benches and labs.
Pitfall Probe loading
What it breaks
Adds capacitance and a return loop that reshapes edges and reflections; the instrument becomes part of the channel.
Quick check
Compare with and without the probe at the same node; look for systematic edge-rate and overshoot changes.
Fix / normalize
Use low-loading differential probing or a defined measurement pad; keep the reference plane consistent across setups.
Pitfall Trigger mismatch
What it breaks
Misaligned time bases fold drift into jitter or hide bounded steps; results shift with trigger point selection.
Quick check
Re-run with trigger moved to the same reference plane (source vs receiver); watch for offset and spread changes.
Fix / normalize
Define a single trigger/reference plane and record it; avoid mixing instrument reference and DUT-derived reference.
Pitfall Counter window / denominator
What it breaks
Averaging hides burst errors; different windows produce different “rates” for the same failure mechanism.
Quick check
Split metrics by short and long windows; verify whether failures appear as bursts rather than steady random errors.
Fix / normalize
Standardize time windows and reset policy; report both tail (burst) and average behavior as separate numbers.
Pitfall Bandwidth mismatch
What it breaks
RJ-like spread scales with bandwidth; different front-end bandwidths report different jitter for the same DUT.
Quick check
Repeat with matched bandwidth limits; compare RMS values after normalizing the instrument path.
Fix / normalize
Declare bandwidth and filtering; never compare RMS jitter numbers without bandwidth alignment.
Pitfall Pattern dependence
What it breaks
Deterministic jitter and bounded behavior can depend on traffic patterns; PRBS may not represent real traffic.
Quick check
Compare a defined stress pattern set with a real-traffic capture; look for mode- or transition-specific outliers.
Fix / normalize
Define and freeze a pattern suite for correlation; include transitions that stress encoding/recovery modes.
Pitfall Reference plane mismatch
What it breaks
Measuring at different nodes (pin, via, connector) changes observed reflections and skew; “same signal” is not the same plane.
Quick check
Move the measurement point along the path; quantify how much the metric changes with plane selection.
Fix / normalize
Document a single plane for acceptance and a second plane for debug; do not mix them in the same report.
Correlation rule: A timing metric is incomplete without its context: bandwidth, window, trigger plane, and traffic pattern.
Normalize context first; assign ownership second.
H2-10 · Design Hooks & Control Knobs
Timing can be improved without changing device class by applying controllable design knobs. The goal is to reduce supply-to-edge coupling, limit deterministic edge distortion, and keep multi-lane behavior consistent for skew control.
The hooks below provide strategies rather than part recommendations. Each knob states what it improves, the common trade-off,
and a pass-criteria placeholder to align with system budgeting and validation gates.
Supply isolation
DJ / bounded
- Improves: reduces supply-modulated edge timing and recovery-mode sensitivity.
- Control: partition rails, local filtering, low-impedance return, consistent decoupling.
- Trade-off: startup sequencing, drop/thermal, BOM and layout area.
- Pass criteria: jitter and lock remain within X under Y switching stress.
Edge-rate control
DJ
- Improves: stabilizes threshold crossing time and reduces deterministic edge distortion.
- Control: series damping, drive-strength/slew settings, termination consistency.
- Trade-off: setup/hold margin, dynamic power, and EMI balance.
- Pass criteria: eye opening improves and BER tail reduces under the same pattern suite.
Channel grouping
Skew
- Improves: reduces lane mismatch and drift by keeping lanes in consistent domains and directions.
- Control: group critical lanes, avoid mixed directions, keep loading and routing symmetry.
- Trade-off: pin-mux constraints and routing complexity.
- Pass criteria: Δt(skew) ≤ X across corners and defined modes.
Reference-plane discipline
- Improves: keeps validation comparable across builds and labs; avoids “moving target” acceptance.
- Control: define acceptance plane and debug plane; label pads/vias and keep documents consistent.
- Trade-off: adds documentation and fixture requirements.
- Pass criteria: metrics at the acceptance plane match within X across Y benches.
Mode coverage control
- Improves: exposes bounded behavior and mode-dependent latency that hides under single-pattern tests.
- Control: define a stress pattern suite; include transitions that exercise encode/recovery modes.
- Trade-off: longer test time and more fixtures/scripts.
- Pass criteria: bound and tail metrics hold under the full pattern suite.
Control rule: Apply one knob at a time and re-run the same normalized measurement context (bandwidth, window, trigger plane, pattern suite).
This turns “tuning” into a correlated engineering loop rather than trial-and-error.
H2-11 · Validation & Production Gates
Timing must graduate from “bench numbers” to “production-grade evidence.” A gate is only useful when it freezes measurement context, proves corner coverage, and ships with an auditable evidence pack (configs, plots, logs, and limits).
The three stages below convert delay/skew/jitter from a design discussion into a repeatable release process. Each stage defines:
normalization rules, pass criteria placeholders (X/Y/N), and required artifacts for traceability.
Bring-up
Goal
Establish a correlated baseline: the same setup must produce the same timing numbers across benches.
Normalization (must freeze)
- Bandwidth and filtering declared
- Trigger reference plane declared
- Short + long windows (tail + average)
- Pattern suite defined (even if minimal)
Pass criteria (placeholders)
- Baseline jitter ≤ X (RMS) under Y condition
- Skew Δt ≤ X across N lanes
- Correlation delta ≤ X between benches
Evidence pack
- Setup screenshots: BW / trigger / windows
- Reference-plane diagram and pad map
- Baseline report version (frozen)
EVT / DVT
Goal
Close the system budget across corners: Source / Isolation / Receiver ownership remains consistent under stress.
Coverage (corner matrix)
- Temperature and supply corners
- Mode corners (encode/recovery behaviors)
- Stress events (system switching / dv/dt context)
- Realistic traffic plus defined stress patterns
Pass criteria (placeholders)
- Residual margin ≥ X at corner Y
- Bounded behavior within X under stress Y
- No mode-specific outlier beyond X
Evidence pack
- Corner matrix sheet (tested vs planned)
- Budget alignment log (before/after knobs)
- Failure triage notes (link to pitfall/knob steps)
Production
Goal
Convert EVT/DVT results into production limits using correlated proxy metrics and fixed fixtures.
Productionization
- Fixed fixture and cabling (versioned)
- Golden unit + periodic re-correlation
- Proxy metrics selected for strong correlation
- Limit versioning and change control
Pass criteria (placeholders)
- Proxy metric within X (per unit)
- Golden correlation within X (per shift)
- Fail handling: retest / quarantine / tag (N)
Evidence pack
- Fixture BOM + revision label
- Golden calibration record
- Sampling plan: rate / count (X/Y)
Reference BOM (example part numbers for gate correlation)
Use a small, fixed DUT set as “golden correlation anchors” so that jitter/skew/delay reports stay comparable across Bring-up → EVT/DVT → Production.
The items below are representative isolation parts used for timing-sensitive validation.
Low-jitter / high-speed differential isolation
ADN4654 / ADN4655 / ADN4656 (ADI iCoupler LVDS gigabit isolators)
Role in gates: provides a repeatable “clock/data-grade” isolation anchor for jitter and skew correlation in high-speed paths.
Multi-channel CMOS isolation anchor
ISO7741 (TI quad-channel digital isolator family)
Role in gates: provides a stable multi-lane baseline for channel-to-channel skew and delay drift correlation across PVT corners.
Wide channel-count family for “lane grouping” checks
Si86xx family (Skyworks / Silicon Labs digital isolators)
Role in gates: supports grouping/mixed-direction scenarios to verify that skew control and normalization rules hold when lane count increases.
Gate usage rule: keep the reference DUT set fixed (same part numbers, same board/fixture rev). If a part number changes, the baseline must be rebuilt and re-correlated before limits move.
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H2-12 · FAQs
These FAQs close out review, acceptance, and field disputes without expanding scope. Each answer is a fixed 4-line, audit-friendly structure with measurable placeholders (X/Y/N).
1) Datasheet jitter looks OK, but JESD still fails — what must be normalized first?
Likely cause: Jitter definition mismatch (bandwidth/window/trigger plane/pattern) hiding bounded or mode-specific behavior.
Quick check: Re-measure with frozen bandwidth and window; align trigger to the same reference plane; run the agreed pattern suite.
Fix: Standardize the measurement context across benches/labs; report RMS and bounded components separately under the same stimulus.
Pass criteria: Additive jitter ≤ X (RMS) within Y bandwidth, and bounded component ≤ X under N pattern modes.
2) Clock phase-noise looks clean, but ENOB/SFDR drops — what timing assumption is usually wrong?
Likely cause: The “clean” metric is taken at a different reference plane than the sampling point; distribution tail or deterministic steps are not captured.
Quick check: Measure at the receiver sampling plane with the same trigger and window; compare tail metrics (not only average/RMS).
Fix: Lock the acceptance plane and include a tail/bounded check alongside RMS; correlate with a fixed stress pattern set.
Pass criteria: Tail/bounded timing error ≤ X at corner Y, with correlation delta ≤ X across N repeats.
3) Same DUT, different labs disagree — what is the fastest correlation checklist item?
Likely cause: Measurement context mismatch (bandwidth limit, counter window, trigger plane, or fixture/cable revision).
Quick check: Compare the four headers: bandwidth, window, trigger plane, pattern suite; confirm fixture and cable rev match.
Fix: Freeze a single “acceptance recipe” and require it in every report; use a golden unit to re-correlate before judging results.
Pass criteria: Lab-to-lab delta ≤ X under identical recipe, with golden correlation within X over Y minutes and N runs.
4) Scope eye looks better after a setup change, but BER worsens — what measurement side effect is likely?
Likely cause: Probe loading or bandwidth change reshaped edges/ISI, making the displayed eye look wider while tail errors increased.
Quick check: Re-run with a low-loading differential probe and a fixed bandwidth; compare BER tail under the same pattern suite.
Fix: Treat the probe/fixture as part of the channel; standardize probing and bandwidth before comparing eye vs BER.
Pass criteria: Under the frozen setup, BER tail ≤ X over Y bits and eye margin meets X at N repeated runs.
5) Skew meets spec, but eye margin shrinks — what is most likely mismatched in the definition?
Likely cause: Skew measured as mean delay offset while the system is sensitive to edge-to-edge alignment or mode-dependent bounded steps.
Quick check: Measure skew at the same threshold/edge sense and reference plane; separate mean skew from bounded/mode steps.
Fix: Align skew definition to the system timing ruler (edge/threshold/mode); report skew and jitter separately, not as one number.
Pass criteria: Mean skew ≤ X and bounded step ≤ X under mode set N at corner Y.
6) Skew passes at room temp, fails at corners — is it skew drift or jitter growth first?
Likely cause: PVT-driven drift shifts channel alignment (skew drift) before random spread dominates; the failure looks like “jitter” if windows are too long.
Quick check: Track mean delay per lane vs temperature/voltage; compare short-window edge alignment before evaluating RMS spread.
Fix: Budget skew drift as a separate term and verify it at corners; then evaluate jitter on top using the same window/bandwidth.
Pass criteria: Skew drift ≤ X across corner sweep Y, and RMS jitter increase ≤ X within Y bandwidth for N lanes.
7) Clock path passes, data path fails — which timing ruler likely got mixed (fs–ps vs UI)?
Likely cause: Clock evaluated with tight jitter metrics while data was judged with a different window/pattern, or UI-based margin assumptions were applied to clock-grade paths.
Quick check: Confirm the same reference plane and pattern suite for data; ensure clock is evaluated by jitter while data is evaluated by UI/BER using consistent windows.
Fix: Split acceptance: clock uses jitter/tail metrics; data uses UI/BER metrics; keep the measurement recipe consistent within each.
Pass criteria: Clock additive jitter ≤ X (RMS) and data BER tail ≤ X over Y bits under N patterns.
8) Data path passes, but clock isolation fails sampling performance — what should be checked before touching the isolator?
Likely cause: Reference plane or window mismatch hides clock-path tail behavior; supply/return coupling injects deterministic steps under system switching.
Quick check: Re-check clock at the receiver plane with fixed bandwidth/window; repeat under the defined switching stress condition.
Fix: Normalize clock measurement context first, then apply supply isolation/edge shaping knobs before concluding an isolator-class limitation.
Pass criteria: Under stress Y, clock tail/bounded error ≤ X for N cycles and correlation delta ≤ X across repeats.
9) Jitter worsens only under switching stress — first adjust supply isolation or edge-rate control?
Likely cause: Supply/return coupling modulates threshold crossing or recovery timing; edge-rate changes may mask symptoms but not remove the coupling source.
Quick check: Correlate jitter excursions with supply ripple or ground bounce during the same stress event using the same trigger/window.
Fix: Prioritize supply isolation/return integrity first; then tune edge-rate only after the supply-coupling term is reduced.
Pass criteria: Under stress Y, jitter increase ≤ X (RMS) and bounded step ≤ X across N events.
10) Improving edge-rate reduces EMI but breaks timing — what knob sequencing avoids false conclusions?
Likely cause: Edge shaping changed the timing ruler (threshold crossing distribution) without re-normalizing the acceptance measurement context.
Quick check: Re-run the same measurement recipe after each knob step; compare mean delay, skew, and bounded behavior separately.
Fix: Apply one knob at a time; lock bandwidth/window/trigger/pattern; only then decide whether timing or EMI improved.
Pass criteria: After knob step, skew ≤ X and jitter ≤ X under Y context, with correlation delta ≤ X over N runs.
11) Bring-up passes, EVT/DVT fails — what evidence pack item is usually missing or inconsistent?
Likely cause: The acceptance recipe was not frozen (fixture/cable rev, trigger plane, bandwidth/window, or pattern suite drifted across stages).
Quick check: Diff the evidence packs: recipe headers + fixture rev + golden correlation record; identify what changed between stages.
Fix: Enforce stage gate: EVT/DVT must reuse the bring-up recipe or formally re-baseline with a golden unit before changing limits.
Pass criteria: Recipe delta = 0 (or approved change), and golden correlation within X across Y minutes and N repeats.
12) Production proxy passes, but field failures happen — what gate link is most likely broken first?
Likely cause: Production proxy metric lost correlation to the true timing failure mode (pattern/mode/stress not represented in production test).
Quick check: Re-run field-return units through EVT/DVT stress patterns under the frozen recipe; compare proxy vs true tail/bounded metrics.
Fix: Update the production proxy to cover the missing mode/stress; re-baseline limits with golden correlation before rollout.
Pass criteria: Proxy-to-truth correlation ≥ X across N units, and field-mode tail metric ≤ X under stress Y.
FAQ usage: In disputes, normalize context first (bandwidth/window/trigger plane/pattern), then apply budgeting and knobs.
This prevents “spec-correct but system-fail” arguments from looping without evidence.
