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Push-Pull / Half-Bridge / Full-Bridge Isolated DC-DC

Push-Pull / Half-Bridge / Full-Bridge Isolated DC-DC

← Back to: Digital Isolators & Isolated Power

Core Idea

Push-Pull / Half-Bridge / Full-Bridge isolated converters are the workhorse choice for medium-to-high power rails when efficiency, low ripple, and production robustness must be proven together. This page turns topology selection into measurable design evidence—timing windows, magnetics losses, EMI paths, thermal margin, and fault behavior—so the power stage can ship with clear pass criteria.

Definition & When to Use These Topologies

Scope Medium-to-high power isolated DC-DC built around Push-Pull, Half-Bridge, and Full-Bridge stages—optimized for scalable power, controllable EMI, and low ripple rails with synchronous rectification options.

Key outcomes this page targets

  • Efficiency: Meet target efficiency of X% at Y W across VIN = A–B, with predictable light-load behavior (define policy: skip/burst/forced-PWM as applicable).
  • Ripple & noise: Keep output ripple within X mVpp (define bandwidth and probe method), and prevent commutation spikes from dominating analog/control rails.
  • Thermal headroom: Maintain hot-spot rise within ΔT ≤ X°C at Tamb = Y°C, including transformer copper/AC-loss and rectifier conduction loss.
  • EMI containment: Control common-mode and differential-mode paths (switch-node dv/dt, transformer capacitance, rectifier commutation) to achieve pre-compliance margin of X dB (test setup defined).
  • Production robustness: Tolerate magnetics/process spreads (leakage, turns, gap, winding capacitance) without crossing protection thresholds or losing stability.

Quick “choose this if…” routing

Push-Pull
  • Power needs exceed typical single-ended comfort, while preserving a relatively simple, symmetric primary stage.
  • Transformer utilization and scalability matter, and design control can prevent long-term imbalance (flux-walk).
  • System accepts additional validation gates for symmetry, current balance, and reset margin.
Half-Bridge
  • A balanced choice is needed between complexity and performance for mid-to-high power rails.
  • Common PWM/current-mode controller ecosystems are preferred, with manageable device stress and good EMI control.
  • Design can accommodate bus capacitor midpoint behavior and layout-driven commutation loops.
Full-Bridge
  • Highest scalability is required (higher power, higher current), with strong motivation to distribute conduction loss.
  • Control flexibility is valued (PWM or phase-shift families), especially when switching behavior and EMI must be tightly engineered.
  • Higher component count and bring-up complexity are acceptable for better headroom at power extremes.

Do / Don’t (scope guard)

Do use this page when the design must deliver scalable isolated power with controlled ripple/EMI and production-ready robustness.
Don’t use this page as a deep tutorial for other families: Flyback/QR Flyback, Resonant (LLC), PoE isolated PD converters, Isolated power modules. Those topics should be handled on their dedicated sub-pages (link-only here).

Decision Gateway (Medium/High-Power Isolated DC-DC) Input conditions Power level VIN range Ripple / noise target Isolation class Cost / complexity Pick topology family by constraints and scaling needs Push-Pull • symmetric stage • scalable power • manage imbalance Half-Bridge • balanced complexity • common control • solid EMI control Full-Bridge • best for high power • flexible control • higher complexity Note: Other families (Flyback/Resonant/PoE/Modules) are link-only from this page to avoid scope overlap.
Diagram intent: route designs by constraints (power, VIN, ripple, isolation class, cost) into the most suitable bridge-family topology without expanding into sibling topics.

Topology Snapshot: Push-Pull vs Half-Bridge vs Full-Bridge

Shared vocabulary used throughout the rest of this page

  • Switch Network: the primary-side switching stage that applies an AC excitation to the transformer (defines dv/dt and commutation loops).
  • Transformer utilization: how effectively core/window/copper convert switching action into delivered power (impacts RMS currents and thermal).
  • Stress profile: the dominant V/I stresses borne by switches, transformer windings, and rectifiers (drives device rating and snubber needs).
  • Core reset / imbalance: how the transformer avoids flux accumulation (especially critical for symmetric topologies where small mismatches can accumulate).
  • Control friendliness: how naturally the topology pairs with PWM or phase-shift families and how it behaves at light load/min duty constraints.

Engineering snapshot (fixed fields per topology)

Push-Pull

Best fit: mid-to-high power rails where a symmetric excitation is attractive and transformer utilization is a priority.

Main stress: sensitive to imbalance-driven flux accumulation; RMS winding currents and switching transitions dominate heat/EMI.

Key pitfall: flux-walk from drive asymmetry or duty clamp mismatch → transformer heating/saturation risk.

Typical control style: PWM families with careful symmetry validation and current-sense hygiene.

First bring-up check: confirm primary current symmetry over many cycles (no slow drift; margin ≥ X%).

Half-Bridge

Best fit: mid-to-high power where complexity must be bounded while improving scalability and EMI control versus simpler families.

Main stress: commutation loop integrity and bus-cap midpoint behavior; dv/dt at the switch node drives CM noise paths.

Key pitfall: layout-driven ringing and midpoint instability → SR false triggering, EMI spikes, or control noise injection.

Typical control style: PWM/current-mode controllers with clear duty limits and well-defined light-load policy.

First bring-up check: verify switching node ringing and midpoint stability across load steps (peak overshoot ≤ X%).

Full-Bridge

Best fit: high power scalability and current sharing, with stronger motivation to distribute conduction loss and improve headroom.

Main stress: drive timing and commutation management across four switches; transformer RMS currents and rectifier transitions dominate loss.

Key pitfall: loss of desired commutation behavior at light load (e.g., ZVS window collapse) → higher loss/EMI.

Typical control style: PWM or phase-shift families, chosen based on efficiency/EMI priorities and magnetics constraints.

First bring-up check: validate commutation evidence vs load (switching loss trend monotonic; margin ≥ X).

Power-Stage Anatomy (Block-View, Not a Schematic) Push-Pull Half-Bridge Full-Bridge Switch Network Isolation Barrier Transformer Rect (Diode/SR) Output LC & Rails Switch Network mid Isolation Barrier Transformer Rect (Diode/SR) Output LC & Rails Switch Network Isolation Barrier Transformer Rect (Diode/SR) Output LC & Rails All three share the same backbone: switching network → isolation transformer → rectification (diode/SR) → output LC; differences are in stress distribution and control options.
Diagram intent: keep the discussion at “engineering block-view” level to define shared language for later chapters (timing, magnetics, SR, EMI, control, and production gates).

Operating Principle & Timing Waveforms You Must Budget

Why timing matters In bridge-family isolated DC-DC, most “mystery” failures trace back to timing windows: dead-time, commutation intervals, phase shift behavior, and SR conduction windows. If these windows are not budgeted, efficiency, thermal, EMI, and stability will degrade together.

Fundamental switching intervals (what happens when)

  • Energy transfer window: transformer sees an applied primary excitation; current ramps and energy moves to the secondary through the rectification path.
  • Commutation interval: current transfers between devices and parasitics; this is where overshoot/ringing and EMI are usually generated.
  • Dead-time: prevents cross-conduction. Too short risks shoot-through; too long increases body-diode conduction, loss, and stress.
  • Phase-shift (PSFB, if used): effective power control is set by phase offset between bridge legs; commutation windows become the critical control variable rather than simple PWM duty alone.
  • Secondary conduction window: defines when SR (or diodes) should conduct; incorrect SR timing causes reverse current, extra heating, or false turn-on under ringing.

Dead-time, cross-conduction risk, and commutation paths

  • Cross-conduction risk: occurs when high-side and low-side of the same leg overlap. Evidence is a sharp current spike synchronized with gate transitions.
  • Commutation loop control: the shortest, tightest high-di/dt loop reduces ringing and overshoot. Poor loops shift the burden to snubbers and increase EMI.
  • Dead-time trade: increasing dead-time reduces overlap risk but increases diode conduction (loss + recovery stress). Budget both minimum and maximum dead-time.

Timing budget checklist (fill X / Y / N with project thresholds)

Primary timing guards

  • Dead-time min: t_dead(min) ≥ X ns (no cross-conduction evidence).
  • Dead-time max: t_dead(max) ≤ Y ns (limit diode conduction + recovery stress).
  • Overshoot cap: Vds/Vsw peak ≤ X% of rating at worst-case VIN/load.
  • Ringing settle: ring-down ≤ Y ns before the next critical edge or SR enable.

Secondary (SR) timing guards

  • SR overlap: SR1 & SR2 overlap ≤ X ns (prevent shoot-through on secondary).
  • SR turn-off margin: SR late-off margin ≥ Y ns (avoid reverse current/re-circulation heating).
  • False-on immunity: SR gate disturbance stays below threshold by X mV margin during ringing.
  • Conduction window alignment: SR on/off fully contained within secondary conduction window with margin ≥ N.

PSFB-only (if applicable)

  • Phase-shift range: control operates within a stable phase window: φ ∈ [X, Y] across expected load range.
  • Commutation evidence: desired commutation behavior remains visible down to X% load (define evidence marker).
  • Transition loss trend: switching loss does not spike unexpectedly during load steps (define acceptable delta ≤ X).

First bring-up waveforms (minimum evidence set)

  • Primary switch node (Vsw/Vds): capture overshoot and ringing; confirm ring-down timing vs SR enabling.
  • Primary current (Ip): confirm commutation cleanliness and no slow drift (early sign of imbalance).
  • SR gates (Vgs) + SR drains (Vds): verify SR timing, overlap, and reverse-current behavior.
  • Output ripple measurement: define bandwidth and probing method; enforce a consistent measurement “pass criteria” (X mVpp over Y MHz).
  • Transformer current direction cue: confirm current direction flips align with expected commutation windows (diagram below).
Timing Lanes (Budget Dead-Time + SR Windows) Q1 Q2 SR1 SR2 Dead-time Ip direction cue Budget rule: SR windows must stay inside the valid secondary conduction window, with margin on both edges.
Diagram intent: show the minimum timing relationships to budget—no Q1/Q2 overlap (dead-time), SR window alignment, and a current-direction cue for commutation sanity checks.

Transformer & Magnetics Design for Medium/High Power

Core message Magnetics determine efficiency, thermal limits, EMI coupling, and production consistency. A correct topology can still fail if turns ratio, leakage, AC copper loss, and winding capacitance are not co-designed.

Design steps (ratio → core → leakage → winding → thermal)

  • Step 1 — Turns ratio from VIN/VOUT and duty constraints: choose Np:Ns to keep control within a safe duty/phase window across VIN extremes (budget Dmin/Dmax or φ range as X/Y).
  • Step 2 — Core selection (material/size/B-margin): pick material and core size so peak flux stays below target: Bpk ≤ X T at worst-case operating point; validate loss vs switching frequency and temperature.
  • Step 3 — Leakage inductance plan: decide whether leakage is purely an enemy (spikes/EMI) or can be partially beneficial (commutation behavior). Set a measurable target: L_leak ≤ X or within [X, Y].
  • Step 4 — Winding strategy (AC loss mitigation): select foil vs litz vs multi-strand; use interleaving/split windings to reduce leakage but monitor the increase in winding-to-winding capacitance (C_ps).
  • Step 5 — Thermal and process robustness: identify hot spots (ends, window crowding, leads) and define production-critical characteristics (turns, spacing, shield termination, impregnation consistency).

Leakage inductance and capacitance: friend vs enemy

  • Leakage (L_leak) as enemy: creates overshoot, ringing, and extra dissipation; often demands stronger clamps/snubbers and increases EMI.
  • Leakage (L_leak) as friend (case-dependent): may support controlled commutation behavior in some bridge control styles; still requires strict timing and validation evidence.
  • Winding capacitance (C_ps): forms the main common-mode coupling path. Lower C_ps often improves EMI but can conflict with leakage goals; co-design is mandatory.

Pitfalls that most often break designs

Saturation / flux walk

  • Symptom: heating rises sharply; current waveform distorts; protection triggers early.
  • Mechanism: Bpk margin too small or long-term imbalance accumulates flux.
  • Fast check: compare primary current symmetry over time; confirm no slow drift.
  • Fix direction: adjust ratio/window, increase core margin, enforce symmetry gates, revisit drive/timing.

Hot spots / AC copper loss

  • Symptom: localized heating at winding ends/leads; efficiency drops more than expected.
  • Mechanism: skin/proximity effects + window crowding; RMS current higher than assumed.
  • Fast check: IR/thermocouple mapping under steady load; identify hot-spot location.
  • Fix direction: winding geometry change (foil/litz/split), reduce AC field concentration, improve window utilization.

Insulation stack-up and EMI coupling

  • Symptom: CM EMI unexpectedly high; behavior changes with cable/ground.
  • Mechanism: large C_ps couples primary dv/dt into secondary reference.
  • Fast check: correlate EMI peaks with switch-node edges; measure C_ps proxy if possible.
  • Fix direction: revise layering/spacing, consider shield layer with controlled termination, reduce dv/dt where allowed.

Process variation (production drift)

  • Symptom: same BOM behaves differently across builds; thermal and EMI spread is large.
  • Mechanism: leakage/spacing/shield termination variability; impregnation and winding tension differences.
  • Fast check: define KPCs and measure L_leak / turns / temperature rise per lot.
  • Fix direction: tighten magnetics spec, add incoming inspection gates, lock winding recipe and termination rules.
Transformer Cross-Section (Parasitics Drive EMI + Spikes) Window / stack-up P ISO SHIELD S L_leak C_ps CM path Primary dv/dt C_ps Secondary ref Cable / chassis Trade reminder: interleaving typically lowers L_leak but increases C_ps; shield layers can reduce CM noise if termination rules are consistent.
Diagram intent: visualize the stack-up (P / ISO / optional SHIELD / S) and the two parasitics that dominate behavior—L_leak (spikes/commutation) and C_ps (common-mode EMI coupling path).

Primary Power Devices & Drive Strategy

Scope guard This section focuses on primary power devices and drive strategy inside bridge-family isolated DC-DC. Protection features typically covered in gate-driver topics (e.g., DESAT, Miller clamp) are link-only here: Isolated Gate Driver.

Device selection knobs (choose by evidence, not by headline specs)

  • Voltage headroom: size Vds/Vce with measured overshoot margin, not only VIN. Target: V_peak ≤ X% of rating at VIN=Y, load=Z.
  • Qg vs switching loss: higher Qg increases gate-drive loss and can slow edges; slower edges reduce EMI but raise switching loss. Budget: P_gate ≤ X W, t_r/t_f within [Y, Z].
  • Coss/Crss sensitivity: Crss couples dv/dt into the gate loop. Layout + gate shaping must prevent false turn-on. Margin: Vgs_noise ≤ X mV below threshold.
  • Body diode / Qrr (MOSFET cases): reverse recovery increases commutation stress and overshoot. Evidence: ΔV_overshoot ≤ X V, ring settles ≤ Y ns.
  • Package & thermal: prefer packages that support Kelvin source/emitter for clean gate return. Thermal proof: ΔT_hotspot ≤ X°C at Y W.

Gate drive loop (make it a local, quiet loop)

  • Local loop closure: driver → gate → device → Kelvin return should be the smallest loop on the board.
  • Kelvin return priority: gate return must not share impedance with the power commutation return path.
  • Gate shaping knobs: use R_on / R_off split (diode separation) to independently tune EMI vs turn-off overshoot.
  • Placement rule: place the driver closest to the gate pins; keep sensitive traces away from the primary switching node.
  • Bring-up proof: capture Vgs + Vds together at the device pins; confirm no false turn-on during ringing.

Snubbers & clamps (what each one actually solves)

Ringing control

  • Tool: RC snubber near the high dv/dt node.
  • Goal: reduce high-frequency ring amplitude and settle time.
  • Trade: adds loss; may heat locally.
  • Pass criteria: ring amplitude ≤ X, ring-down ≤ Y ns.

Spike limiting

  • Tool: TVS / RCD clamp / active clamp (as applicable).
  • Goal: cap overshoot and protect device headroom.
  • Trade: energy must be handled (thermal + efficiency hit).
  • Pass criteria: V_peak reduction ≥ X%, clamp loss ≤ Y W.

Startup / soft-start implications

  • Stress window: early cycles can have abnormal duty/phase and magnetizing current; overshoot may be worse than steady-state.
  • Proof: capture Vds/Vsw peak and primary current during startup; enforce a startup peak limit: V_peak,start ≤ X% of rating.
  • Policy: ramp limits and clamp sizing must be validated at VINmax and worst-case load transitions.

3 loops you must keep tight (layout decides the waveform)

Gate loop
  • Driver close to gate pins; shortest trace pair.
  • Gate return uses Kelvin source/emitter.
  • Measure Vgs at device pins (avoid misleading probes).
Commutation loop
  • Switch + bus cap + transformer primary = smallest loop area.
  • High di/dt return never shares with sensitive control ground.
  • Place local decoupling at the power devices.
Clamp loop
  • Clamp must sit at the spike source, not far away.
  • Clamp return path must be a tight local loop.
  • Energy sizing: E_clamp ≥ X mJ per event (budget).
Loop Map (Keep These Three Loops Tight) Switch Network Bus Caps Transformer Isolation Clamp Gate Driver High dv/dt High di/dt Gate loop Commutation loop Clamp loop Diagram intent: visualize the three dominant loops that shape stress and EMI—tight loops win more than “stronger parts.”
Diagram intent: highlight the three loops that must be physically small (gate loop, commutation loop, clamp loop) and the regions of high dv/dt and high di/dt that drive stress and EMI.

Secondary Rectification: Diode vs Synchronous Rectification

Core goal Synchronous rectification (SR) can materially improve efficiency and thermal headroom in low-voltage, high-current rails. The benefit comes with timing and noise-immunity requirements that must be verified on the bench.

When SR matters (use clear thresholds)

  • High output current: diode conduction loss dominates when Iout is high and Vout is low. Trigger: P_diode_cond ≥ X W at Iout=Y A.
  • Efficiency target is tight: SR is justified when expected gain ≥ X% at the main operating point.
  • Thermal headroom is limited: SR can reduce rectifier heat, but requires clean timing and layout to avoid new failure modes.
  • Light-load share is large: SR may need a policy below X% load to avoid reverse current and noise-triggered behavior.

SR control methods (timing reference is the key)

Self-driven SR

  • Reference: secondary waveform (transformer/rectifier node) provides natural timing.
  • Strength: simple and fast (minimal latency).
  • Risk: ringing and threshold sensitivity can cause false turn-on, especially at light load.

Controller-driven SR

  • Reference: controller timing aligned to primary commutation and expected secondary conduction window.
  • Strength: supports adjustable dead-time and light-load policy.
  • Risk: misalignment or noise injection can cause overlap or late turn-off reverse current.

Common SR failure modes (what to check first)

SR shoot-through (overlap)

  • Symptom: rectifier heating spikes; efficiency collapses; current spikes appear at transitions.
  • Mechanism: SR1 and SR2 overlap or a device turns on during the opposite conduction interval.
  • Quick check: overlap in Vgs waveforms; abnormal low Vds during overlap window.
  • Fix direction: increase dead-time, improve gate-loop immunity, reduce ringing at commutation nodes.

Reverse current at light load

  • Symptom: light-load efficiency worse than diode; SR devices heat despite small load.
  • Mechanism: SR remains on after current crosses zero, allowing reverse conduction.
  • Quick check: correlate inductor/secondary current polarity with SR gate timing.
  • Fix direction: add light-load SR policy, improve turn-off margin, align SR window to the true conduction interval.

Ringing-induced false turn-on

  • Symptom: intermittent behavior across layout/cable/temperature; EMI and heating worsen together.
  • Mechanism: dv/dt + parasitic coupling lifts Vgs above threshold during ringing.
  • Quick check: Vds ringing and Vgs bumps line up in time.
  • Fix direction: gate damping, tighter commutation loop, clamp/snubber to reduce ringing amplitude and settle time.

Ripple dominated by commutation

  • Symptom: output ripple spikes correlate with rectifier transitions.
  • Mechanism: rectifier commutation + layout inductance injects spikes into output LC.
  • Quick check: compare ripple timing vs SR transitions; use consistent probing method.
  • Fix direction: refine SR timing, tighten secondary commutation loop, improve output current return paths.

SR bring-up checklist (3 waveforms + pass criteria placeholders)

Waveform set (minimum)

  • SR Vgs: verify clean gate drive and noise margin.
  • SR Vds: verify correct conduction window and commutation behavior.
  • Secondary/inductor current: verify polarity and zero-cross timing.

Pass criteria (fill X/Y/N)

  • SR overlap ≤ X ns.
  • Reverse current peak ≤ Y A (or duration ≤ N ns).
  • Vgs noise stays ≥ X mV below threshold during ringing.
  • Ringing settles ≤ Y ns before SR enable edge.
Secondary Commutation (SR Windows + Reverse Current Risk) SR1 SR2 Isec Dead-time Overlap Reverse current risk zone (light load / late SR turn-off / ringing-induced false-on) Budget rule: SR must turn off before current reverses; overlap must stay below the defined ns threshold.
Diagram intent: visualize SR1/SR2 conduction windows, dead-time, overlap risk, and the region where reverse current is most likely if SR timing is late or noise-triggered.

Control Methods & Compensation (PWM, Current-Mode, Phase-Shift)

Scope guard This section focuses on loop behavior, compensation targets, and sense-path integrity for bridge-family isolated DC-DC. Device-level protection features and driver IC comparisons are link-only: Gate Driver / Quick Pairings.

Control family mapping to topologies (what’s typical and why)

Push-Pull
  • Typical: PWM, peak current-mode.
  • Why: straightforward modulation, common controllers.
  • Loop risk: duty imbalance → flux walk evidence over time.
  • First proof: primary current symmetry + no slow drift.
Half-Bridge
  • Typical: PWM, peak/average current-mode.
  • Why: clean plant behavior and sensing options.
  • Loop risk: sense noise + filtering phase-lag traps.
  • First proof: stable crossover under worst noise conditions.
Full-Bridge
  • Typical: PWM or phase-shift (PSFB).
  • Why: scalable power, flexible modulation.
  • Loop risk: phase-shift dynamics vary with load region.
  • First proof: transient + margins across load sweep.

Current sense options (accuracy vs noise vs delay)

Shunt

  • Strength: direct, wide bandwidth.
  • Risk: switching noise injection via shared impedance.
  • Layout rule: Kelvin pick-off; route sense away from switching node.
  • Proof: sense ripple stays below X mV at worst-case dv/dt.

CT (current transformer)

  • Strength: isolation-friendly, good bandwidth.
  • Risk: reset/saturation and baseline drift at low frequency.
  • Layout rule: tight loop through CT; defined reset path.
  • Proof: baseline drift ≤ X% over Y ms.

Lossless (DCR / Rds_on proxy)

  • Strength: low dissipation.
  • Risk: temperature dependence and nonlinearity.
  • Layout rule: stable reference routing; minimize pickup.
  • Proof: loop behavior stays within X% across temperature sweep.

Noise filtering without phase-lag traps

  • Rule: do not “fix” noise by pushing a dominant filter pole near crossover.
  • Budget: sense filter pole ≥ X × f_c to avoid phase margin collapse.
  • Proof: margins remain ≥ PM: X° and GM: Y dB with noise present.

Compensation goals (translate specs into loop targets)

  • Crossover target: choose f_c to balance speed and robustness. Budget: f_c ≤ X × f_sw and within plant validity window.
  • Stability margins: phase margin PM ≥ X°, gain margin GM ≥ Y dB across VIN/load sweep.
  • Transient translation: step response target: ΔVout ≤ X% for a load step of Y A, settle time ≤ Z µs.
  • Sampling delay: any sense/ADC/filter delay must be included in the phase budget; verify with worst-case noise and temperature.

Special cases that frequently break loops

Subharmonic risk (peak current-mode)

  • Trigger: duty enters a region where cycle-to-cycle stability requires slope compensation.
  • Evidence: alternating peak current or “period-2” behavior.
  • Gate: no alternating waveform at worst-case VIN and load; threshold: alternation ≤ X%.

Flux walk (push-pull imbalance)

  • Trigger: systematic duty/timing mismatch or asymmetric sense/drive delays.
  • Evidence: primary current average drifts over time; heating rises unexpectedly.
  • Gate: symmetry metric within X% over Y s.

Phase-shift dynamics (PSFB)

  • Trigger: effective modulation behavior changes with load region.
  • Evidence: same compensation behaves differently at light vs heavy load.
  • Gate: margins and transient targets hold across load sweep.

Duty/phase limitation

  • Trigger: controller saturates near duty/phase limits.
  • Evidence: clipped control command, slower transient, unexpected overshoot.
  • Gate: no persistent limiting during nominal steps; limit-hit rate ≤ X.

Loop design “gates” (evidence-based workflow)

Gate A · Plant ID
  • Identify dominant poles/zeros from response data.
  • Include sense/filter delay in the model.
  • Pass: ID error ≤ X%, key poles in [Y, Z].
Gate B · Margins
  • Verify PM/GM at worst-case VIN/load.
  • Confirm crossover within safe fraction of f_sw.
  • Pass: PM ≥ X°, GM ≥ Y dB, f_c ≤ Z × f_sw.
Gate C · Transient
  • Run load-up and load-down steps.
  • Check limiting and abnormal oscillation evidence.
  • Pass: ΔV ≤ X%, settle ≤ Y µs, no subharmonic evidence.
Control Block Diagram (Plant + Sense Path + Noise Injection) Compensator PWM / PS Modulator Gate Drive Plant Power Stage Sense Filter (phase budget) Switch node noise Sense noise Comp path Sense path Diagram intent: show where phase budget is spent (sense/filter delay) and where noise couples into the loop.
Diagram intent: map the closed-loop path (Comp → Modulator → Drive → Plant) and the sense/filter chain where phase-lag and noise injection commonly break stability.

EMI, Noise, and Ripple: System-Level Co-Design

Scope guard This section focuses on EMI/noise paths and practical design knobs in medium/high-power isolated DC-DC. Detailed leakage-current limits and standard clauses are application-specific and are link-only: Safety & Compliance / Medical HMI.

Dominant EMI sources (identify the main offenders first)

  • Primary switch dv/dt: fast edges drive common-mode displacement current through parasitics.
  • Transformer capacitance (C_ps): couples primary dv/dt into the secondary reference and cables.
  • Rectifier commutation: secondary switching transitions inject spikes into output return paths.
  • Return-path/plane coupling: shared impedance converts high di/dt loops into noise on control and chassis references.

CM vs DM paths (break the path, not just the symptom)

Common-mode (CM)

  • Driver: switch node dv/dt + C_ps.
  • Path: primary → C_ps → secondary ground → cable/chassis.
  • Break points: shield layer, edge-rate control, layout split/return control.

Differential-mode (DM)

  • Driver: commutation di/dt loops on primary/secondary.
  • Path: loop area + input/output wiring.
  • Break points: loop minimization, local decoupling, filter partitioning.

EMI knobs list (each knob: helps / hurts / first check)

Edge-rate shaping (gate resistor)

  • Helps: lower dv/dt → CM emissions drop.
  • Hurts: switching loss and heat rise.
  • First check: EMI peaks align with Vsw edges; quantify slope vs loss.

RC snubber (switch node)

  • Helps: reduces ringing amplitude and settle time.
  • Hurts: dissipates power locally.
  • First check: ring-down ≤ X ns before sensitive timing edges.

Clamp loop quality

  • Helps: caps overshoot and stabilizes stress.
  • Hurts: a large clamp loop becomes an antenna.
  • First check: clamp placed at spike source; smallest return loop.

Transformer shield layer

  • Helps: cuts CM coupling via C_ps.
  • Hurts: wrong termination can worsen coupling.
  • First check: shield termination node (primary/secondary/chassis policy).

Y-cap (link-only limits)

  • Helps: provides CM return path to reduce emissions.
  • Hurts: leakage current constraints depend on standards/applications.
  • First check: placement and return path length; validate leakage policy elsewhere.

Filter partitioning

  • Helps: isolates noise source from external wiring.
  • Hurts: can interact with control/input impedance if done blindly.
  • First check: compare noise pre/post filter; ensure no new oscillation evidence.

Layout split & return control

  • Helps: prevents shared-impedance noise injection.
  • Hurts: bad splits create long loops and radiators.
  • First check: high di/dt loops remain local; no cross-gap return.

Measurement method (pitfall control)

  • Helps: correct diagnosis and correct knob selection.
  • Hurts: long ground leads create fake spikes.
  • First check: use ground spring + bandwidth definition; repeatability ≤ X%.

Output ripple: where it really comes from (and how not to lie to yourself)

  • Commutation spikes: tied to rectifier transitions and loop inductance. First fix: secondary commutation loop + SR timing.
  • LC ripple: tied to output filter dynamics and load. First fix: confirm measurement bandwidth and pick the correct sense point.
  • Ground bounce: probe/reference artifacts dominate if return is not controlled. First fix: ground spring and consistent reference.
  • Pass criteria placeholders: Vout ripple ≤ X mVpp over Y MHz, spike ≤ Z mV at the defined point.

Practical validation gates (system-level evidence)

Near-field + node correlation

  • Scan switching node, transformer area, cable exit region.
  • Correlate peaks with Vsw and commutation timing.
  • Pass: key peaks reduced by ≥ X dB with controlled trade-offs.

One-knob-at-a-time rule

  • Change one knob and log helps/hurts.
  • Track efficiency hit and thermal impact.
  • Pass: emissions improve while loss penalty ≤ Y%.
Noise Coupling Map (CM Path + Blocking Points) Switch node C_ps Secondary GND / ref Cable Emissions Snubber Shield Layout split DM path (loop area) High di/dt Filter Diagram intent: follow the CM path (Switch node → C_ps → Secondary GND → Cable → Emissions) and place blocking points deliberately.
Diagram intent: visualize the dominant CM coupling path through transformer capacitance and the three practical blocking points (snubber, shield, layout split/return control).

Protection, Fault Behavior, and Reliability

Scope guard This section covers converter protection behavior, recovery policy, diagnosability, and long-term reliability. Safety clause details and certification requirements are link-only: Safety & Compliance.

Protection set (define trigger → action → proof)

OCP
  • Trigger: Ipk ≥ X A (or Iout ≥ Y A).
  • Action: cycle-by-cycle / hiccup / latched (policy must be explicit).
  • Impact: limits device stress, may increase EMI if repeated restarts.
  • Proof: capture Ipri + Vsw + Vgs, confirm no abnormal heating; pass: no damage at overload for N.
OVP
  • Trigger: Vout ≥ X V (define measurement point).
  • Action: shutdown / clamp / latch (define reset condition).
  • Impact: prevents downstream damage; may stress rectifier if uncontrolled.
  • Proof: verify overshoot ≤ Y% under load-step and restart.
UVLO
  • Trigger: VIN ≤ X V or Vbias ≤ Y V.
  • Action: stop switching, enforce safe defaults.
  • Impact: avoids partial turn-on and loss runaway.
  • Proof: no chatter at brownout; hysteresis ≥ Z V (placeholder).
OTP
  • Trigger: Tj ≥ X °C or Ths ≥ Y °C (sensor policy).
  • Action: shutdown / hiccup / latch (define cool-down gate).
  • Impact: protects magnetics and silicon from accelerated aging.
  • Proof: hotspot temperature stays ≤ Z °C at rated load and ambient.

Short-circuit survival (define expectations and thermal time constants)

Short-circuit classes

  • Hard short: near output terminals, minimal wiring.
  • Remote short: cable harness adds inductance/resistance.
  • Intermittent short: contact bounce and repeated arcing behavior.

Survival pass criteria (placeholders)

  • No destructive failure during SC for X s.
  • Hotspot temperature ≤ Y °C (transformer / MOSFET / rectifier policy).
  • Restart duty ≤ N% to prevent thermal accumulation.
  • Waveform evidence: Vsw overshoot ≤ Z%, no uncontrolled ringing growth.

Fault recovery policy (hiccup timing and restart gates)

Hiccup OFF window

t_off = X ms (cool-down window).

Retry ON window

t_on = Y ms (probe window; avoid stress runaway).

Restart thresholds

VIN ≥ X V, T ≤ Y °C, Vbias ≥ Z V.

Retry count

N retries → then latched (or degrade mode) per policy.

Diagnosability Define at least one clear diagnostic signal per fault (PG / fault pin / counter flag), and keep evidence logs consistent across bring-up and production test.

Fault “truth table” (condition → action → diagnostic → pass)

Overload (OCP)
  • Condition: Ipk ≥ X
  • Action: CBC or hiccup (policy)
  • Diagnostic: fault flag + count
  • Pass: no damage; restart stable within N
Short-circuit
  • Condition: Vout ≈ 0, I limited
  • Action: hiccup OFF/ON
  • Diagnostic: PG low + SC flag
  • Pass: survive X s, hotspot ≤ Y°C
Brownout (UVLO)
  • Condition: VIN ≤ X
  • Action: stop switching
  • Diagnostic: UVLO flag
  • Pass: no chatter; restart clean when VIN ≥ Y
Over-temperature (OTP)
  • Condition: T ≥ X
  • Action: shutdown / latch
  • Diagnostic: OTP flag + timestamp
  • Pass: cool-down gate honored; no drift after restart

Long-term reliability (what actually drives aging)

  • Transformer hot-spot: sustained hot-spot temperature accelerates insulation and resin aging; define hot-spot measurement method and limit: ≤ X °C.
  • Insulation stress factors: higher electric field + temperature + repetitive surges increase aging risk; keep stress margin explicit in documentation.
  • Process consistency: winding stack-up and impregnation consistency matter; include lot traceability and build record requirements.
  • Evidence placeholders: thermal log ≥ Y min, load profile definition, failure triggers, and corrective action record format.
Fault State Machine (Trigger → Action → Recovery) Normal OCP (CBC) Hiccup OFF Retry Latched OTP (T ≥ X) Ipk ≥ X Policy t_off = X VIN ≥ X N retries Diagram intent: make fault behavior explicit (trigger thresholds, timing, retry policy) to enable diagnosable and production-ready delivery.
Fault behavior should be described as a state machine with explicit thresholds and timing placeholders, enabling consistent bring-up evidence and production diagnostics.

Engineering Checklist (Design → Bring-up → Production)

Intent Convert the bridge-converter knowledge into deliverable gates: evidence, limits, and traceability. Hi-pot/PD clause details are link-only: Safety & Compliance.

Design checklist (10–15 items)

  • Topology choice is justified by power band, stress budget, and scalability evidence (pass: meets targets with ≥ X% margin).
  • Control family is mapped to topology (PWM / current-mode / PSFB) with defined operating regions.
  • Transformer turns ratio and duty/phase limits are consistent with worst-case VIN/VOUT (pass: no saturation evidence).
  • Leakage strategy is documented (friend vs enemy) with spike/EMI plan (pass: overshoot ≤ X%).
  • SR strategy is defined (diode vs SR, self-driven vs controlled) with dead-time margin placeholders (t_dead ≥ X ns).
  • Three critical loops are constrained (gate loop / commutation loop / clamp loop) with placement rules.
  • Sense path choice is finalized (shunt/CT/lossless) with filter pole budget (pole ≥ X × f_c).
  • Loop targets are specified: f_c ≤ X × f_sw, PM ≥ Y°, GM ≥ Z dB.
  • EMI plan lists CM/DM paths and blocking points (snubber/shield/layout split) with test intent.
  • Thermal plan defines hotspot measurement method and limit (T_hotspot ≤ X °C at rated load).
  • Protection policy is explicit (CBC/hiccup/latch) with restart gates and diagnosable signals defined.
  • Documentation set includes param limits, evidence snapshots, and version-controlled design decisions.

Bring-up checklist (10–15 items)

  • Safe power-up sequence is defined (current limit, step VIN, load staging: no-load → light → rated).
  • First-capture waveforms are collected: Vsw, Ipri, Vgs, SR Vgs/Vds, Vout ripple (method defined).
  • Stress checks confirm overshoot and ringing are within placeholders (Vsw overshoot ≤ X%).
  • Timing budget is verified (dead-time, SR overlap, commutation windows; overlap ≤ Y ns).
  • Loop margins are validated at corner VIN/load (PM ≥ X°, GM ≥ Y dB).
  • Transient validation runs load-up and load-down steps (ΔV ≤ X%, settle ≤ Y µs).
  • Short-circuit behavior is verified with survival and restart duty placeholders (survive X s, duty ≤ N%).
  • UVLO/OTP behavior is checked for chatter and clean recovery gates (VIN hysteresis ≥ X V).
  • Near-field EMI pre-scan identifies top 3 hotspots and correlates with switching events.
  • Ripple measurement is repeated with correct probe method; repeatability ≤ X%.
  • Thermal soak log captures hotspot stability over X min at rated load and ambient.
  • Diagnostic signals are exercised and logged (fault flags and counters match reality).

Production checklist (10–15 items)

  • ATE points cover key rails, protection thresholds, and efficiency checkpoints with pass bands (X/Y placeholders).
  • Parameter limits are defined per lot with guard bands (Vout, I-limit, frequency/phase range).
  • Transformer traceability is enforced: vendor, lot, build recipe, and inspection records.
  • Magnetics consistency checks include leakage/inductance spot checks and drift thresholds (≤ X%).
  • Hi-pot/PD strategy is referenced and test records are retained (clause details are link-only).
  • Burn-in triggers are defined (temperature rise, efficiency drop, abnormal fault count thresholds).
  • Functional tests include protection behavior: OCP/UVLO/OTP transitions and recovery timing.
  • Golden waveform snapshots are archived with version tags for regression comparison.
  • Change control requires evidence updates: waveforms, margins, EMI deltas, and thermal deltas.
  • Shipment criteria include diagnostic sanity: fault flags cleared, counters within X, PG behavior correct.
  • Deliverables package is complete: test reports, logs, BOM/version, and release sign-off.
Gate Flow (Spec → Design → EVT → DVT → PVT) Spec Targets Constraints Schematic Stress budget Protection policy Layout 3 loops Partition EVT Bring-up Waveforms Loop margins DVT EMI Δ Thermal PVT Production ATE limits Traceability Diagram intent: present the deliverable gates and the two acceptance points per gate for production-ready bridge converters.
Gate flow intent: enforce evidence-based delivery from spec to production, with explicit acceptance points (margins, waveforms, EMI delta, thermal margin, ATE limits, traceability).

H2-11. Applications

Application buckets map real system needs to a topology choice (Push-Pull / Half-Bridge / Full-Bridge) and the evidence required to ship: ripple, transient, EMI, thermal, and fault recovery.

Scope guard

This chapter stays at “requirements → topology fit → measurable pass criteria”. Detailed controller/driver selection appears in H2-12. Safety clause details belong to the Safety & Compliance page.

Bucket A · Drive / Control Rails (industrial drives, servo controllers)

Primary goal: stable control electronics power under fast load steps and harsh common-mode noise.

  • Need: large load-step headroom + predictable recovery. Topology fit: Half-Bridge (HB) / Full-Bridge (FB) favored for scalable power; Push-Pull (PP) fits selected power bands with careful balance.
  • Transient pass: ΔV ≤ X% @ step YA, settle ≤ Z µs (define probe bandwidth).
  • EMI pass: CM/DM plan verified at X kHz–Y MHz (filter partition + transformer Cps control).
  • Thermal pass: hotspot ≤ X°C at ambient Y°C; margin ≥ Z°C to shutdown.
  • Fault policy: short/overload recovery uses hiccup or latch with diagnosable pins/counters (policy must be explicit).

Bucket B · Auxiliary Rails for Power Stages (isolated 12/15V, 5V, etc.)

Primary goal: reliable isolated bias for secondary-side control, sensing, and local housekeeping.

  • Need: low ripple + robust start-up + clean recovery after brownout. Topology fit: HB/FB common for medium-to-high power; PP works with strict balance and magnetics margin.
  • Ripple pass: Vout ripple ≤ X mVpp (measurement method fixed: ground spring, bandwidth Y MHz).
  • Start-up pass: inrush limited; no abnormal overshoot > X% during soft-start (define load condition).
  • Noise coupling: switching node dv/dt control and transformer parasitic path budgeted (Cps / shield options).

Bucket C · Multi-rail Systems (sequencing + cross-regulation)

Primary goal: multi-output predictability with defined interaction limits (not “best effort”).

  • Need: rail sequencing + bounded cross-regulation. Topology fit: HB/FB often easier to scale with defined secondary strategies; PP requires stricter symmetry controls.
  • Sequencing pass: rail-A leads rail-B by ≤ X ms; UVLO/PG states are deterministic at power-down.
  • Cross-reg pass: rail-B drift ≤ X% when rail-A load steps YA (define which rail is master-regulated).
  • Protection interaction: one-rail short must not force uncontrolled restart storms on other rails (policy defined).

Bucket D · Low-ripple Analog Rails (precision sensing, mixed-signal)

Primary goal: ripple/spike control where synchronous rectification (SR) and layout dominate outcome.

  • Need: low ripple + low HF spikes + low CM injection. Topology fit: HB/FB with SR and disciplined partitioning; PP only when balance and parasitics are tightly controlled.
  • Ripple pass: ≤ X mVpp over band Y kHz–Z MHz; spike ≤ N mV (scope bandwidth stated).
  • EMI pass: CM path constrained by Cps and shield strategy; Y-cap usage is minimized and justified (limits addressed on Safety page).

Application acceptance fields (shared)

Each bucket must define these fields before tape-out and keep them unchanged through production.

Ripple: ≤ X mVpp Transient: ΔV ≤ X% @ Y A EMI: CM/DM pass @ X–Y MHz Thermal: hotspot ≤ X°C Fault: hiccup/latched policy
Drive / Control Rails transient · EMI · fault Aux Rails ripple · start-up Multi-rail Systems sequencing · cross-reg Low-ripple Analog spike · CM injection Push-Pull (PP) balance critical Half-Bridge (HB) scales cleanly Full-Bridge (FB) best for high power Key metrics to prove Ripple Transient EMI (CM/DM) Thermal Fault policy

H2-12. IC Selection Logic & Quick Pairings (with BOM-ready examples)

Selection is expressed as a decision tree (requirements → topology → control family → drive & SR strategy → sensing/protection). Part numbers below are representative, widely-used starting points—final selection must match voltage, frequency, thermal, and compliance constraints.

Selection decision steps (logic, not a catalog)

  • Step 1 · Power band: decide PP vs HB vs FB by RMS/thermal scaling and transformer utilization.
  • Step 2 · Control family: PWM vs peak current-mode vs phase-shift (PSFB) based on transient/efficiency and commutation behavior.
  • Step 3 · Gate drive approach: bootstrap half-bridge drivers vs transformer drive vs isolated drivers (deep dive: Gate Driver page).
  • Step 4 · Rectification choice: diode vs synchronous rectification (SR), including light-load reverse current behavior.
  • Step 5 · Evidence gates: timing overlap, stability margins, thermal headroom, EMI path control, fault recovery determinism.
Power level VIN range Efficiency target EMI severity Push-Pull (PP) balance required Half-Bridge (HB) clean scaling Full-Bridge (FB) high power PWM / current-mode common for PP/HB Phase-shift (PSFB) common for FB SR strategy (diode vs SR) light-load reverse control Sense & protection noise vs phase-lag budget Deliverable evidence: timing · stability · thermal · EMI · fault determinism

Controller IC examples (PP / HB / FB)

  • Double-ended PWM (PP/HB): TI UC3825 / UC2825A (classic dual-output PWM) :contentReference
  • Dual-ended current-mode (PP/HB): TI UC3846 / UC3847 (current-mode family for push-pull style converters) :contentReference
  • Current-mode with alternating drivers: TI LM5030 (push-pull / half-bridge / full-bridge usage noted in datasheet) :contentReference
  • Phase-shift full-bridge (PSFB): TI UCC28950 / UCC28951 (PSFB controllers with SR support) :contentReference
  • Phase-shift full-bridge (legacy PS family): TI UCC3895 / UCC2895 :contentReference

Rule of thumb: pick the controller family only after the timing budget (dead-time/phase-shift/SR windows) is stated as measurable limits.

Primary gate-drive IC examples (power-supply context)

  • 600 V bootstrap half-bridge driver: TI UCC27714 (HO/LO, bootstrap, noise-robust) :contentReference
  • High-side driver commonly paired with bridge controllers: TI LM5101 (appears in TI design note with LM5030 bridge usage) :contentReference
  • When isolation is required: use an isolated driver family (examples listed on the dedicated Isolated Gate Driver page; keep this page “link-only” for deep details).

Evidence gate: primary gate loop inductance, commutation loop inductance, and clamp/snubber loop inductance must be bounded by layout rules (see H2-5).

Secondary rectification: SR controller examples

  • Controller-driven SR (PSFB-friendly): use PSFB controllers with SR outputs such as TI UCC28950/UCC28951 :contentReference
  • VDS-sensing “diode-replacement” SR: TI UCC24610 (VDS-sensing, avoids false turn-on with min on/off times) :contentReference
  • Versatile SR driver: onsemi NCP4306 (secondary-side SR driver for multiple SMPS topologies) :contentReference

Bring-up proof (placeholders): SR overlap ≤ X ns, reverse current ≤ Y A at light load, and ringing immunity verified with worst-case layout.

Sense & protection building blocks (examples)

  • Current sense controllers (in-controller): prefer controllers that support cycle-by-cycle limit and slope compensation when operating near duty constraints.
  • External gate driver robustness: choose drivers with strong dV/dt immunity and defined UVLO thresholds (documented in the driver datasheet).
  • Optional “ideal diode / ORing” (system-level, not SR): ADI LT4320 for bridge rectification / polarity correction use-cases (only if the architecture requires it). :contentReference

This page avoids expanding into system software logging; it only defines which fault pins/counters must exist to support black-box diagnosis.

Quick pairings (BOM-style recipes)

  • Recipe 1 · 48V telecom / industrial rail (HB, current-mode, high current):
    Controller: TI LM5030 :contentReference · Primary driver: TI LM5101 :contentReference · SR strategy: controller-driven SR (or TI UCC24610 if diode-replacement style fits) :contentReference · Pass criteria: ripple ≤ X mVpp, ΔV ≤ Y%, hotspot ≤ Z°C.
  • Recipe 2 · PSFB high-power rail (FB, phase-shift, SR outputs):
    Controller: TI UCC28950 or UCC28951 :contentReference · Primary drivers: half-bridge drivers as required by the implementation (bootstrap vs transformer/isolated) · SR strategy: use built-in SR outputs (timing window proven) · Evidence: ZVS window ≥ X ns, SR overlap ≤ Y ns, EMI pass at N dBµV.
  • Recipe 3 · Classic PP mid-power rail (PP, dual-ended PWM):
    Controller: TI UC3825 :contentReference or TI UC3846 (current-mode) :contentReference · SR strategy: diode for lower current; SR when Iout pushes conduction loss (prove reverse current at light load) · Critical proof: flux-walk prevention + symmetry margin documented.
  • Recipe 4 · 400V bus auxiliary rail (HB driver, high dv/dt environment):
    Driver: TI UCC27714 (600 V HO/LO) :contentReference · Controller: select by control family (PWM/current-mode) and required protection policy · SR: pick SR method only after timing windows and ringing immunity are confirmed.

BOM-ready part-number list (copy/paste)

Controllers: UC3825, UC2825A, UC3846, UC3847, LM5030, UCC28950, UCC28951, UCC3895, UCC2895.

Primary drivers: UCC27714, LM5101 (plus implementation-specific bridge drivers as needed).

SR controllers/drivers: UCC24610, NCP4306 (or PSFB controller SR outputs like UCC28950/51).

Optional ideal diode bridge: LT4320 (only if architecture requires diode-bridge replacement).

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H2-13. FAQs

Format rule (fixed 4 lines)

Each question is answered using a field-ready structure: Likely cause / Quick check / Fix / Pass criteria (threshold placeholders X/Y/N). This section only closes on troubleshooting and acceptance criteria; it does not introduce new domains.

Efficiency is high at full load but collapses at mid load — SR timing or magnetics AC loss?

Likely cause: SR timing pushes reverse current at mid load, or transformer/winding AC loss dominates at the chosen switching frequency.

Quick check: Capture SR Vds+gate timing and secondary current; compare core/winding temperature rise at full vs mid load under same airflow.

Fix: Tighten SR turn-off to avoid reverse current (or add light-load inhibit); revisit winding strategy (foil/litz/interleave) and frequency to reduce AC loss.

Pass criteria: Mid-load efficiency drop ≤ X% at load Y%; SR reverse current ≤ N A peak; transformer hotspot ΔT ≤ X°C at ambient Y°C.

Primary MOSFET Vds overshoot spikes after layout “looks fine” — first check which loop?

Likely cause: High di/dt commutation loop inductance or clamp/snubber loop inductance is larger than expected; gate loop ringing can add false dv/dt stress.

Quick check: Probe Vds with the shortest ground spring; measure ringing frequency to back-calculate effective L; confirm clamp components sit inside the smallest possible loop.

Fix: Shrink commutation + clamp loops (placement/return path); tune RC/RCD/TVS clamp to the measured ringing energy; add controlled gate resistance only after loop inductance is addressed.

Pass criteria: Vds overshoot ≤ X V or ≤ Y% of device rating; ringing decays within N cycles; clamp temperature rise ≤ X°C at worst-case VIN.

Push-pull shows flux walk / transformer heating — imbalance from drive or duty clamp?

Likely cause: Primary drive asymmetry (timing mismatch, unequal Rg, unequal delays) or duty clamp / reset margin causes net DC bias in magnetizing current.

Quick check: Compare Q1/Q2 on-time and peak primary current each half-cycle; measure magnetizing current drift over N ms; check duty-limit behavior under line/load extremes.

Fix: Match drive paths (Rg, routing, delays), add symmetry correction in control, and ensure core reset margin; increase magnetizing inductance or reduce max duty if saturation margin is tight.

Pass criteria: Half-cycle peak current mismatch ≤ X%; magnetizing current DC drift ≤ Y A over N ms; transformer hotspot ΔT ≤ X°C at rated power.

Half-bridge has audible noise under certain loads — control mode or magnetics resonance?

Likely cause: Burst/skip or subharmonic oscillation moves energy into the audible band, or transformer/mechanical mounting resonates at a load-dependent excitation.

Quick check: Log switching frequency / mode transitions vs load; correlate noise peak with waveform burst patterns and transformer vibration points (light touch + stethoscope method).

Fix: Force continuous mode above a defined load, adjust compensation / ramp to prevent subharmonics, and damp mechanical resonance (potting/fixture) after electrical mode is stabilized.

Pass criteria: No audible tone above X dBA at distance Y cm across N%–100% load; switching mode remains stable (no burst) above Y% load; ΔV ripple ≤ X mVpp.

Full-bridge phase-shift: ZVS disappears at light load — what’s the fastest confirm?

Likely cause: Light-load current is insufficient to charge/discharge device capacitances within dead-time, so ZVS window collapses (especially with high Coss or long commutation loops).

Quick check: Measure switch-node voltage at turn-on and confirm if Vds is near zero; compare ZVS presence at two loads and two dead-time settings to isolate current vs timing limits.

Fix: Adjust dead-time/phase-shift timing, reduce commutation inductance, or add a controlled circulating current strategy (only if efficiency impact is acceptable).

Pass criteria: At load ≤ Y%: Vds at turn-on ≤ X V for ≥ N% switching events; switch-node ringing peak ≤ X V; efficiency penalty ≤ Y% vs baseline.

Output ripple meets spec on bench but fails in system — measurement method or CM coupling?

Likely cause: Bench probing underestimates HF components (ground lead, bandwidth) or system cabling/grounding turns common-mode current into differential ripple at the load.

Quick check: Re-measure with ground spring + defined bandwidth; compare ripple at converter output vs at load connector; check CM current on cable shield/return with a clamp probe.

Fix: Lock the measurement method, add secondary-side HF filter partitioning, and break CM paths (shield strategy, transformer Cps control, snubber at key nodes).

Pass criteria: Ripple ≤ X mVpp at load over Y MHz bandwidth; CM cable current ≤ N mA RMS; ripple delta (bench→system) ≤ X mVpp.

SR MOSFET runs hot though diode loss should be lower — reverse current or dead-time too long?

Likely cause: Dead-time forces body-diode conduction (high loss), or SR timing causes reverse current (especially at light-to-mid load), or ringing triggers false turn-on.

Quick check: Capture SR gate vs Vds to see diode-conduction intervals and overlap; measure secondary current direction near zero-crossing; check for false gate pulses during ringing.

Fix: Reduce dead-time while preventing shoot-through, add reverse-current inhibit or blanking, and damp ringing at the rectifier node before tightening timing.

Pass criteria: SR diode-conduction time ≤ X ns per cycle; reverse current ≤ Y A peak at light load; SR MOSFET case ΔT ≤ X°C at rated output.

EMI fails only on certain cables — CM path via transformer capacitance or Y-cap choice?

Likely cause: Cable geometry shifts common-mode impedance; transformer Cps and Y-cap create a CM injection path that excites cable-as-antenna behavior.

Quick check: Swap cables and record delta at failing bands; measure CM current on the cable; confirm if emissions track switch-node dv/dt and transformer shield/Y-cap placement.

Fix: Reduce CM source (edge-rate shaping, snubbers), add/relocate shielding to intercept Cps coupling, and tune Y-cap only after leakage constraints are satisfied (handled on Safety page).

Pass criteria: EMI margin ≥ X dB in band Y–N MHz across cable set; CM current ≤ Y mA RMS; dv/dt at switch node reduced by ≥ X% without efficiency loss > Y%.

Short-circuit test passes but field faults cause repeated restarts — hiccup timing too aggressive?

Likely cause: Hiccup/retry timing does not match thermal time constants; borderline faults create a restart storm that never lets temperatures settle or rails stabilize.

Quick check: Log restart period and temperature trend during repeated faults; check UVLO/OTP thresholds and whether startup inrush triggers current limit repeatedly.

Fix: Increase off-time or add restart backoff, add fault latching for persistent faults, and tighten qualification for “safe restart” conditions (UVLO clear, temperature margin).

Pass criteria: Restart attempts ≤ X per hour under fault; hiccup off-time ≥ Y ms; peak component temperature stays ≤ N°C; recovery to regulation within X ms once fault is removed.

Two builds with same BOM show different thermal — transformer process variation or airflow assumptions?

Likely cause: Magnetics build variation (leakage, DCR, core loss) or enclosure airflow/thermal interface differs from assumptions, shifting hotspot location and loss partitioning.

Quick check: Compare transformer DCR and leakage (relative delta), measure no-load loss at a fixed frequency, and validate airflow path with a simple smoke/temperature gradient check.

Fix: Tighten magnetics specs (DCR, leakage, core material/AL) and add thermal margin; update airflow/derating assumptions and verify worst-case with controlled fan/obstruction tests.

Pass criteria: Unit-to-unit hotspot delta ≤ X°C at rated power; transformer DCR within Y% and leakage within N% across lots; enclosure airflow keeps sink rise ≤ X°C.

Control loop stable in small-signal sim but rings in hardware — sense noise injection or layout?

Likely cause: Sense path picks up switching noise (ground impedance, poor partition) or filtering adds phase lag not modeled; layout creates an unintended feedback path.

Quick check: Scope the sense node with high bandwidth and short return; inject a small load step and measure ringing frequency; compare behavior with temporary RC filters and clean grounding.

Fix: Re-route/partition sense return, add noise filtering with bounded phase impact, and re-tune compensation only after the sense signal is clean and deterministic.

Pass criteria: Phase margin ≥ X° and gain margin ≥ Y dB (measured); load-step overshoot ≤ N% with settle ≤ X µs; sense noise ≤ Y mVpp at bandwidth N MHz.

Passing efficiency but failing hold-up transient — bulk cap ESR or control bandwidth?

Likely cause: Bulk capacitor ESR/ESL and wiring impedance dominate droop, or control bandwidth is too low to correct within the hold-up window; current limit behavior may clamp response.

Quick check: Measure Vout droop during hold-up with a defined event; estimate energy from bulk cap (C, ΔV) and compare to load; observe whether control hits current limit.

Fix: Reduce ESR/loop impedance, increase bulk energy or adjust droop allowance, and tune control bandwidth within stability margins; ensure current limit does not prematurely clamp hold-up response.

Pass criteria: Hold-up droop ≤ X% for Y ms at load N A; recovery to regulation ≤ X ms after event; measured ESR-induced step ≤ Y mV.

Note: Replace X/Y/N with project-specific thresholds and keep the measurement method (bandwidth, probe, location, load) fixed across validation and production.

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