Clocking & Phase Noise for DACs: Jitter Budgets and Spur Control
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Wideband DAC performance is clock-limited when phase noise and jitter modulate the output, raising noise floors and creating predictable spurs. This page shows how to translate output targets into a windowed jitter budget, place PLL/cleaning and distribution correctly, and prove the result with repeatable measurements.
What this page solves (and when clock noise dominates)
This page helps identify when a DAC’s dynamic limits are set by the clock path (phase noise, jitter, and PLL spurs), then shows how to trace symptoms back to the right root cause and next action.
- SNR degrades as output frequency (fout) increases, even when amplitude is unchanged.
- Wideband “carpet” noise lifts the floor around a tone (skirted spectrum).
- Discrete spurs land at offsets tied to reference, divider ratios, or PLL patterns.
- Close-in noise “humps” appear near the carrier, often changing with supplies or loop settings.
- Sweep fout: if noise rises predictably with higher fout, the clock path is likely a top contributor.
- Change RBW: noise-like floors move with RBW; true spurs remain as lines.
- Nudge reference/dividers: spurs that move with ref/divider settings point to PLL-related deterministic tones.
- Power A/B: close-in humps changing with supply filtering suggest coupling into VCO/clock buffers.
- SNR gets worse as fout rises → treat clock phase noise/jitter as a primary limit; build a budget and verify it with controlled clock A/B tests.
- Spurs stay locked to reference/dividers → focus on PLL spur mechanisms and reference leakage (deterministic tones), not on “more jitter spec” alone.
- Close-in noise humps appear → suspect VCO/loop bandwidth choices and supply/crosstalk coupling into the clock chain.
Clock noise → output noise: the one model to trust
A DAC does not “see” phase noise as a number in a table. It sees uncertain sampling instants. The same timing error causes bigger output error when the waveform slope is steeper, so clock quality becomes more critical as output frequency and bandwidth increase.
- Phase error becomes time error: phase noise means the clock edge arrives slightly early/late.
- Time error becomes amplitude error: sampling the waveform at the wrong instant picks the wrong value.
- Waveform slope sets sensitivity: higher fout (or wider bandwidth) → steeper slope → larger error for the same jitter.
- Random jitter / random PN spreads energy into a noise skirt and raises the noise floor.
- Periodic modulation (PLL spurs, reference leakage, supply ripple) creates discrete spurs at repeatable offsets.
- Many real systems show both: a higher floor plus new lines, meaning “cleaner jitter” alone will not remove deterministic spurs.
- Floor-driven limit (SNR): spectrum looks “carpet-like” and tracks RBW.
- Spur-driven limit (SFDR): new lines appear at fixed offsets and often track reference/divider settings.
- Close-in hump: near-carrier skirt worsens with loop bandwidth or supply coupling into clock/VCO stages.
Convert phase noise specs into RMS jitter (integration boundaries that matter)
Phase-noise plots and “integrated jitter” numbers only become useful after the integration boundaries match the system’s bandwidth and clock chain. The most common mistake is not the math—it is integrating the wrong offset region (or trusting a vendor number measured with a different window and filtering).
- Phase noise is a spectrum density (dBc/Hz) versus offset frequency from the carrier.
- Integrating a chosen offset range produces a single number: RMS phase (then expressed as RMS jitter in time).
- The offset range is the “measurement window” that decides whether the number predicts real output floors.
- Close-in: loop bandwidth choices, VCO behavior, and supply/crosstalk coupling into clock stages.
- Mid-offset: where jitter cleaners and bandwidth selection often change the shape the most.
- Far-out: reference noise floor, fanout/buffer additive noise, and wideband board-level interference.
- Offset limits: the vendor’s integration start/stop must align with the offsets that matter to the application bandwidth.
- Hidden filtering: some numbers include internal cleaning/buffering behavior that may not match the system’s topology.
- Added contributors: fanout additive jitter, board-to-board distribution, and coupling can dominate even with a “good” source.
- Keep the DAC output tone and amplitude fixed.
- Change only one clock variable: source or cleaner bandwidth.
- If the noise skirt/floor moves, the integrated PN window is relevant.
- If only lines/spurs move (or stay locked), the dominant issue is deterministic (PLL spurs or coupling), not random jitter.
Jitter is not a single universal number. A jitter value is only meaningful when its integration offsets match the offsets that actually shape the output spectrum in the intended bandwidth.
Jitter budget method: from output requirement back to the clock chain
A usable jitter budget starts from the performance requirement (SNR, SFDR, or modulation metrics) under the worst-case operating condition, then allocates allowable timing uncertainty across reference, PLL/cleaner, distribution, and coupling so verification can confirm each share.
- SNR-based: treat random PN/jitter as a floor and keep noise skirts below the allowed noise budget.
- SFDR-based: budget deterministic tones separately (PLL spurs / coupling), because “better jitter” does not erase locked spurs.
- EVM/ACLR-based: focus on the offset regions that distort phase in-band; match integration windows to the channel bandwidth.
- Highest fout: timing sensitivity rises with waveform slope.
- Largest bandwidth: include any interpolation, upconversion, and reconstruction windows that matter to the spec.
- Most fragile supply/layout: coupling often amplifies close-in humps and spur content.
- Convert allowed error to allowed timing uncertainty at the worst-case output condition.
- Allocate total jitter across the chain: reference → PLL → cleaner → distribution → coupling → board-to-board.
- Add margin for temperature, aging, supply noise, and layout variation so production units still pass.
- Verify by causality: change one clock contributor at a time and confirm the predicted movement in floor/skirt or locked spurs.
- Reference: far-out floor and part of close-in (architecture-dependent).
- PLL: close-in shape and spur risks (loop bandwidth is the main lever).
- Cleaner: mid-offset improvement but can introduce new spur patterns.
- Distribution: additive jitter, skew/coherence risk, and crosstalk sensitivity.
- Coupling: board-level, not a datasheet number—managed by isolation and returns.
- Board-to-board: connectors/cables/returns add uncertainty and noise pickup.
- Temperature: loop bandwidth and VCO noise shift with operating point.
- Aging: reference drift and supply changes move noise/spur behavior over time.
- Supply noise: unit-to-unit ripple differences create extra PM/FM spur content.
- Layout variation: return-path differences change coupling into clock edges.
- Test windows: lab settings and production test settings must use consistent offsets.
RTZ vs NRZ: what changes in spectra, images, and clock sensitivity
RTZ and NRZ are not “better vs worse.” They trade spectrum shaping against sensitivity to clock-edge quality. The right choice is made by checking the specific in-band and out-of-band windows that matter to the spec.
- Simpler timing: fewer waveform constraints beyond edge placement.
- Energy stays concentrated in the main lobe for many use cases.
- Often more tolerant of duty-cycle variation and pulse-width imperfections.
- Common default for general-purpose waveform and control outputs.
- Changes spectral envelope and can improve certain image / out-of-band windows.
- More sensitive to edge timing, duty-cycle stability, and pulse-width error.
- Clock-shape imperfections can show up as sidebands or locked spurs.
- May introduce different power/linearity tradeoffs that must be verified by measurement.
- Wideband, strict out-of-band masks, image control → RTZ is often worth evaluating first.
- Clock chain is constrained (duty-cycle drift, board-to-board distribution, noisy edges) → NRZ is often the safer baseline.
- Decide by windows: confirm which mode wins in the exact in-band and out-of-band regions tied to the spec.
- In-band SNR/SFDR: confirm the main performance does not regress.
- Close-in skirt: check near-carrier noise and sidebands around critical tones.
- Far-out floor: verify wideband noise in the intended bandwidth.
- Images / OOB mask: compare the exact out-of-band windows required by the system.
- Spur map: look for new locked spurs that follow duty-cycle or divider settings.
If RTZ improves out-of-band images but introduces close-in humps or new locked spurs, the limiting factor is typically clock-edge quality (duty/pulse-width) or coupling—not the DAC core itself.
PLL & jitter-cleaning architecture: where cleaning works and where it cannot
Jitter cleaning is a frequency-selective tool. It reshapes which noise dominates across offset regions, but it cannot “erase” deterministic spurs injected by coupling, supplies, or data activity. A correct architecture places cleaning where it controls the offsets that matter to the output windows.
Reference → PLL/VCO → Clean-up → Fanout → DAC
- Reference: noise floor sets far-out limits.
- PLL/VCO: close-in shape and spur risk.
- Clean-up: improves specific mid-offset regions.
- Fanout: additive noise + coherence risk.
- Selected offset bands (often mid-offset).
- Reference noise contribution (architecture-dependent).
- Skirt/floor that follows the cleaned region.
- Supply/crosstalk injected locked spurs.
- Board-level coupling that modulates edges.
- Data-related deterministic spur mechanisms.
- Too narrow: relies more on VCO close-in behavior; can leave near-carrier humps and slow tracking.
- Too wide: pulls more reference noise into the output and can expose reference-related spur patterns.
- Correct bandwidth: places the crossover so the dominating offsets match the intended spectrum windows.
- Change only loop bandwidth or clean-up placement.
- Confirm which offset region changes (close-in vs mid vs far-out).
- If spurs stay locked, the dominant problem is deterministic injection (coupling/supply), not lack of “cleaning.”
Cleaning should be placed where it controls the integration windows used in the jitter budget, and where downstream fanout and routing do not re-inject additive noise or deterministic modulation.
Clock distribution & fanout: additive jitter, isolation, and crosstalk traps
The clock chain often looks clean at the source and fails at the receiver. Fanout, buffers, routing, termination, and return paths can re-inject edge modulation after the last “clean” stage, so the final centimeters must be treated as part of the jitter and coherence budget.
- Series contributors: each stage can add edge uncertainty (fanout, buffer, trace, receiver).
- Absolute vs relative: absolute jitter affects single-channel noise; relative phase/skew governs multi-channel coherence.
- Interface form: swing/common-mode/return currents decide how easily coupling becomes timing modulation.
- Additive jitter is not just a part number; it is a system sum after cleaning.
- More channels usually means more switching activity and more coupling opportunities.
- Load/termination shapes return currents; bad returns create edge movement that looks like phase noise.
- Skew drift can be the dominant multi-channel failure mode even when absolute jitter looks fine.
- Spurs change with load modes → shared supply / insufficient isolation → split rails, local filtering, and quiet reference for fanout stages.
- Amplitude changes with layout rev → broken return paths / crossing splits → keep return continuous under pairs and avoid plane gaps under clock routes.
- Spurs follow frame/data rates → field coupling from data buses → increase spacing, add shielding/guarding, and avoid parallel runs.
- Channel-to-channel phase drifts → topology / unequal loads → prefer symmetric trees, matched loads, and controlled termination locations.
- Swing: steeper edges can amplify supply/ground modulation into timing shifts.
- Common-mode: common-mode movement can convert to differential edge timing at receivers.
- Return currents: termination choices decide loop area and coupling sensitivity.
- Crosstalk: spacing and reference planes decide whether “data” becomes “clock phase.”
Multi-channel systems must track two budgets: absolute jitter (noise skirt) and relative phase/skew (coherence). A fanout tree that looks acceptable on absolute jitter can still fail by skew drift across temperature, rails, and loading.
Deterministic spurs: where they come from and how to kill them (not with jitter spec)
Spurs are not random jitter. They are deterministic modulation that produces locked spectral lines. Treat them as a source-and-path problem: identify what the spur locks to, then break the injection path or change the mechanism.
- PLL / divider spurs: lines locked to reference, PFD, divider ratios, or fractional modulation patterns.
- Reference leakage: lines that follow the reference (or its harmonics) when the reference is moved.
- Supply / digital activity modulation: lines locked to switching regulators, frame rates, triggers, or periodic loads.
- Random jitter reshapes noise floors and skirts.
- Deterministic spur lines come from periodic FM/PM or leakage paths.
- Cleaning may reduce some noise regions yet keep locked tones unchanged.
- Move reference/divider settings and check if spur positions move proportionally.
- Change supply conditions (filtering, switching frequency, or a cleaner rail) and check if the spur moves or collapses.
- Change data/frame/trigger rates and check if spur spacing follows these periodic activities.
- PLL / fractional spurs: adjust loop bandwidth, plan PFD/reference, change divider strategy, align/synchronize where applicable.
- Reference leakage: isolate reference routing, control returns and termination, reduce coupling paths into clock edges.
- Supply/digital modulation: isolate rails, filter and partition, separate high di/dt domains from clock tree, reduce periodic injection.
A spur problem is solved by breaking the deterministic modulation path or changing what it locks to. Jitter specifications help predict noise floors, not locked spectral lines.
Layout & grounding for clock purity: return paths and isolation rules that actually work
Clock purity is preserved when edges are not modulated. Board-level failures almost always enter through three paths: supply modulation, return-path detours, and field coupling from fast digital activity. Layout must block these paths in a repeatable way.
- Minimize loop area: shortest electrical loop (signal + return), not just shortest trace.
- Keep reference planes continuous: avoid plane gaps, splits, and abrupt reference changes under the pair.
- Never cross a split: crossing a gap forces return detours and increases edge modulation risk.
- Avoid parallel runs with fast data: if crossing is required, cross quickly and near-orthogonally.
- Termination is also a return decision: place terminations so return currents close locally and do not traverse sensitive zones.
- Clock island supply: PLL/VCXO/cleaner/fanout should use quiet rails with local filtering or a dedicated LDO where feasible.
- Keep noisy di/dt loops away: switcher hot loops and large digital bursts must not share return geometry with clock edges.
- Three-island layout: clock island / digital island / analog island with a controlled connection strategy (avoid uncontrolled multi-point returns).
- Plan return paths: ensure the intended return is shorter than any accidental path through other islands.
- Use guard / fence when it provides a controlled coupling sink and the reference plane stays continuous.
- Avoid guard when it creates slits, forces return detours, or turns a clean plane into a maze.
- Pass/fail test: if the guard makes the return path longer or less obvious, it is likely harmful.
- If a spur locks to a switcher frequency, isolate the clock island rail and shorten its return loop.
- If a layout rev changes spur amplitude, suspect return-path detours (splits, vias, reference changes).
- If spurs track frame/data rates, increase separation and remove long parallelism with data buses.
A clean clock part number does not guarantee a clean clock at the DAC. A clean clock at the DAC requires controlled return paths, isolated supplies, and separation from periodic digital injection.
Verification & measurement: prove the budget (phase noise, jitter, SFDR)
A jitter budget is only useful if it can be verified. Verification must separate clock-only quality from system output behavior, then close the loop by changing one clock variable and observing how the output spectrum responds.
- Clock-only: measure PN/jitter with the same integration windows used in the budget.
- System output: measure DAC output SNR/SFDR/SNDR in the target bandwidth and masks.
- Correlation: change one clock variable and confirm the expected output change by window and shape.
- Noise skirts / raised floors tend to track random timing noise and PN regions.
- Locked lines are deterministic modulation (supply, divider, frame/data injection), not random jitter.
- Correlation beats guessing: only changes that move predictably with the chosen variable should be credited to clock noise.
- Different RBW/VBW or averaging settings.
- Different window functions or record lengths.
- Different trigger/sync conditions across runs.
- Different PN integration bounds vs the budget.
- Reference source or distribution noise dominating the reading.
- Supply/ground coupling into probes and fixtures.
- Fanout/termination changes between A/B setups.
- Environmental or cabling differences that re-inject spurs.
- Clean-up A/B: swap a cleaner or change its placement and watch mid-offset skirts/floors move.
- Loop BW A/B: change PLL bandwidth and observe which offset regions shift (close-in vs far-out).
- Supply filter A/B: change clock-island filtering and check whether locked lines collapse without affecting random skirts.
The budget is validated when the predicted window changes match the measured window changes. If locked lines do not move when clock noise is altered, the dominant mechanism is deterministic injection, not random jitter.
Production checklist & vendor questions (clock chain that survives volume)
Volume success requires a clock chain defined by measurable windows and pass/fail gates, not by a single “integrated jitter” headline. Every vendor field should map to a production risk and to an acceptance test performed with fixed boundaries.
- Phase noise (PN) at defined offset points (close-in / mid / far-out) and at the target output frequency.
- Integrated RMS jitter with explicit integration bounds (e.g., [f1..f2]), measurement mode, and operating condition.
- Spur specification (worst-case level + what it locks to: reference / divider / fractional pattern).
- Additive jitter for fanout/buffers (again with explicit integration bounds).
- PSRR / supply sensitivity vs frequency (or a clear test condition that ties to the intended rail noise environment).
- Power guidance: recommended rails, isolation suggestions, decoupling and termination requirements.
- Startup / warm-up and settling time to stable phase noise and spur behavior.
- Temp / aging behavior (drift and any control-loop bandwidth or spur changes across temperature).
- Phase coherence metrics for multi-output systems: channel-to-channel skew and skew drift vs temperature/rails/load.
PN points = <offset list> dBc/Hz @ <fout> MHz, condition = <rails/temp/load>
Spurs (worst-case) = <___> dBc, locks to = <ref/div/frac/supply/frame>, offsets/windows = <___>
Additive jitter (fanout/buffer) = <___> fs, integration = [<f1>..<f2>], outputs = <count>
PSRR / supply sensitivity = <curve or points>, rails = <___>, decoupling/termination = <___>
Channel-to-channel skew = <___> ps, skew drift = <___> ps over <temp/rail/load>
- Lot-to-lot PN / spur spread: the same BOM can ship with different noise floors or spur amplitudes across batches.
- Temperature-driven loop changes: PLL bandwidth or internal calibration can shift PN shape and spur behavior at hot/cold corners.
- Board coupling variation: small assembly and routing changes can re-inject deterministic spurs (supply ripple, frame/data activity).
- Shielding and grounding variability: shields that are not consistently bonded can create new return detours and new spur paths.
- Multi-output coherence drift: channel-to-channel skew drift can dominate phased/multi-channel performance even when absolute jitter is stable.
- PN spot-check at defined offsets.
- Integrated jitter with fixed bounds.
- Spur scan: locked lines vs threshold.
- Fanout additive jitter with fixed bounds.
- Measure clock at the receiver node.
- A/B: change one variable (cleaner/BW/rail) and observe movement by window.
- Check skew drift across temperature/rails/load.
- SFDR/SNR/SNDR in the target bandwidth/mask.
- Separate noise skirts from locked spurs.
- Pass/fail by defined windows and frequency regions.
- Crystek CCHD-957 (low PN XO class)
- SiTime SiT5356 (TCXO class)
- Silicon Labs Si5345
- TI LMK04828
- ADI AD9545
- ADI HMC7044
- TI LMK00304
- ADI ADCLK954
- TI LMK1C1104 (LVCMOS buffer class)
- TI TPS7A94
- ADI ADP7156
- Analog Devices / LT LT3042
Note: Part numbers above are examples to anchor RFQs and test gates. Production acceptance must be defined by measurement windows and masks.
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FAQs – Clocking & Phase Noise for DACs
These FAQs focus only on DAC clocking and phase-noise behavior: jitter budgets, RTZ/NRZ sensitivity, PLL/jitter cleaning, distribution/fanout traps, layout return paths, and verification methods.
Why does DAC SNR get worse as output frequency increases, even with the same clock?
Timing noise converts into output voltage noise more strongly at higher output frequencies, so wideband noise floors and skirts rise as the tone moves upward.
- The noise floor or skirt rises broadly (not just a few discrete lines) as output frequency increases.
- The degradation is consistent across repeated runs with the same tone and measurement setup.
- Budget and validate at the highest output frequency and widest relevant bandwidth.
- Run a one-change A/B (swap cleaner or adjust loop bandwidth) and confirm the skirt/floor moves by the expected offset region.
A single “integrated jitter” number without its integration bounds is not sufficient to explain frequency-dependent SNR loss.
Is “integrated RMS jitter” from a datasheet enough to budget a DAC system?
Not by itself. The number depends on integration bounds, operating mode, and where it was measured in the chain, so system budgets must standardize windows and measurement points.
- The datasheet lists multiple jitter values depending on mode, bandwidth, or output format.
- Different vendors quote different integration ranges, making direct comparisons misleading.
- Define a single integration window (e.g., [f1..f2]) and use it consistently for all contributors.
- Measure or specify jitter at the receiver node (at the DAC input) when possible.
A cleaner’s datasheet jitter is not the same as “system jitter” once fanout, routing, and supply coupling are included.
How should phase-noise integration bounds be chosen for a DAC jitter budget?
Bounds should match what can influence the application’s output masks and what can be measured repeatably, then be used consistently across reference, PLL/cleaner, distribution, and layout contributors.
- Close-in offsets are typically controlled by loop behavior and coupling; far-out offsets often expose noise floors and distribution noise.
- Changing loop bandwidth shifts which offsets dominate the measured jitter.
- Split the budget into close-in / mid / far-out windows and assign ownership (loop BW, reference, distribution).
- Validate by one-change A/B: adjust loop BW and confirm the expected window changes.
Integrating “as wide as possible” does not guarantee better predictability; it can hide which block actually dominates.
Why is there a “noise skirt” around the tone instead of a few discrete spurs?
A noise skirt is a broadband effect consistent with random timing noise and phase noise, while discrete spurs usually indicate deterministic modulation or leakage.
- The spectral rise is continuous and symmetric around the tone (skirt), not a set of narrow lines.
- The skirt changes when clock PN regions are altered (cleaner or loop BW changes).
- Do a one-change A/B: swap the cleaner or adjust PLL bandwidth and look for skirt movement by offset region.
- Verify clock at the receiver node; distribution can re-inject timing noise after cleaning.
A better spur spec does not automatically reduce a broadband skirt; those mechanisms are different.
Spurs move with reference or divider changes—what does that imply?
The spur is locked to the PLL/reference/divider mechanism rather than being random jitter. Treat it as a deterministic signature and fix the locking source or its coupling path.
- Spur spacing or position follows reference frequency, divider ratios, or fractional patterns.
- Changing loop settings changes the spur level more than the broadband floor.
- Adjust loop bandwidth and confirm whether the spur responds in a predictable way.
- Re-plan PFD/reference settings or divider strategy to reduce known locking products.
Reducing RMS jitter alone will not remove a spur that is produced by deterministic locking.
Spurs follow DC/DC switching or frame/data rates—how can the path be isolated?
This is deterministic injection through supply, return-path, or field coupling. Isolation succeeds when the locked line collapses under a one-change A/B to the suspected path.
- The spur stays at the same offset/spacing and tracks the switching frequency or activity rate.
- The spur does not behave like a broadband skirt when clock PN is improved.
- Isolate the clock-island rail (quiet LDO or additional filtering) and check whether the locked line drops.
- Increase separation and remove long parallelism between clock routes and high-speed data.
- Confirm return-path continuity (no split crossings) near clock distribution and terminations.
“Cleaner fixes everything” is false when the spur is created after the cleaner by coupling or periodic load modulation.
RTZ vs NRZ: which one is more sensitive to clock edge quality and duty-cycle error?
RTZ often increases sensitivity to edge placement and duty-cycle/width errors because its timing and pulse-width behavior becomes part of the spectrum, while NRZ is usually more tolerant but trades image and out-of-band behavior differently.
- Switching NRZ↔RTZ changes the out-of-band envelope and can change which spurs dominate.
- Duty-cycle or distribution changes affect RTZ results more strongly in many builds.
- Define the observation windows (in-band SNR/SFDR and out-of-band masks) before picking RTZ/NRZ.
- Validate with a controlled A/B using the same measurement setup and the same tone plan.
RTZ is not “better” by default; it is a trade that can expose distribution and duty-cycle weaknesses.
If RTZ improves images, why did SFDR get worse in a real build?
Image behavior and spur behavior are not the same metric. RTZ can reduce certain images while increasing sensitivity to duty-cycle errors, supply modulation, or distribution-induced edge timing changes that create new dominant spurs.
- The out-of-band envelope improves but a few new discrete lines become dominant.
- Spurs correlate with duty-cycle, rails, or distribution topology rather than with broadband jitter.
- Run a one-change A/B focusing on duty-cycle control, distribution, and clock-island supply filtering.
- Measure clock at the DAC input and correlate spur movement with the suspected injection source.
Better image suppression does not guarantee better SFDR if deterministic spurs are introduced elsewhere.
For multi-channel DACs, what matters more: absolute jitter or channel-to-channel skew?
Both must be budgeted separately. Absolute jitter controls noise floors, while channel-to-channel skew and skew drift control coherence and phase alignment across channels.
- Single-channel performance looks acceptable, but beamforming/phasing or cancellation across channels fails.
- Performance shifts with temperature/rails even when the clock source looks stable.
- Use symmetric fanout trees with matched loads and controlled termination placement.
- Validate skew drift over temperature/rails/load as a production gate, not only at room temperature.
A low absolute jitter specification does not guarantee multi-channel phase coherence.
How can a fanout buffer “ruin” a cleaned clock?
Fanout and distribution can add jitter and can re-inject deterministic modulation through supply and return paths near the receivers, so the clock can degrade after the last “clean” block.
- Clock looks good at the cleaner output but worse at the DAC input node.
- Spurs increase when more channels are enabled or when loads change.
- Use fanout parts with specified additive jitter in the same integration window used for the budget.
- Give the fanout and clock island a quiet rail and keep return paths local and continuous.
- Measure at the receiver node and correlate improvements with node-level changes.
A low additive-jitter headline does not protect against board-level coupling that creates deterministic spurs.
Why did a PCB revision change spur amplitude even when the clock BOM is unchanged?
Layout changes can alter return paths, plane continuity, and coupling geometry. That changes deterministic injection strength, so spurs can move in amplitude without any BOM change.
- Spurs correlate with routing changes near splits, via transitions, or termination placement.
- Spurs correlate with proximity/parallelism between clock routes and fast data or switcher loops.
- Check for clock routes crossing plane splits or losing continuous reference planes.
- Remove long parallel runs with high-speed data and shorten clock return loops near receivers.
- Use one-change A/B (route/termination/rail isolation) and confirm a predictable spur response.
“Same BOM” does not mean “same clock at the DAC” when return paths and coupling geometry change.
What is the fastest way to prove a jitter budget is correct (or wrong)?
Use a three-layer loop: clock-only measurement with fixed windows, predict the output impact, then measure the DAC output and confirm that changes occur in the expected windows and shapes under a one-change A/B.
- If improving PN/jitter reduces skirts/floors as predicted, the budget is on the right track.
- If locked spurs do not respond, the dominant mechanism is deterministic injection, not random jitter.
- Fix integration bounds and measurement settings (RBW/VBW/window/averaging) across all runs.
- Change one thing (cleaner, loop BW, or clock-island rail filtering) and observe which windows change.
- Measure at the DAC input node and at the DAC output to confirm where the change is injected.
A “good” clock plot at the source is not proof; proof requires correlation at the receiver and at the output under controlled A/B changes.
