DAC Code-to-Code Consistency and Major Carry Transients
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Clean large-step switching is not “one glitch number”—it is a repeatable envelope across worst-case code boundaries and real loads. This page shows how to identify major-carry hot spots, separate core glitch from reference/ground/IO coupling, and lock a production-ready test + layout checklist so every step behaves consistently.
What this page solves
Large DAC code steps (especially major-carry transitions) can inject a brief but disruptive transient into bias rails, references, and sensitive analog nodes. The real problem is not “noise” — it is step-dependent energy and recovery behavior that changes with code position, direction, load, and update timing.
Glitch
A short transient can trip comparators, disturb ADC sampling, or punch through an analog protection window. Peak alone is misleading; glitch energy (area) often predicts real disturbance better.
Settling
Two steps with the same size (Δcode) can settle very differently depending on the starting code and carry boundary. The “tail” defines when a rail or bias becomes usable again.
Crosstalk
A big step on one channel can bump other channels through shared reference, supply impedance, or ground return. Disturbance-free switching requires controlling where the transient current flows.
Scope: This page focuses on large-step transient cleanliness and repeatability: identifying worst transitions, mapping root causes, selecting mitigation levers, and verifying with production-ready tests.
Not covered: deep INL/DNL theory, a full DAC architecture encyclopedia, or a complete RF spur catalog. These are separate topics and are intentionally kept out to avoid cross-page overlap.
What readers get from this page
- Worst-case step vectors that reliably expose major-carry and boundary behavior.
- Minimal metrics (peak, area, settling-to-window, residual-at-time) to quantify repeatability.
- Root-cause map (switching injection, ref/supply droop, buffer recovery, load/parasites).
- Layout hooks (return paths, reference isolation, probing points) that prevent cross-channel bumps.
- Test flow that turns waveforms into pass/fail envelopes suitable for production.
Define “code-to-code consistency” and “major carry”
Precise bias and setpoint switching needs more than “low glitch” claims. It needs repeatable transient behavior across the code range. Two transitions with the same step size can produce different disturbance if their bit activity and internal switching paths differ.
Code-to-code consistency
Under the same conditions (supply, temperature, load, update rate, measurement bandwidth), the transient metrics produced by the same transition class (step size and direction) should remain within a tight envelope across the code range.
- Same Δcode does not guarantee same waveform.
- Consistency is about distribution (envelope), not a single “typical” plot.
- Worst behavior often clusters around boundary regions (carry points, segment boundaries).
Major carry
A major-carry transition crosses a binary carry boundary where many bits flip at once (example: 0x0FFF → 0x1000). This concentrates switching activity and frequently produces the most stressful transient.
Practical meaning: major carry is a reliable worst-case test vector for glitch energy, reference droop, and cross-channel bumps.
Minimal measurement set (enough to judge repeatability)
These four metrics avoid common misreads where a “small peak” still causes system disturbance (or vice versa).
Peak
Captures protection windows, comparator/ADC upset risk, and overshoot margin.
Area (glitch impulse)
Integrates transient energy; correlates with disturbance through RC loads and sensitive analog nodes.
Settling to a window
Time until the waveform stays inside ±(x LSB / x ppm). Defines when the bias or rail is usable again.
Residual at a fixed time
Error remaining at a defined delay after the update edge; critical for timed control sequences.
Root causes: why large steps disturb the output
A “big step glitch” is rarely a single phenomenon. It is the sum of four disturbance paths that scale differently with code position, direction, update edge timing, and load. Stable designs diagnose the waveform first, then apply the correct control knob instead of adding random filtering.
Quick triage: narrow edge spikes often point to switching injection; shared bumps on other channels point to reference/supply bounce; long tails often point to buffer recovery; fixed-frequency ringing often points to load/parasitics.
Switching charge injection / clock feedthrough
Symptom
Very short spikes aligned with the update edge; strong code dependence near carry/boundary regions; peak can be high even with light loads.
Mechanism
Many bits toggling at once injects charge through switch parasitics and couples the update edge into the output node. Major-carry transitions concentrate the worst switching stress.
Knob
- Use worst-case vectors (major-carry / boundary codes) to expose the true peak and area.
- Add output damping (Riso / small RC) to prevent injected charge from turning into ringing.
- Keep the update edge away from sensitive sampling/decision windows when timing is controllable.
Reference / supply droop & ground bounce
Symptom
VREF/AVDD shows small droop or bounce during the step; other channels bump at the same time; disturbance grows with step size and update activity.
Mechanism
Large steps create transient current spikes inside the DAC and output path. With finite supply impedance and shared return paths, these spikes translate into reference droop and ground bounce that directly modulate the output and couple into neighbors.
Knob
- Shorten transient current loops with local decoupling placed at the correct pins and return paths.
- Keep reference and analog return isolated from digital edge currents; avoid shared “thin neck” returns.
- Probe VREF/AVDD and a local ground-sense point during worst-case steps to confirm coupling.
Output buffer recovery & stability
Symptom
Overshoot/undershoot followed by a long tail; large steps show “slew-limited” ramps or plateaus; adding RC can slow recovery or trigger ringing.
Mechanism
The buffer operates in a different regime for large-signal steps: slew limits, output stage nonlinearity, and reduced phase margin with heavy capacitive loads can extend settling and create code-dependent recovery behavior.
Knob
- Use output isolation (Riso) to keep the buffer stable with capacitive loads and reduce overshoot.
- Define a realistic settling window (±x LSB/ppm) and measure worst-case vectors, not a single “typical” plot.
- Keep load, cable, and filter boundaries explicit; recovery problems scale with what the buffer must drive.
Load & parasitics
Symptom
Ringing at a repeatable frequency; behavior changes with cable length, probe grounding, or layout; a small series resistor sharply reduces ringing.
Mechanism
The output node forms a resonant network with Cload, ESR/ESL, package inductance, routing inductance, and cable impedance. The measurement loop can also add inductance and “create” ringing that is not present in the real system.
Knob
- Damp the network (Riso/termination) and keep high-current loops short to reduce ESL.
- State load conditions explicitly (Cload, cable, filter) when comparing consistency across codes.
- Use low-inductance probing (ground spring / coax) to avoid measuring probe artifacts.
Worst-case transitions: which codes are truly dangerous
Randomly stepping a few codes almost always misses the real worst case. The most dangerous behavior clusters around transitions that maximize switching activity (carry boundaries) or trigger internal switching-path changes (boundary regions). A good plan uses a fixed set of test vectors that cover these hotspots.
Vector: 0x0000 → 0xFFFF
Why: full-scale stress; exposes buffer recovery, load ringing, and reference droop under maximum swing.
Vector: 0xFFFF → 0x0000
Why: reverse full-scale stress; reveals direction-dependent overshoot and asymmetry in recovery.
Vector: 0x0FFF → 0x1000
Why: major-carry boundary; high multi-bit toggle activity; often the worst for glitch energy and edge-coupled spikes.
Vector: 0x1000 → 0x0FFF
Why: reverse major-carry; detects direction-sensitive injection and recovery differences across the same boundary.
Vector: 0x7FFF → 0x8000
Why: mid-scale carry boundary; common hotspot where switching stress and reference modulation show up clearly.
Vector: 0x8000 → 0x7FFF
Why: reverse mid-scale carry; captures asymmetry and confirms whether the boundary itself is the driver.
Vector: 0x8000 → 0x4000
Why: large step near mid-scale; stresses buffer recovery while probing typical boundary-adjacent behavior.
Vector: 0x4000 → 0x8000
Why: reverse of the prior vector; highlights direction-dependent overshoot and ground-bounce sensitivity.
Vector: 0x00FF → 0x0100
Why: small-scale carry boundary; isolates edge-coupled charge effects without full-scale buffer stress.
Vector: boundary codes → boundary codes
Why: internal switching-path changes cluster at boundary regions; this vector set is used to search and lock the true worst envelope.
Metrics & specs: how to quantify consistency (not just “glitch”)
Consistency is not a single waveform. It is an envelope of transient behavior across code positions and worst-case vectors. Peak alone can be misleading; stable judgments use area, settling-to-window, and residual-at-time under fixed conditions.
Measurement rule: keep bandwidth, sampling rate, load, and integration window consistent. Only then can envelopes be compared across codes or devices.
Glitch impulse (Area)
Unit: V·s (or nV·s)
Measures integrated transient energy. More stable than peak for comparing code regions and devices, and correlates with disturbance through RC loads.
Overshoot / undershoot (Peak)
Unit: V (or %FS)
Captures threshold risks (protection windows, comparator/ADC upset) and headroom. Always interpret together with area and settling.
Settling time to a window
Unit: s (or µs/ms)
Time until the waveform enters and stays inside ±(0.5 LSB / 1 LSB / x ppm). This defines when the bias/setpoint is usable again.
Residual error at a fixed time (Residual@t)
Unit: V (or LSB/ppm)
Remaining error at a defined delay after the update edge. Critical for timed sequences and control logic where decisions happen at a fixed time.
Code-dependent settling (Envelope)
Output: envelope across vectors
Overlay worst-case vectors and treat the outer bound as the real behavior. A single “typical” plot is not sufficient for disturbance-free switching.
Recommended judgment templates (no hard numbers)
- Settling spec: “Tsettle to ±(x LSB / x ppm) under the fixed worst-case vector set.”
- Impulse spec: “Area (V·s) envelope across carry boundaries and boundary zones within stated bandwidth/load.”
- Safety spec: “Peak overshoot/undershoot must remain below the system protection window under worst-case vectors.”
- Timing spec: “Residual@t at the system decision time must stay inside the control error budget.”
Metric selection depends on the application
Bias / setpoint switching
Use: Area + Tsettle(window) + Peak
Power trim / sequencing
Use: Peak + Residual@t + Tsettle
Closed-loop control
Use: Residual@t + Area + Envelope
AWG / fast waveform steps
Use: Peak + Area + Tsettle (fixed bandwidth/load)
Design levers inside the DAC (what the silicon may or may not do)
Some consistency improvements come from silicon features (update staging, deglitching, sample-and-hold), while others must be handled outside the chip (damping, reference isolation, layout). The fastest way to avoid surprises is to ask for vector-based transient data and confirm behavior by test when it is not published.
What silicon may provide (feature knobs)
- Segmented switching / optimized switching: can reduce worst carry behavior and concentrate hotspots differently.
- Deglitching / glitch reduction: may reduce peak and area, but can change the settling envelope.
- Sample-and-hold (S/H): can isolate update transients from the output during controlled timing.
- RTZ options: can reshape large-step behavior and recovery depending on the output network.
What must be handled outside the chip
- Damping and load definition (Riso/termination/RC) to control overshoot and ringing.
- Reference and return-path isolation to prevent droop/bounce from modulating Vout and neighbors.
- Measurement discipline to avoid probe-induced ringing and false envelope comparisons.
Update mechanism matters
- Single-buffer: write activity and update edge can coincide, increasing edge-coupled injection risk.
- Double-buffer / staged update: separates “write” from “update,” improving control of when the transient occurs.
- Synchronous latch / trigger: aligns updates across channels, but can amplify shared reference/return stress if the supply path is weak.
Vendor questions (copy/paste)
- Are major-carry and full-scale step vectors included in transient characterization?
- Provide conditions and plots for Peak, Area (V·s), Tsettle to ±(x LSB/ppm), and Residual@t.
- What update staging exists: single-buffer, double-buffer, or synchronous trigger?
- Does enabling deglitch / S/H / RTZ change settling-to-window and residual behavior?
- For voltage-output: recommended Riso range and supported capacitive load for stable settling.
- For current-output: large-step behavior with typical loads/TIA; any saturation/recovery guidance.
- Any notes on multi-channel simultaneous update and reference/ground coupling sensitivity?
If the datasheet does not publish transient data, run the fixed worst-case vector set (major-carry + full-scale) and capture Peak/Area/Tsettle/Residual under stated bandwidth and load; treat the envelope as the real spec.
Reference, supply, and grounding: preventing step-induced droop
Large steps amplify hidden power/return mistakes. If the transient current loops share the wrong return paths, the step pulls on VREF/AVDD and the local ground, turning a “code change” into a system-wide bump. Consistency improves when the major-step current paths are short, separated, and verified.
Path
- DAC switching loop: code activity → internal transient current → AVDD decoupling → return.
- Reference loop: VREF dynamic load → ref buffer/decoupling → quiet return.
- Output loop: buffer/load charging current → return path → local ground reference.
Placement
- Shortest loops: place decoupling at the correct pins and keep the return directly under the loop.
- Band-split decoupling: small/high-frequency close, bulk slightly farther, both with clean return.
- Reference isolation: VREF decoupling returns to a quiet region; avoid shared “neck-down” returns.
- AVDD/DVDD partition: keep fast digital return currents away from the analog reference point.
Verification
- Capture VOUT + VREF + AVDD (and a local ground sense) during major-carry and full-scale steps.
- Use the fixed worst-case vectors to expose coupling; typical steps often miss droop/bounce behavior.
- Perform A/B changes: decoupling placement and return routing should measurably shrink the envelope.
- Use low-inductance probing to avoid creating ringing that does not exist in the real loop.
Do
- Return VREF decoupling to a quiet ground region close to the VREF pin loop.
- Keep AVDD transient loops tight with local decoupling and continuous return beneath.
- Route digital edges so their return does not cross the analog reference point.
- Measure VREF/AVDD during worst-case steps to confirm the real coupling path.
- Use a single, controlled connection between quiet analog return and noisy digital return regions.
Don’t
- Do not share the VREF return with fast digital return currents through a narrow “neck.”
- Do not place reference/bulk capacitors far away with long inductive connections.
- Do not let multi-channel updates hit a weak shared supply path without local energy storage.
- Do not assume a clean VOUT plot means clean reference behavior; verify VREF/AVDD directly.
- Do not measure with long ground leads that add inductance and fake ringing.
Output network & load: taming overshoot and recovery without slowing everything
Overshoot and long settling tails are often created by the output network, not by the code step itself. The practical goal is to choose damping and load boundaries that reduce ringing and recovery problems without making every transition unnecessarily slow.
Decision mini-flow (waveform → knob)
- Fixed-frequency ringing → start with Riso, reduce loop inductance, and define cable/termination.
- Long tail / slow return → prioritize buffer recovery and explicit Cload boundaries.
- Peak crosses thresholds → limit overshoot first (Riso/termination), then re-check Tsettle.
- Multiple channels bump → verify ref/supply/return (H2-7) before changing the output network.
- TIA shows plateaus → treat it as saturation/recovery; tune feedback/boundaries and validate Residual@t.
- Close the loop → judge with Peak/Area/Tsettle/Residual envelopes (H2-5) using worst-case vectors.
Case 1: capacitive load
- Symptom: overshoot and ringing that scales with Cload.
- First knobs: Riso damping and shorter high-current return loops.
- Verify: Peak and Tsettle to a window under worst-case vectors.
Case 2: long cable / remote load
- Symptom: stronger ringing and sensitivity to probing/connection changes.
- First knobs: define termination or isolation, then control routing inductance.
- Verify: Peak and Area envelope across hotspot vectors.
Case 3: current-output DAC with external TIA
- Symptom: plateau/flat-top during large steps, followed by slow recovery.
- First knobs: treat as saturation/recovery and tune feedback/boundaries.
- Verify: Residual@t and Tsettle to the application window.
Multi-channel and cross-domain coupling: keeping other channels quiet
Consistency is system-level: a large step on one channel can disturb other channels if reference, ground return, or digital edges are shared incorrectly. The goal is to identify synchronous correlation, confirm the likely coupling path, and apply fixes that measurably shrink the bump envelope on quiet channels.
Measurement discipline: capture CH1 step trigger, CH2 output, VREF (pin or island), and a local ground sense at the same time. Use worst-case vectors and low-inductance probing.
Most common coupling paths
- Shared reference: CH1 step pulls VREF and CH2 follows as a small bump.
- Shared ground return: local ground moves during update; CH2 sees edge-aligned spikes.
- Digital IO / trigger injection: edges couple into analog nodes across routing/return.
Symptoms → Likely path → Fix (quick cards)
Symptom
CH2 shows a small slow bump aligned to CH1 step.
Likely path
Shared reference (VREF droop).
Fix
Star/split VREF branches; keep VREF return quiet; avoid shared return neck.
Symptom
CH2 shows sharp spikes; very sensitive to probe ground location.
Likely path
Shared ground return (bounce / neck-down).
Fix
Single-point tie; remove shared return neck; keep digital return away from analog reference.
Symptom
CH2 bump correlates with trigger/IO edges, not with step size.
Likely path
Digital IO injection (routing/return coupling).
Fix
Keep IO away; add series resistors; preserve continuous return under IO; avoid crossing analog zones.
Layout & routing for large-step immunity
Large-step immunity comes from visible return-path planning: reference returns stay quiet, output loops stay tight, and digital edges stay away from sensitive nodes. Use checklist items that can be verified by a repeatable measurement or an A/B layout change.
Layout checklist (each item has a verification)
✅ Reference island and return
🔎 Measure VREF(pin/island) during worst-case steps; the envelope should not move with CH1 updates.
✅ Output loop minimization
🔎 Compare ringing/peak with short vs extended loop routing; tight loops reduce ringing sensitivity.
✅ Digital IO kept away from VREF/VOUT
🔎 Toggle trigger/IO edges without code steps; bumps should not appear on quiet channels.
✅ Partition + single-point tie
🔎 Move the tie location in an A/B layout (or use jumpers); return-path coupling should change measurably.
✅ Thermal gradients kept away from ref/output
🔎 Run repeated high-rate large steps; baseline and Residual@t should not drift with time or temperature.
Production test: how to measure major-carry and consistency repeatably
A repeatable production test does not “look at one waveform.” It fixes the setup, runs a defined set of worst-case step vectors, captures the same probe points, computes the same metrics, and judges by window + envelope + percentiles instead of a lucky single capture.
Practical test gear & fixtures (examples with part numbers)
- Oscilloscope (time-domain peaks/ringing): Tektronix MSO64B (6 Series B) or equivalent bandwidth/record length class.
- Differential probing (when needed): Keysight N2790A (high-voltage differential probe) or an equivalent differential probe.
- Reference decoupling example: Murata GRM188R71C104KA01D (0.1 µF, 0603, X7R, 16 V) as a common local decap choice.
- Riso damping resistor example: Vishay TNPW0603 series (use 10 Ω / 22 Ω / 49.9 Ω as practical sweep points).
- 50 Ω capture path: SMA edge connector + 50 Ω terminator (generic equivalents are fine) to avoid long ground leads.
Low-inductance capture matters more than brand names. Prefer coax + termination or very short ground accessories over long probe ground leads.
Test flow (Setup → Stimulus → Capture → Compute → Judge)
Setup
- Fix load boundary (Riso / Cload / cable / termination) and keep it unchanged across runs.
- Define the probe reference (local GND sense point) and keep probe geometry consistent.
- Record temperature, supply rails, and output mode (buffer on/off, range, update mode).
Stimulus
- Run the required worst-case step vectors (below) with a fixed update cadence.
- For multi-channel devices: include simultaneous update vectors and staggered update as a comparison.
Capture
- Trigger on the same update event (LDAC / SYNC / strobe) and align time zero across vectors.
- Capture VOUT plus at least one system cause probe: VREF and/or AVDD and a local GND sense.
Compute
- Peak: overshoot/undershoot relative to final value (V or %FS).
- Glitch area: integrate deviation from the ideal step trajectory (V·s).
- Tsettle@window: time to enter and stay within ±(0.5 LSB / 1 LSB / x ppm).
- Residual@t: error at a fixed time (e.g., 10 µs / 100 µs / 1 ms) for control timing needs.
Judge
- Use a window (accuracy band), an envelope across vectors, and P95/P99 statistics across units.
- Avoid single-shot pass/fail. Require consistent behavior under defined corners (temp, supply, load).
Required step vectors (8–10) for major-carry and envelope coverage
Vector set
- 0 → FS and FS → 0 (maximum step energy, both directions).
- mid → mid + 1 and mid − 1 → mid (baseline small-step symmetry).
- 0x0FFF → 0x1000 and 0x1000 → 0x0FFF (major-carry boundary, both directions).
- quarter → three-quarter and three-quarter → quarter (common large transitions).
- Near-rail small step (tests output stage recovery near headroom limits).
- Multi-channel simultaneous update (if applicable; exposes shared-node coupling).
Why these vectors
- They hit the hotspot codes (major carry / boundary behavior) and directionality.
- They separate “core glitch” from shared reference/ground effects using correlated probes.
- They generate a meaningful settling envelope instead of a single optimistic waveform.
Pass/Fail templates (window + envelope + percentiles)
- Window: Tsettle within ±(0.5 LSB / 1 LSB / x ppm) for the target accuracy mode.
- Envelope: use worst-case across the required vectors (not a single vector).
- Percentiles: production limits by P95/P99 across units (e.g., P95(Tsettle) < limit; P99(area) < limit).
- Corners: repeat at cold/room/hot and supply tolerance; keep the load boundary fixed per SKU.
Common measurement mistakes that cause false conclusions
- Long probe ground lead creates fake ringing and inflated peaks.
- Bandwidth/record limits hide true peaks (looks “better” than reality).
- Inconsistent trigger alignment makes vectors non-comparable.
- AC coupling or drifting baselines corrupt integrated glitch area.
- Missing VREF/AVDD/GND-sense probes turns shared-node coupling into a “DAC core” misdiagnosis.
Engineering checklist & vendor questions (close the loop)
This section is designed to be copied into sourcing emails and design reviews. It turns major-carry consistency into specific questions, checklist items, and a repeatable production acceptance definition.
Questions to vendor (copy/paste)
- Are major-carry glitch/settling results available? Which code transitions are included (e.g., 0x0FFF↔0x1000, 0→FS, FS→0)?
- Under which measurement conditions are those results taken (load model, output mode, buffer on/off, update mechanism, update rate)?
- Is glitch area (V·s) provided or only peak? If only peak is shown, can area-based data be shared?
- What is the recommended VREF drive (buffer/no-buffer), decoupling topology, and “quiet return” guidance for major-step immunity?
- Are there notes on AVDD/DVDD partition and return-path control for large code steps?
- For multi-channel parts: what are the simultaneous update skew and any coupling data during shared-node stress?
- If datasheet does not include this, is there an application note, eval-board report, or test script that matches the vectors in H2-11?
Design review checklist (copy/paste)
- ✅ Worst-case vectors are fixed (10 set) and automated; alignment trigger is consistent across captures.
- ✅ Metrics are defined: Peak, Glitch area, Tsettle@window, Residual@t; envelope is computed across vectors.
- ✅ VREF island/return is quiet; VREF probe confirms minimal droop during major-carry and full-scale steps.
- ✅ AVDD/DVDD returns do not share a narrow neck; single-point tie is explicit and documented.
- ✅ Output damping strategy is defined (Riso/termination/Cload boundary) and verified on worst-case vectors.
- ✅ Multi-channel update plan exists (simultaneous vs grouped/staggered) and quiet-channel bump is measured.
- ✅ Production acceptance uses window + envelope + P95/P99 percentiles across corners (temp, supply, load).
Copyable mini-BOM (examples with part numbers)
- VREF/AVDD local decap: Murata GRM188R71C104KA01D (0.1 µF, 0603, X7R, 16 V)
- Riso damping sweep: Vishay TNPW0603 series (10 Ω / 22 Ω / 49.9 Ω options)
- Cload sweep: C0G/NP0 100 pF / 1 nF / 10 nF; X7R 0.1 µF / 1 µF (generic equivalents)
- Coax capture: SMA edge connector + 50 Ω terminator (generic equivalents)
- Differential probing (when required): Keysight N2790A or equivalent
- Scope class reference: Tektronix MSO64B (6 Series B) or equivalent
Equivalent parts are acceptable as long as the electrical intent is preserved: low-inductance decoupling/return, controlled damping, and repeatable probing.
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FAQs: major-carry and code-to-code consistency
These FAQs close long-tail questions without expanding the main text. Each answer follows the same structure: Short answer → Quick checks → Likely causes → Fix order.
Why does the output “jump” only on certain code boundaries?
Short answer: Some boundaries toggle many internal switches at once (major-carry / segment boundaries), creating larger charge injection and a worse settling envelope.
- Quick checks: run 0x0FFF→0x1000 and the reverse; compare to mid→mid+1; overlay waveforms to see the envelope spread.
- Likely causes: multi-bit toggle event, segment switching, shared reference/return hit at high activity.
- Fix order: confirm VREF/ground stability → add output damping (Riso) → adjust update timing/grouping → re-check vectors.
How to tell DAC core glitch vs reference droop vs ground bounce?
Short answer: Correlate VOUT with VREF and a local ground sense at the same trigger; shared-node problems move VREF/ground with the event.
- Quick checks: measure VOUT + VREF(pin/island) + local GND sense simultaneously; repeat with different probe ground locations.
- Likely causes: VREF droop (slow bump), ground bounce (edge-aligned spikes), IO edge injection (bump follows strobe edges).
- Fix order: make return paths explicit (single-point tie) → isolate VREF branches → slow/route IO away → then revisit core/glitch controls.
Peak looks OK, but the system still misbehaves—what metric is missing?
Short answer: Peak is not enough. Glitch area and Residual@t capture “energy” and “timing-critical error” that can trip comparators or control loops.
- Quick checks: compute glitch area (V·s) and Residual@t (e.g., 10 µs/100 µs/1 ms) for the same vectors.
- Likely causes: long settling tail, slow reference recovery, output buffer large-signal recovery.
- Fix order: tighten VREF/AVDD transient paths → improve output damping/stability → adjust update strategy → re-judge by envelope + percentiles.
Why does adding an RC filter sometimes make settling worse (or a loop unstable)?
Short answer: RC reduces high-frequency content but can add delay and interact with output impedance/driver stability, turning a clean step into a longer tail or ringing.
- Quick checks: compare step responses with/without RC at the same load; inspect phase-like behavior via overshoot and tail length.
- Likely causes: driver stability margin reduced, RC pole too low, cable/inductance forming a resonant network.
- Fix order: start with Riso and layout loop control → then set RC for the real bandwidth need → verify Tsettle@window and Residual@t.
Output oscillates with a capacitive load—where to start (Riso range)?
Short answer: Treat it as an output stability problem first. A small series isolation resistor near the output usually provides the fastest win without slowing everything.
- Quick checks: sweep Riso in practical steps (10 Ω → 22 Ω → 49.9 Ω) and keep it close to the DAC/driver pin.
- Likely causes: capacitive load + trace inductance, insufficient phase margin of the output buffer/driver.
- Fix order: add/sweep Riso → tighten output loop/return path → adjust Cload/termination → re-check major-carry vectors.
Multi-channel DAC: why do quiet channels bump when one channel steps?
Short answer: Quiet-channel bumps are usually shared-node coupling: shared VREF, shared ground return, or digital edge injection during the update event.
- Quick checks: observe CH2 VOUT while CH2 code is fixed; also probe VREF and local GND sense; change only IO edge rate to see sensitivity.
- Likely causes: ref droop coupling, return-path neck-down, IO routing crossing analog zone.
- Fix order: isolate VREF branches/returns → fix single-point tie and remove shared necks → route/slew-limit IO → consider staggered update grouping.
No LDAC / no synchronous latch—how to get “almost simultaneous” updates?
Short answer: Without a true hardware latch, “almost simultaneous” is a timing compromise. The safest approach is grouped updates with measured skew and controlled shared-node stress.
- Quick checks: measure inter-channel skew by capturing two channels on the same trigger; test both simultaneous and staggered sequences.
- Likely causes: bus write jitter, software scheduling, shared-node current peaks when many channels update together.
- Fix order: enforce deterministic write order → group channels by sensitivity → add ref/return isolation so simultaneous events do not move shared nodes.
Why is the worst-case different for up-step vs down-step?
Short answer: Up and down steps can stress different recovery paths (output stage sourcing vs sinking, reference recovery, clamp behavior), so asymmetry is normal and must be tested both ways.
- Quick checks: always pair vectors (A→B and B→A) and compare Peak, Area, and Tsettle@window.
- Likely causes: output stage headroom differences, recovery from saturation, rail-dependent supply droop direction.
- Fix order: confirm headroom and load boundary → improve damping/stability → strengthen VREF/AVDD transient support → judge by envelope.
How to define pass/fail without being fooled by one lucky capture?
Short answer: Use a fixed vector set and judge by accuracy window, worst-case envelope across vectors, and P95/P99 statistics across units and corners.
- Quick checks: lock trigger alignment; repeat each vector multiple times; compute envelope and percentiles instead of best-case.
- Likely causes: non-deterministic triggers, probe variability, environment/corner sensitivity.
- Fix order: standardize setup and probing → freeze vector list → define window + envelope + P95/P99 → then tighten layout/decoupling if needed.
A spur appears after a large code step—does it mean an “RF problem”?
Short answer: Not necessarily. A step can excite periodic recovery (ringing, shared-node droop, IO injection) that shows up as a spur. Treat frequency-domain results as supporting evidence.
- Quick checks: confirm the spur aligns with the step event timing; inspect VOUT ringing and VREF/AVDD droop in time-domain.
- Likely causes: output network resonance, ref/ground coupling, deterministic IO edge injection.
- Fix order: damp the output network → isolate VREF/returns → tame IO edges/routing → re-check spur as a confirmation.
Why do results change a lot between benches or probes?
Short answer: Probing and triggering often dominate the observed glitch. Ground lead inductance, bandwidth limits, and inconsistent time alignment can create or hide peaks and ringing.
- Quick checks: use coax + 50 Ω termination when possible; keep ground path short; lock trigger to the same strobe edge; avoid AC coupling for area measurements.
- Likely causes: long ground leads, insufficient bandwidth/record, different reference points for “ground”.
- Fix order: standardize fixture and probe geometry → standardize trigger alignment → then compare true device-to-device variability.
Which 8–10 step vectors are the minimum set for production screens?
Short answer: The minimum set must cover full-scale energy, major-carry boundaries, small-step baseline, directionality, and at least one mid-large step; multi-channel parts also need a simultaneous update vector.
- Quick checks: include 0↔FS, 0x0FFF↔0x1000, mid↔mid±1, quarter↔three-quarter, near-rail small step, and (if applicable) multi-channel simultaneous update.
- Likely causes: skipping boundary vectors misses the true worst-case envelope and hides coupling hot spots.
- Fix order: lock the vector list → lock load and probing → judge by window + envelope + percentiles.
