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String DAC (Resistor-String): Monotonic Precision for Setpoints

String DAC (Resistor-String): Monotonic Precision for Setpoints

← Back to:Digital-to-Analog Converters (DACs)

A string DAC is the “programmable divider” choice when the priority is monotonic, low-noise, high-resolution setpoints—not speed. System success depends less on the DAC core and more on reference quality, buffer stability with real loads, and controlling leakage/thermal drift through layout and verification.

What this page solves

This page focuses on the resistor-string (string) DAC architecture used for precision setpoints, biasing, and temperature-control loops. It explains why string DACs are naturally monotonic and low-noise, why they are typically slower, and how to design and verify a complete system (reference → string/taps → buffer → load) without surprises in drift, settling, or stability.

Scope rule: this page goes deep on string DAC mechanisms, error ownership, design knobs, and verification tests. Other DAC families are referenced only as one-line “go there if…” pointers.

  • Mechanism (why it behaves this way): monotonic stepping, code-dependent output impedance, and the dominant noise/drift paths.
  • Design ownership (who causes what): map end accuracy and stability to reference, string/tap network, buffer, load, layout, and thermal gradients.
  • Verification (how to prove it): a minimal, repeatable test set for monotonicity, INL/DNL, low-frequency noise, settling, and code-step artifacts.

Not expanded here (one-line pointers only): R-2R ladder (area-efficient mid/high speed), segmented (glitch control with thermometer/binary), current-steering (RF/wideband), delta-sigma DAC (noise shaping + narrow band), JESD204B/C synchronization (SYSREF/LMFC alignment).

String DAC page map: mechanism, ownership, knobs, verification Four-step flow chart connecting string DAC behavior to error ownership, design controls, and a verification test set for precision setpoints. String DAC: deep path from behavior to proof Mechanism → Ownership → Knobs → Verification Mechanism Monotonic steps Zout changes Noise / drift Ownership Reference String / taps Buffer / load Knobs BW limiting Stability margin Thermal control Verification Monotonic INL / DNL Noise / settling Rule: one architecture per page; cross-family details are kept as jump links.

Definition & topology

A string DAC is a precision voltage-divider DAC built from a uniform resistor string and a tap selector. A code selects one node (tap) along the string, and an output buffer isolates the divider from the load. The topology behaves like a programmable divider that favors clean, repeatable DC/low-frequency setpoints over very high update rates.

Ideal transfer: VOUT = VREF × k / 2^N, where k = 0…(2^N−1) and LSB = VREF / 2^N. The LSB becomes the engineering ruler for noise, drift, and settling targets later in this page.

  • Key property to remember: the effective output source impedance is code-dependent. This is the root cause of many “system surprises” (buffer stability, settling, load sensitivity).
  • Another critical distinction: monotonicity (no reverse steps) is not the same as perfect linearity (INL/DNL). A design can be monotonic while still having measurable INL due to mismatch or thermal gradients.
String DAC topology: VREF, resistor string, tap selector, buffer, load Block diagram of a resistor-string DAC with an inset staircase transfer and an icon showing code-dependent output impedance. VREF Low noise Low drift Resistor String Tap Selector Code → tap Monotonic Buffer Drive load Stability Ideal transfer (staircase) Code k VOUT LSB = VREF / 2^N Code-dependent output impedance Zout depends on k Topology: programmable divider + selector + buffer, optimized for precision setpoints.

Monotonicity: what it guarantees, what can break it

Monotonicity means the output never steps backward when the code increases (ΔVOUT(k→k+1) ≥ 0). It is a safety property for “setpoint” systems: commands move in the intended direction. However, monotonicity is not the same as perfect linearity. A string DAC can be monotonic while still showing INL due to gradient, endpoint effects, or code-dependent loading.

Practical rule: treat monotonicity as a system attribute (reference + taps + buffer + load), not as a standalone “DAC spec”. The most common failures are triggered by boundary conditions.

What monotonicity guarantees (and what it does not)

  • Guaranteed: an increasing code produces a non-decreasing steady-state output. This prevents “reverse moves” in biasing and temperature-control loops.
  • Not guaranteed: equal step size (DNL≈0) or a straight transfer curve (INL≈0). Step widths can vary yet remain positive.
  • Also not guaranteed: clean transitions during the step. If a downstream system samples too early, transient artifacts can look like a backward step.

Root causes that can break monotonic behavior

  • Switch path effects: code-dependent RON, charge injection, and tap-node kickback. These often appear as step-dependent transients and settle-time sensitivity.
  • Leakage and bias currents: PCB contamination/humidity, ESD paths, and buffer input bias. These distort tap voltages by loading a code-dependent source impedance.
  • Thermal gradients: temperature non-uniformity along the string changes segment ratios over time or airflow, shifting small steps into “noise-like” ambiguity.
  • Saturation and clamps: reference/buffer headroom limits, output current limit, or protection clamps entering conduction. Once the buffer is non-linear, the DAC transfer is no longer in control.

Engineering conditions for “structural monotonicity” to hold

  • Buffer stays linear: no output swing or load current condition that triggers saturation or limiting.
  • Tap node is not DC-loaded: leakage + input bias stays well below the allowed error budget for the smallest step.
  • Sampling happens after settling: the measurement/control system must not observe mid-transition artifacts.
  • Reference remains stiff: code steps do not modulate the reference via poor decoupling or return paths.
  • Thermal environment is controlled: gradients and airflow sensitivity are kept repeatable.
  • No unintended clamp conduction: protection devices remain off in the normal operating window.
Monotonicity for string DACs: definition, break mechanisms, conditions, verification Framework diagram showing monotonicity definition, four failure mechanism categories, a checklist of engineering conditions, and a minimal verification set. Monotonicity is a system property Definition → Break mechanisms → Conditions → Verification Definition ΔV(k→k+1) ≥ 0 steady-state Break mechanisms Switch path / injection Leakage / bias load Thermal gradients Saturation / clamps Conditions (must hold) Buffer linear region Tap not DC-loaded Sample after settling Reference is stiff Thermal is controlled No clamp conduction Minimal verification DC code sweep Transient window Temp / humidity stress

Linearity model: INL/DNL and code-dependent errors

Linearity describes how closely the string DAC follows an ideal “uniform step” transfer. DNL captures step-to-step width variation relative to 1 LSB, while INL captures the accumulated curvature of the overall transfer. A string DAC is often selected for monotonic behavior, but system accuracy still depends on understanding where INL and DNL come from and which contributors are code-dependent.

Scope rule: this section models resistor-string + tap selector behavior only. Thermometer/binary segmentation strategies belong to the Segmented DAC page.

How string errors map to INL (gradient, mismatch, endpoint effects)

  • Gradient: slow variation along the string (process stress or temperature gradient) bends the transfer curve. It tends to show up as INL curvature and drift with board thermal conditions.
  • Random mismatch: segment-to-segment variation changes individual step widths, driving DNL. The accumulated effect can also contribute to INL but with a different statistical signature than a smooth gradient.
  • Endpoint effects: the first/last taps often see different parasitics and routing, making DNL/INL worse near rails. This is a common reason the “middle codes” look better than the extremes.

Switch-network errors that are code-dependent

  • Static (steady-state) loading: code-dependent RON and leakage interact with a code-dependent source impedance, shifting the effective tap ratio differently across the code range.
  • Dynamic (transition) artifacts: charge injection and kickback produce step-dependent transients. These can corrupt sampled measurements if the observation window is too early, even if DC INL looks acceptable.
String DAC linearity: INL vs DNL sources and code-dependent errors Diagram separating INL and DNL concepts, mapping resistor-string contributors and switch-network code-dependent errors, and highlighting endpoint sensitivity across the code range. INL and DNL are different signatures String contributors + switch-network code dependence Signatures INL: curvature DNL: step widths Resistor-string contributors Gradient → INL curvature Mismatch → DNL variation Endpoint effects → rail codes Switch network Static Ron / leakage Dynamic injection / kickback Code range map (where problems concentrate) 0 Full-scale endpoint endpoint mid codes: typically cleaner Keep this page focused on string topology; segmentation strategies are handled elsewhere.

Noise & resolution floor

The “usable resolution” of a string DAC is set by the system noise floor in the bandwidth that matters to the application. The same DAC can appear quiet or noisy depending on bandwidth, filtering, and how low-frequency noise is separated from drift. Use the LSB as the ruler: LSB = VREF / 2^N.

Engineering threshold: aim for RMS output noise < 0.5 LSB in the effective bandwidth. This keeps small setpoint changes distinguishable and repeatable.

Who dominates (and in which bandwidth)

  • Wideband white noise: dominated by buffer voltage noise and thermal noise contributions, and it scales strongly with the measurement bandwidth. Bandwidth limiting is the primary lever.
  • Reference noise: transfers directly to the output and often becomes the dominant contributor in precision setpoint systems, especially when the output is filtered and the buffer is already quiet.
  • Low-frequency 1/f noise: dominates stability in slow loops and appears in 0.1–10 Hz measurements. It is not removed by simple “short-window” averaging.
  • Drift (not noise): slow movement with temperature, airflow, or self-heating. Drift can look like noise if the observation window is long enough.

Turning “< 0.5 LSBrms” into design actions

  1. Set the ruler: choose VREF and N, then compute LSB.
  2. Define effective bandwidth: setpoint loops and bias rails usually allow strong bandwidth limiting; waveforms require more bandwidth and therefore stricter noise requirements.
  3. Allocate ownership: reserve noise budget for reference, buffer, and remaining contributors (string + pickup). If one block consumes most of the budget, improve that block before “chasing” minor effects.
  4. Use filtering deliberately: bandwidth limiting reduces wideband noise but increases settling time. The filter target must match the required update/settling behavior.

DC stability: 0.1–10 Hz noise vs drift

  • 0.1–10 Hz noise: looks like stochastic wandering around a mean within a short time window; it improves with careful bandwidth limiting and repeated averaging strategies.
  • Drift: shows correlation with temperature, airflow, or warm-up; averaging does not guarantee removal. If the mean value moves over minutes/hours, treat it as drift and track its cause.
  • Minimum separation test: repeat measurements with stable ambient conditions, then introduce a controlled temperature change; correlated movement indicates drift dominance.
Noise and resolution floor for string DACs Framework diagram mapping noise sources across bandwidth, showing a 0.5 LSB RMS target and practical design actions such as bandwidth limiting and reference/buffer selection. Noise ownership depends on bandwidth Wideband → 1/f → Drift Bandwidth Wideband 0.1–10 Hz Drift Noise sources Thermal Buffer Reference 1/f + LF Drift (thermal / environment) Target < 0.5 LSB RMS noise Actions Limit BW Improve ref Improve buf 0.1–10 Hz stability needs: low 1/f + controlled drift Bandwidth controls wideband noise; environment controls drift signatures.

Output impedance & buffer stability

The biggest system pitfall of a string DAC is that the effective output source impedance is code-dependent. The same load and the same output network can produce different settling and stability behavior at different codes. A buffer is required not only for drive strength, but to make the output behavior predictable.

Practical rule: evaluate stability and settling at multiple codes, especially around mid-scale where the source impedance sensitivity is often highest.

Why buffering is mandatory

  • Isolation: prevents load changes and cable capacitance from turning into code-dependent DC errors and gain variation.
  • Predictable settling: converts a code-dependent divider node into a controlled output pole that can be verified and specified.
  • Stable filtering and protection: provides a robust interface for RC filters, clamps, and long interconnects without disturbing the tap network.

How Cload, cables, and RC networks cause oscillation

  • Large capacitive load: reduces phase margin and creates ringing or oscillation if the buffer is not compensated for Cload.
  • Long cables: add distributed capacitance/inductance and reflections; the output can look “randomly unstable” across setups.
  • RC filter placement: placing a large capacitor directly at the buffer output without isolation commonly triggers instability.
  • Clamp conduction near rails: protection devices can turn on during transients and behave as a non-linear load that slows recovery.

Practical stabilization strategies (string-DAC focused)

  • Isolation resistor (Riso): place a small series resistor between buffer output and large Cload/cable. This decouples the capacitive load and restores phase margin.
  • Bandwidth limiting: use controlled output bandwidth to reduce both wideband noise and stability stress, acknowledging the settling-time tradeoff.
  • Load partitioning: keep heavy capacitance and long interconnects on the “far side” of Riso, and validate across codes.
  • Verification habit: step-response checks at low/mid/high codes under minimum and maximum load are mandatory for sign-off.
Code-dependent output impedance and buffer stability for string DACs Diagram showing code-dependent source impedance, comparing an unstable direct-load connection to a buffered and isolated output using an isolation resistor, and listing stabilization actions. Zout changes with code Buffer + isolation makes behavior predictable Zout(code) trend low mid high Direct load (risk) Tap Cable / Cload ringing / instability Buffered + isolated Tap Buffer Riso Cable / Cload Stable System actions Add Riso Limit BW Validate step response (low/mid/high)

Speed & settling: why it’s slower

A string DAC is optimized for clean, monotonic setpoints, not for maximum update rate. The practical speed limit is usually not the tap network alone, but the settling chain: selector → buffer → output network (Riso/RC) → load. “Fast” only has meaning when the settling band is defined (for example, ±0.5 LSB or ±X ppm).

Sign-off rule: settling time must be checked at multiple codes and under representative loads, using a defined error band (not an undefined “looks stable” judgment).

What sets the update rate and settling time

  • Selector / tap switching: creates a transition artifact (glitch impulse) and a brief tap-node disturbance. This is usually short, but it can dominate if the observation window is too early.
  • Buffer: often the main limiter. Large steps can enter slew-rate behavior first, then converge in small-signal mode. Output headroom, current limit, and stability margin set the recovery tail.
  • Output network (Riso/RC): bandwidth limiting lowers noise but increases settling time. Large capacitive loads without isolation can introduce ringing and extend settling.
  • Load: cables and remote inputs add capacitance/inductance and can create reflections or slow recovery. The same DAC can “settle differently” across setups.

Small step vs major step (why the tests differ)

  • Small steps (a few LSB): the final error band can be comparable to the noise floor. A measurement with excessive bandwidth may falsely report “not settled” because it is observing noise.
  • Major steps (large code moves): dominated by slew-rate, overshoot/ringing, and recovery tail. These transitions must be captured with an observation window that includes the full recovery behavior.
  • Practical criterion: use a two-stage judgment for major steps: (1) coarse arrival into a wide band, then (2) final settling into the target band (±0.5 LSB or ±X ppm).

When a string DAC is not the right fit (jump conditions)

  • Wideband waveforms or RF modulation: prefer current-steering / RF DAC architectures.
  • Higher speed with strong linearity control: consider segmented DAC families.
  • Very low noise with narrow bandwidth: delta-sigma DACs are often a better match.
  • High-speed multi-channel serial alignment: use JESD204-enabled DAC solutions and timing alignment.
String DAC settling: chain, step classes, and jump conditions Framework diagram showing the settling chain from selector to load, comparing small-step and major-step behaviors, and listing jump conditions where other DAC architectures are a better fit. Settling chain defines speed Selector → Buffer → Riso/RC → Load Selector Buffer Riso / RC Load Step classes Small step noise-limited Major step slew + tail Jump conditions Wideband / RF Higher speed linearity ΔΣ narrowband Define settling band (±0.5 LSB or ±X ppm) before comparing “speed”.

Reference, biasing, and drift chain

In precision setpoint systems, long-term accuracy is often dominated by the reference and distribution chain, not by the DAC core. A stable output requires controlling the reference accuracy and drift, then preventing the system (wiring, return paths, and thermal gradients) from converting a good reference into a drifting remote setpoint.

Ownership map: drift must be assigned to the correct block (reference, distribution/returns, thermal environment), then verified with targeted tests instead of broad “averaging”.

Reference terms that become system error

  • Initial accuracy: sets the starting absolute error after power-up or production calibration.
  • Tempco: sets the slope of error vs temperature and defines how much thermal tracking is required.
  • Long-term drift: sets recalibration needs and determines whether “stable today” stays stable over months.

How the system turns “good DAC” into “drifting setpoint”

  • Remote load and line loss: voltage drop and return current variations make the remote setpoint differ from the board value. Compare board-side and remote measurements to separate DAC error from distribution error.
  • Ground bounce and return paths: digital or power return currents shift the local reference point. A stable DAC output can still look like a drifting setpoint when the ground reference is moving.
  • Thermal gradients: the reference, buffer, and string may not share the same temperature. Airflow and nearby heat sources can introduce slow, repeatable offsets that mimic “random drift”.

Practical error ownership (without generic methodology)

  • Reference: track initial accuracy, tempco, and long-term drift as the primary error terms.
  • Distribution/returns: treat line loss and ground movement as separate system errors and validate with two-point measurement.
  • Thermal environment: verify airflow/heat-source sensitivity with controlled perturbations and correlation.
Reference and drift chain ownership for string DAC systems Block diagram mapping reference accuracy and drift into system errors through distribution, return paths, and thermal gradients, highlighting board versus remote setpoint behavior. Drift chain: from reference to remote setpoint Reference → Distribution/Returns → Thermal → Remote load Reference Initial / Tempco Long-term Distribution Line loss Ground bounce Thermal Gradient Airflow Remote Load Board vs remote setpoint check Board measurement near DAC/buffer Remote measurement at the real load Difference reveals distribution/return/thermal errors

Layout, leakage, and thermal gradients

In precision setpoint designs, failures are frequently caused by leakage and thermal behavior rather than by the DAC core. Surface leakage (contamination and humidity), thermal gradients (self-heating and airflow), and return-path mistakes can create slow offsets that look like “random drift”.

Key idea: leakage is a DC error mechanism (not noise), and thermal gradients are often repeatable when perturbed. Both must be treated as first-class system error terms.

Leakage: contamination and humidity can dominate 16-bit setpoints

  • What it does: surface leakage behaves like an unknown DC current path that biases high-impedance nodes and shifts the setpoint.
  • Common triggers: flux residue, ionic contamination, condensation, and leakage through protection devices.
  • Signature: offsets change with humidity, board cleanliness, connector proximity, and sometimes with code (due to code-dependent source impedance).

Thermal gradients and airflow sensitivity: why “it drifts with time”

  • Self-heating: local power dissipation changes junction temperatures and causes slow settling of the output value.
  • Gradients: reference, buffer, and resistor string may not track the same temperature, creating ratio-like drift.
  • Airflow: fan state and airflow direction can modulate local temperatures and produce repeatable slow offsets.

String-DAC layout actions (precision-focused)

  • Isolation moat: keep-out gaps around sensitive nodes to break surface leakage paths.
  • Guard ring: surround high-impedance nodes with a guard at a similar potential to reduce leakage-induced offsets.
  • Kelvin reference/ground: define a true measurement return point and avoid routing large return currents through it.
  • Connector discipline: avoid placing sensitive nodes near connectors where contamination and humidity exposure are highest.
  • Thermal island: place reference + buffer + DAC in a coherent thermal zone, away from strong heat sources and airflow edges.

Minimum diagnostics (fast checks)

  • Humidity/cleanliness check: repeat key codes before/after cleaning or with controlled humidity change.
  • Airflow check: toggle fan state or block airflow and look for correlated output movement.
  • Return-path check: compare board-side and remote measurements to isolate distribution/ground shifts.
Precision failure triangle for string DAC setpoints Triangle framework showing leakage, thermal gradients, and return paths as the main precision failure causes, with practical layout actions such as guard rings, isolation moats, Kelvin returns, and thermal zoning. Precision failure triangle Leakage · Thermal · Return paths Leakage Flux / Humidity Return Kelvin / GND Thermal Gradient / Airflow Layout actions Isolation moat Guard ring Kelvin return Thermal island Treat leakage as DC error and thermal gradients as repeatable drift paths.

Measurement & verification

Verification should be built around a minimum test set that captures monotonicity, INL/DNL, noise (wideband and 0.1–10 Hz), settling (small and major steps), and glitch/overshoot. Each test must define bandwidth, observation window, and pass criteria to avoid confusing noise or drift with static errors.

Always define three things before measuring: bandwidth, window, and error band. Without them, “pass/fail” becomes a measurement artifact.

Minimum test matrix (string-DAC focused)

Test Method Pitfall Pass criteria
Monotonic Up/down code sweep + focused codes Noise mistaken as non-monotonic ΔV ≥ 0 within uncertainty
INL/DNL Controlled sweep + stable reference Thermal drift during long scans Within datasheet band
Noise (BW) RMS with defined bandwidth Bandwidth mismatch across tests RMS < 0.5 LSB
0.1–10 Hz Long record + LF filtering Drift mistaken as noise Noise + drift separated
Settling Small + major steps Window too short (miss tail) Within error band
Glitch Scope capture on key code jumps Probe/loading distortion Peak + duration limits

Glitch and overshoot (string-DAC measurement style)

  • Capture key jumps: mid-scale transitions and application-critical code boundaries.
  • Control probe loading: verify that the probe and cable do not create ringing that is not present in the real system.
  • Use consistent criteria: peak amplitude, pulse duration, and return-to-band time (aligned with the settling error band).
Minimum verification set for string DACs Diagram showing six core tests (monotonicity, INL/DNL, wideband noise, 0.1–10 Hz noise, settling, glitch) linked to common pitfalls (bandwidth, reference stability, thermal drift, windowing) and unified pass criteria. Minimum verification set Define bandwidth · window · error band Core tests Monotonic sweep INL / DNL Noise (BW) 0.1–10 Hz Settling Glitch Common pitfalls Bandwidth Reference Thermal drift Windowing Unified criteria Error band RMS noise Repeatability

Engineering checklist

This checklist turns string-DAC setpoint requirements into sign-off items. Each line maps requirements → parameters → side effects → verification and can be copied into project reviews.

Use one consistent “definition of done”: define bandwidth, observation window, and error band (±0.5 LSB or ±X ppm), then sign off across representative codes and loads.

Requirements (inputs)

Parameters (what must be specified or requested)

Side effects (what can go wrong)

Verification (minimum sign-off set)

Engineering checklist flow for string DAC projects Four-step flow from requirements to parameters to side effects and verification, showing key sign-off items for load, reference, buffer stability, drift, protection, and production test coverage. Checklist flow Requirements → Parameters → Side effects → Verification Requirements Parameters Side effects Verify Load / Cload Cable Error band Protection Vref Buffer Riso / RC Layout Code-dependent Leakage Thermal drift Return paths Monotonic INL/DNL Noise Settling Sign off across representative codes, loads, and environmental states.

Applications, IC selection logic, and FAQ

Applications (string-DAC typical)

  • Precision bias / setpoints: clean, monotonic programmable dividers for thresholds, bias rails, and trim points. Focus is absolute stability and low noise, not bandwidth.
  • Temperature control setpoints: stable control targets for TEC/heater loops where low-frequency noise and drift dominate perceived stability.
  • Instrumentation trim: offset/gain trims and calibration setpoints where repeatability and monotonic updates matter more than speed.
  • Slow ramps and sweeps: low-rate sweeps that must remain smooth; sign off against settling and glitch on major transitions.

IC selection logic (fields → risk mapping → inquiry template)

Fields to request

  • Monotonic guarantee conditions (temperature, supply, load range).
  • INL/DNL (typ/max) across temperature.
  • Reference requirements: Vref range, input current, noise impact.
  • Output buffering: max output current and stability guidance with Cload/cables (recommended Riso).
  • Settling time to a defined band (small-step and major-step) with explicit test conditions.
  • Glitch/overshoot metrics and measurement setup (string-DAC style).
  • Protection: ESD rating, short/overload behavior, recovery characteristics.
  • Interface/update behavior: default code, update trigger, and multi-channel alignment support (basic LDAC-style triggers).

Risk mapping

  • Large Cload or long cables → stability risk and extended settling tail.
  • High humidity or contamination exposure → leakage-driven DC offset risk.
  • Airflow or nearby heat sources → thermal-gradient drift risk.
  • Remote setpoints → line-loss and return-path error risk (board vs remote mismatch).
  • ESD/short stress → post-stress offset/noise/settling change risk.

Inquiry template (copy/paste)

Target: N-bit string DAC setpoint. Output range: ___ V. Error band: ±___ ppm (or ±0.5 LSB). Load model: Rload ___ Ω, Cload ___ nF, cable length ___ m. Environment: ___ °C, humidity ___, airflow states ___.
Please provide: monotonic guarantee conditions, INL/DNL across temperature, settling time to the stated error band for small-step and major-step, buffer stability guidance with the stated Cload/cable (recommended Riso/RC), glitch/overshoot metrics with test conditions, and ESD/short behavior plus recovery characteristics.

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FAQ (string-DAC only)

Does monotonic guarantee mean perfect linearity (small INL)?
No. Monotonicity only guarantees the output does not go backward when the code increases. INL can still be significant due to resistor gradients, endpoint effects, and code-dependent switching errors. Use monotonic tests for “no backward steps” and INL/DNL characterization for linearity.
Why can settling time vary with code?
A string DAC’s effective source impedance varies with the selected tap. With the same output network and load capacitance, different codes can create different poles and recovery behavior. Sign off settling across representative codes, not only at one point.
How much Cload typically starts to cause ringing or instability?
The threshold depends on the output buffer and the presence of isolation (Riso). A small capacitive load may be fine, while longer cables or larger capacitors can reduce phase margin and create ringing. The practical rule is to validate with the real load/cable and use Riso/RC to control the pole and damping.
What is the purpose of Riso and where should it be placed?
Riso isolates the buffer from capacitive loads and helps prevent instability and long ringing tails. Place it close to the buffer output, then connect the cable/capacitor after Riso. Adjust RC only with a defined bandwidth and settling target.
Why can humidity or flux residue shift a “stable” setpoint?
Surface contamination can create leakage paths that behave like a DC bias current. That changes the measured setpoint and can be strongly humidity-dependent. Guard rings, isolation moats, and process controls (cleaning/coating) are often required for high-resolution stability.
How long should warm-up be before precision readings?
Warm-up time is set by reference and thermal gradients, not by the DAC code alone. Establish a warm-up window by logging output vs time after power-up under the expected airflow and nearby heat conditions, then define the “measurement-ready” criterion.
How to distinguish 0.1–10 Hz noise from drift?
Use a long record and a defined low-frequency band. Noise appears as bounded random variation within the band, while drift shows a trend correlated with temperature, airflow, or time since power-up. Treat drift as a system error term to be assigned and mitigated.
How should glitch impulse be measured for a string DAC?
Capture time-domain transitions on key code jumps (especially mid-scale and application-critical boundaries) using a measurement setup that does not add ringing. Use peak amplitude, duration, and return-to-error-band time as criteria, aligned with settling requirements.
Board output is stable but the remote load drifts. What should be checked first?
Measure board-side and remote-side simultaneously. A difference that changes with load current points to line loss or return-path movement. If the difference changes with airflow or temperature, thermal gradients in the distribution path are likely contributors.
ESD passes but accuracy becomes worse. What is the likely cause?
ESD can create latent damage or leakage shifts in protection paths, output stages, or nearby high-impedance nodes. Compare pre/post-stress offset, low-frequency noise, and settling. If humidity sensitivity increases afterward, suspect leakage-related changes.
When is a string DAC the wrong choice?
If the requirement is wideband waveform generation, RF modulation, or very high update rates, a current-steering or RF DAC architecture is typically a better fit. If narrowband ultra-low noise is the priority, a delta-sigma DAC may be more suitable.
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