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Use ideal-diode OR-ing with current sharing (master/slave or autonomous) to achieve low-drop dual-source paralleling with reverse blocking, thermal balance, path-health telemetry and failure bypass. Scope: board-level dual sources only; excludes BMS charge algorithms, DC/DC multi-phase, and UPS-class systems.
Brands limited to TI, ST, NXP, Renesas, onsemi, Microchip, Melexis. Procurement focus: write sharing target, ΔV priority window, reverse-block threshold, PG/FAULT cross-interlock, and telemetry requirement into BOM no-substitute clauses.
What Dual OR-ing & Current Sharing Solves
Schottky paralleling at mid/high currents suffers from high drop (Vf) and thermal mismatch that skews branch currents and shortens lifetime. Ideal-diode controllers use MOSFET Rds(on) for low drop and reverse blocking; adding a current-sharing loop controls skew, balances heat, and enables telemetry + bypass.
Schottky loss: P ≈ I × Vf
Heat scales linearly with current; hotspots drive imbalance.
Ideal-diode loss: P ≈ I² × Rds(on)
Lower drop improves efficiency and thermal spread for sharing.
Sharing error: ε = |I₁ − I₂| / (I₁ + I₂)
Target ≤ 3–5% based on thermal and lifetime limits.
Reverse block: Vrev_block ≥ |VA − VB|max
Include overlap/surge margin to avoid back-feed and stress.
Verification: 0→100% load sweep, log I1/I2, IR thermography, and priority handover waveforms.
Degradation test: inject contact resistance rise on one path; confirm health flag → bypass timing and no back-feed.
BOM remarks (copy & paste)
Ideal-diode OR-ing + current sharing target ≤ __%; ΔV priority window = __ mV; reverse blocking ≥ __ V; PG/FAULT cross-interlock; telemetry (I, ΔV, Temp, counters) required.
Architecture Options: Master/Slave vs Autonomous Sharing
Two sharing strategies: master/slave with a central ΔV/voltage reference, and autonomous distributed correction. Choose by current level, thermal density, layout symmetry, MCU involvement, and need for telemetry. Tune the ΔV priority window (typ. 30–80 mV) and enforce PG/FAULT cross-interlocks.
Master/Slave — Deterministic cutover; centralized monitoring. Sensitive to single-point faults; compensation must reflect layout asymmetry.
Autonomous — Better fault tolerance and N-way scaling; requires tighter bandwidth matching and offset control; light-load stability needs hysteresis/limit-band.
ΔV window — Narrow → fast but jitter-prone; Wide → stable but higher overlap loss. Start at 30–80 mV, then correlate with line loss and ripple.
Offsets — Sharing error ≈ Vos / (G·Rsense) + thermal/layout terms; use 4-terminal Rsense and Kelvin routing.
BOM remarks (copy & paste)
Architecture = Master/Slave (or Autonomous); ΔV priority window = __ mV; PG/FAULT cross-interlock; op-amp Vos ≤ __ µV; Rsense 4-terminal ≤1%; Kelvin sense required.
Current Sharing Loop (Sampling, Amplification, Stability)
Achieving ≤3–5% sharing error requires a disciplined chain: 4-terminal Rsense with Kelvin routing, an amplifier or dedicated sharing controller with matched bandwidth, and compensation that preserves 60–80° phase margin. At light loads, dead-zone behavior and micro-conduction around the MOSFET gate can cause jitter or beating; use hysteresis or limit-band tactics to stabilize.
- Sampling: 4-terminal Rsense, single-point star return; target full-load Vsense ≥ 25–50 mV to suppress Vos impact.
- Amplification: choose GBW to match loop bandwidth; design for 60–80° phase margin.
- Light-load stability: add hysteresis and minimum loop gain; use a modest RC zero if needed.
- Thermal–electrical coupling: asymmetrical copper and cooling shift Rds(on)(T), re-distributing current—verify with IR + I₁/I₂ overlay.
Sharing error (budget)
ε ≈ Vos / (G · Rsense) + f(T, Rds(on), layout)
MOSFET conduction loss
P_MOSFET ≈ I² · Rds(on)
Loop injection/Bode: record crossover frequency and phase margin (if the controller supports injection).
Light-load spectrum: <5% rated load; look for beating/jitter; sweep ΔV window and hysteresis.
Thermal–electrical: IR thermography + I₁/I₂ vs. time; repeat after thermal shock to check redistribution.
BOM remarks (copy & paste)
Rsense 4-terminal; tolerance ≤1%; Kelvin routing; op-amp Vos ≤ __ µV; loop phase margin ≥ 60°; ΔV window = __ mV; light-load hysteresis = __ mV.
Path-Health Monitoring & Failure Bypass
Define a measurable loop: observe (I_branch, ΔV, temperature, counters), decide (threshold + trend with debounce and voting), and act (derate → bypass → latch/retry). Bypass must complete within a bounded time and guarantee a “no back-feed” window; PG/FAULT lines should carry clear semantic codes to the MCU.
Telemetry: I_branch, ΔV_path, device/copper temperature, switch/bypass counters, timestamped event log; moving average + peak capture.
Decision: threshold + trend (1st/2nd derivative); debounce and multi-source voting to avoid false trips under ripple.
Action: derate → bypass → latch/retry; define semantic PG/FAULT and event codes for firmware.
BOM remarks (copy & paste)
Telemetry required: current, ΔV, temperature, fault counters; Bypass action ≤ __ ms; No back-feed during bypass (I_rev < __ mA, t < __ µs); PG/FAULT semantic mapping to MCU required.
Programmable contact resistance: step/ramp injection; log detection delay and bypass timing.
Thermal shock: −40/125 °C × 500 cycles; track ΔV trend and counter increments.
No back-feed proof: oscilloscope window with I_rev < __ mA, duration < __ µs during bypass.
| Signal | Semantic meaning | Example event codes |
|---|---|---|
| PG | Path usable, priority valid, temperature OK | 0x10 OK_IDLE, 0x11 OK_PRIMARY |
| FAULT | Over-temp / ΔV anomaly / reverse-current detected / bypass action | 0x21 OT, 0x22 DV_ANOM, 0x23 REV_CUR, 0x24 BYPASS |
Design Rules (Thresholds, ΔV Window, Interlocks)
Set actionable limits so engineering and procurement can commit values directly to the BOM: sharing target, ΔV priority window, reverse-blocking headroom, Rsense policy, PG/FAULT cross-interlocks, thermal symmetry, and EMC-friendly loop bandwidth.
Sharing target
5–10 A: ≤ 3% · ≥10 A: ≤ 5%
ΔV priority window
Start at 30–80 mV; widen for stability, narrow for agility.
Reverse blocking
Vrev_block ≥ |VA − VB|max + surge margin.
Rsense policy
Full-load Vsense ≥ 25–50 mV; ≤1% tol; ≤50 ppm/°C; 4-terminal + Kelvin.
PG/FAULT interlocks
Cross-interlock to avoid dual cutover; MCU must receive semantic states.
Thermal & EMC
Symmetric copper/vias/cooling; ΔT trigger for derate/bypass; keep loop BW off system noise peaks.
BOM no-substitute remarks (copy & paste)
Sharing target ≤ 3% (5–10 A) / ≤ 5% (≥10 A); ΔV window = __–__ mV; Reverse blocking ≥ __ V (incl. surge); Rsense 4-terminal, Kelvin, ≤1% tol, ≤50 ppm/°C; PG/FAULT cross-interlock; MCU semantic codes required; No back-feed window: I_rev < __ mA, t < __ µs; Thermal ΔT trigger = __ °C / __ s.
Validation Checklist (Bring-up to Mass-Release)
A stepwise script that works for small-batch builds and scales to production: sharing sweep, priority handover, reverse blocking, bypass latency and no-back-feed, thermal stability, and aging/repeatability. Each item includes recordables and pass/fail gates.
- Sharing sweep: 0–100% stepped + ramps; log I₁/I₂, ε; capture light-load jitter.
- Priority handover: dual-source overlap sweep; quantify switch-point jitter and brownout risk.
- Reverse blocking: inject ±ΔV; measure reverse leakage and cutoff time.
- Failure bypass: inject contact-R / over-temp / UVLO; measure bypass latency and prove no-back-feed.
- Thermal stability: −40/25/85/125 °C, airflow A/B; IR + current match overlay.
- Aging & repeatability: mating cycles, thermal shock, bend/vibration; re-check gates.
| Test | Record | Gate (Pass/Fail) |
|---|---|---|
| Sharing sweep | I₁/I₂ vs. load; ε curve; jitter notes | ε ≤ __% (tiered by current); jitter ≤ __ mV |
| Priority handover | Switch-point jitter; Vout dip | Jitter ≤ __ mV; ΔVout ≤ __ V / __ µs |
| Reverse blocking | Irev; cutoff time | Irev < __ mA; tcutoff ≤ __ µs |
| Failure bypass | Latency; no-back-feed oscilloscope proof | tbypass ≤ __ ms; Irev < __ mA, t < __ µs |
| Thermal stability | IR heatmap + I match overlay | ε within target; ΔT ≤ __ °C |
| Aging & repeatability | Post-stress re-check of all gates | No gate exceeded after N cycles/shocks |
Mass-release gates (copy & paste)
Sharing error ≤ __% ; Switch jitter ≤ __ mV ; Bypass latency ≤ __ ms ; No back-feed: I_rev < __ mA, t < __ µs ; Reverse leakage ≤ __ mA ; Thermal ΔT ≤ __ °C ; Brownout ΔVout ≤ __ V / __ µs.
Small-Batch Procurement & Cross-Brand Paths
Keep ideal-diode OR-ing + current sharing. Preserve telemetry (I, ΔV, temperature, fault counters) and PG/FAULT semantics. Update the ΔV priority window and thresholds when crossing brands. Do not replace with Schottky OR-ing.
A→A (Same brand / Pin-to-Pin)
- TI LM74700-Q1, LM5050-1/-Q1 — ideal-diode / OR-ing controllers.
- Renesas ISL6144 — HV OR-ing MOSFET controller.
- onsemi NCV68061 — ideal-diode NMOS controller.
- ST STEF12H60M / STEF01 — eFuse path (pair with OR-ing logic).
Action: reuse ΔV window + interlock; retune sense/Vhys; verify no back-feed.
A→B (Cross-brand / Same capability)
- TI LM74700-Q1 ⇄ Renesas ISL6144 ⇄ onsemi NCV68061.
- To ST eFuse (STEF12H60M/01): keep external OR-ing + ΔV mapping.
- NXP MC33XS2410 (smart high-side with diagnostics) + external ΔV/share.
Action: re-measure ΔV (30–80 mV start), cutoff time, reverse leakage; update PG/FAULT semantics.
A→C (Higher capability / Small PCB rev)
- onsemi NIS6350 — 5 V eFuse (USB/aux path protection).
- ST STEF12H60M — 60 A eFuse; pair with OR-ing controller.
- Microchip PD70224 / PD70288 (IdealBridge) or HV Auxiliary eFuse RD.
- Melexis MLX91220 — add path-health current telemetry (sensor).
Action: accept minor layout/thermal changes; remap ΔV + semantics; set bypass & no-back-feed thresholds.
Brand scope: TI / ST / NXP / Renesas / onsemi / Microchip / Melexis only. For Melexis, use current sensors (e.g., MLX91220) to preserve path-health telemetry when controllers are from other brands.
Sources for part numbers and capabilities: TI LM74700-Q1 datasheet & product page; TI LM5050-1 (-Q1) product/datasheet; Renesas ISL6144 product/datasheet; onsemi NCV68061 product/datasheet; onsemi NIS6350 datasheet; ST STEF12H60M product/datasheet; NXP MC33XS2410 product page; Microchip HV Auxiliary eFuse reference design & PD70224/PD70288 IdealBridge; Melexis MLX91220 datasheet.
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FAQ
This FAQ focuses strictly on dual-source ideal-diode OR-ing with current sharing at the board level: ΔV priority window, sharing loop behavior, PG/FAULT interlocks, path-health monitoring, bypass timing, and verification hooks. Values with “__” are intended to be finalized in your BOM and validation checklist.
What is the core difference between Master/Slave sharing and autonomous averaging?
Master/Slave uses a central reference and ΔV guidance, giving deterministic priority, simpler telemetry semantics, and easier PG/FAULT interlocks. Autonomous averaging distributes sensing and correction, improving fault tolerance but demanding tighter amplifier offset, bandwidth matching, and layout symmetry. Start with a 30–80 mV ΔV window, enable cross-interlocks, and validate switch-point jitter by overlapping the two source voltages across temperature.
For 5–10 A rails, how tight should the sharing target be (3% vs 5%)?
For 5–10 A rails, target ≤3% sharing error to keep junction temperatures balanced and extend lifetime. Above 10 A, ≤5% is often acceptable, provided copper, vias, and heatsinking remain symmetrical. Validate with 0–100% stepped and ramped load profiles, overlay IR thermography with I₁/I₂ curves, and confirm that light-load jitter does not grow when ambient or airflow changes.
How do I choose Rsense for accuracy, loss, and temperature drift simultaneously?
Set full-load Vsense to 25–50 mV so amplifier offset does not dominate. Use ≤1% tolerance and preferably ≤50 ppm/°C, four-terminal construction, and strict Kelvin routing. Too small Vsense raises sharing error. Characterize error versus amplifier offset and temperature. Record resistor self-heating and drift in the report, then lock these selections as no-substitute BOM fields.
How wide should the ΔV priority window be to avoid ping-pong switching?
Begin at 30–80 mV and tune against ripple and wiring losses. Narrow windows improve agility but increase chatter risk; wider windows reduce switching activity at the cost of extra dissipation. Add a small hysteresis or bandwidth limit. Verify with dual-source overlap sweeps and specify a maximum switch-point jitter of ≤__ mV in the validation matrix and firmware acceptance tests.
How can I detect early degradation from rising contact resistance?
Track trends, not just thresholds: monitor ΔV, current, device temperature, fault counters, and switching frequency over time. Define slope-based triggers that issue warnings, request derating, or schedule bypass before hard failures. Emulate degradation by injecting a small series resistance and record telemetry timing. Require these fields in the BOM so cross-brand alternatives keep identical visibility and semantics.
What is the safest failure-bypass method, and how do I avoid back-feed?
First disable the degraded path, confirm reverse current remains inside the no-back-feed window, then enable the healthy path. Specify and test: Irev < __ mA and duration < __ µs, plus bypass latency ≤ __ ms. Capture oscilloscope proof at cold, room, and hot. Keep PG/FAULT semantics consistent across brands so firmware actions remain deterministic during bypass.
Why is light load less stable, and how do I compensate it?
At light load, MOSFETs operate near the micro-conduction region and dead-zone, making loop gain sensitive and prone to beat-frequency jitter. Limit loop bandwidth, add small hysteresis or RC filtering, and ensure phase margin ≥ 60–80°. Validate with <5% rated load, measuring noise spectra and time-domain oscillations. Record thresholds that suppress chatter without hurting hand-over agility.
How do PG/FAULT interlocks prevent brownout during hand-over?
Use cross-interlocks so both paths cannot cut over simultaneously. Add vote-based debouncing around the ΔV switching zone. Firmware should treat PG/FAULT as semantic states, not raw pins. In validation, require Vout dip ≤ __ V for ≤ __ µs while overlapping sources. Keep the exact state meanings stable across brands and record mappings in the change log.
May I place Hot-Swap in front of each path? What are the trade-offs?
Yes, provided Hot-Swap SOA and current-limit ramp do not fight the OR-ing and sharing loops. The inrush profile must not distort ΔV priority. Constrain Hot-Swap bandwidth and slope below the sharing loop response, then confirm no unexpected hand-over. Validate with enable sequencing, surge and short pulses, and record any change to sharing error or reverse current.
How do I verify symmetry across temperature and after aging?
Test at −40/25/85/125 °C with airflow variants. After thermal shock and mating cycles, re-measure sharing error, ΔT, and reverse current. Pass if ε meets the target (≤3% for 5–10 A or ≤5% above), ΔT ≤ __ °C, and Irev remains within limits. Keep IR images and I₁/I₂ overlays as release evidence tied to serial numbers.
Can Schottky OR-ing be used temporarily in the lab, and under what limits?
Only for short, low-current prototyping where thermal headroom is ample and telemetry is not required. Schottky loss scales with I×Vf, creating thermal imbalance and no PG/FAULT semantics. Do not ship or qualify with it. Prefer an evaluation board based on an ideal-diode controller to preserve ΔV behavior, reverse blocking, and data needed for debugging.
Which BOM fields prevent purchasing from selecting non-telemetry parts?
Specify: “Telemetry required (I, ΔV, temperature, fault counters), PG/FAULT semantic mapping, ΔV priority window = __–__ mV, no-back-feed window (Irev < __ mA, t < __ µs), cross-interlocks, Rsense 4-terminal ≤1% with Kelvin.” Add: “Alternatives limited to TI/ST/NXP/Renesas/onsemi/Microchip/Melexis. Do not replace ideal-diode + sharing with Schottky OR-ing.”
