Definition & Scope

Port-level protection for Ethernet focuses on differential ESD/EFT at the pair and common-mode lightning surge that must return to chassis. Physical stack: RJ-45 → Magnetics (Transformer + CMC) → CT → Chassis → PHY. Residual voltage/energy defines the upper boundary for downstream eFuse/Hot-Swap/OR-ing.

Boundaries (Anti-overlap)

• No PHY registers/protocol flows here.
• No PoE classification/power budget math; we only state constraints so protection does not break signature/classification.
• No energy metering or long logs (those live in the Telemetry sibling page).

Threat Mapping

• Differential path: IEC 61000-4-2 ESD / 4-4 EFT couple at the pair → impacts eye/BER/link stability.
• Common-mode path: external lightning/GR-1089 couples to cable shield/pairs → returns to chassis through CT clamp and surge stages.
• PoE constraint: leakage in the ~57 V window must not spoof signature/classification.

Interface to eFuse/Hot-Swap/OR-ing

This page outputs residual limits (V_RESIDUAL, energy, duration) and a fault semantic (active-low FAULT / active-high PG). Downstream power path shall survive the residual and latch/report per the unified polarity.

Key Parameters

• Differential: C_diff (array effective), V_BR, TLP peak, R_dyn, package L/C.
• Common-mode: V_RESIDUAL, I_SURGE(8/20), L_loop (return inductance), leakage at ~57 V (PoE safe).
• Placement: array-to-RJ-45 distance ≤ X mm; array→chassis return loop ≤ L_target.

Validation Hooks

• Pass/fail wording for IEC 61000-4-2/4-4/4-5 and GR-1089 (link recovery time, residual peak, no PHY latch-up).
• Unified PG/FAULT polarity and debounce window for event logging.

Threat Model: ESD / EFT / Surge / GR-1089

Event Sources & Waveforms

• IEC 61000-4-2 ESD: ±8 kV contact / ±15 kV air (typical system levels); fast edge, low energy but high dv/dt.
• IEC 61000-4-4 EFT: burst trains with ns rise; stresses routing discontinuities and return paths.
• IEC 61000-4-5 Surge: 1.2/50-8/20; for Ethernet, common-mode to chassis is typical (e.g., 1 kV CM).
• GR-1089 external line lightning tests (telecom/operator grade) — higher energy CM events.

Differential vs Common-Mode Propagation

• Differential (near-end injection): treat with TLP/TDR equivalence; watch eye/BER, Sdd21, bias stability.
• Common-mode (far-end coupling): energy couples to cable; correct path is CT→chassis with minimal L_loop.

PoE-Specific Constraint

Protection must not break IEEE detection/classification. Control leakage near ~57 V and keep signature R_sig intact. CT clamp path must bypass the signature network.

Metrics & Logging

• Record LINK_RECOVERY_MS, frame error rate delta, PHY auto-recovery (no manual reset needed).
• Thermal hotspot map during surge to guide via fences and spring placement.

Differential Pair ESD Topologies

Deliver a minimal, repeatable recipe: select ultra-low-capacitance arrays, place them within X mm of the RJ-45 pads, and provide a low-inductance return to chassis. Reduce residual without degrading the eye; for substitutions, satisfy C_diff and V_BR before I_pp.

Selection

• C_diff target: ≤ 0.2–0.5 pF (speed-tiered; use the lower bound for 5G/10G).
• Secondary metrics: V_BR (breakdown/clamp), TLP peak (pulse capability), R_dyn (lower is better).
• Unidirectional vs bidirectional: default to bidirectional; only use unidirectional when DC bias and polarity are guaranteed safe.
• Package parasitics: prefer short-lead, symmetric arrays; account for L_pkg/C_pkg in bandwidth budgeting.

Placement & Return

• Distance: array to RJ-45 pad centerline ≤ X mm; array→chassis loop inductance ≤ L_target.
• Return path: nearby chassis vias/spring fingers; avoid digital-ground return to prevent ground bounce.
• Via strategy: 2–3 parallel vias from array to chassis; bridge any splits with springs/straps to reduce L_loop.

π vs T Topology

• T (default): better bandwidth/eye preservation; use when margin is tight.
• π: lowest residual but adds more effective C; use only when high-speed margin allows.
• Compare by eye/BER and TLP clamp-slope; do not decide by I_pp alone.

Failure Modes & Replacement Rules

• Clamp miss (V_BR drift), leakage rise (PoE signature impact), package open/detach.
• A→A / A→B: keep C_diff and V_BR first, then R_dyn, then I_pp. Re-validate eye + IEC 61000-4-2.

Key Parameters

C_diff, V_BR, TLP peak, R_dyn, L_pkg/C_pkg, layout thresholds (≤ X mm, loop ≤ L_target).

Validation Hooks

• IEC 61000-4-2 injection + eye/BER comparison; record LINK_RECOVERY_MS, BER_delta, residual.
• S-parameters: Sdd21 (bandwidth/insertion loss) and Sdc (bias integrity).

Common-Mode Lightning Suppression

Use a GDT/TSS → low-R_dyn TVS cascade to shed energy then limit residual, and a short CT→chassis clamp that bypasses PoE signature. Targets: low V_RESIDUAL, limited PCB energy, PoE-safe leakage.

Cascade & CT-Clamp

• GDT/TSS → TVS: front stage carries I_8/20, TVS sets residual and slope (low R_dyn).
• CT clamp: dedicated short path to chassis away from the IEEE signature/classification network; control leakage around 57 V.

Loop Inductance & CMC Order

• Minimize L_loop: straight return to chassis, via fences, springs/straps across slots.
• CMC helps CM→DM rejection, but surge energy must exit via GDT/TSS + TVS + CT-clamp first.

Targets & Metrics

• V_RESIDUAL below magnetics/PHY withstand with ≥30% margin.
• Design for I_8/20, P_pp, low R_dyn; verify leakage near PoE 57 V window.

Validation Hooks

• IEC 61000-4-5 / GR-1089: measure residual waveform/peak, thermal hotspots, link recovery time.
• Chassis connection impedance scan (near-field + inductance estimate); event telemetry flag with unified polarity.

Layout Rules & Return Paths

Turn “short • straight • wide • decoupled” into executable rules for Ethernet port protection. Give numeric thresholds and probe standards so the layout can be reviewed and reproduced.

Differential ESD Arrays

• Placement: array center to RJ-45 pin centerline ≤ X = 2–4 mm (1G ≤3 mm; 10G ≤2 mm).
• Symmetry: matched pads/vias; avoid stubs ≥ 0.5 mm; length-compensate paired vias.
• Return: array → chassis direct; do not use digital GND flood; keep path straight.
• Loop inductance target: L_target ≤ 1.5 nH (10G ≤ 1.0 nH).
• Via bundle: parallel chassis vias N ≥ 3 (Ø 0.30–0.35 mm; pitch 0.6–1.0 mm) adjacent to array.
• Copper width: return copper / neck width ≥ 0.8–1.2 mm.

Common-Mode Surge Path (GDT/TVS → Chassis)

• Cascade: GDT/TSS (energy) → low-R_dyn TVS (residual) → chassis.
• Via fence: along GDT/TVS-to-chassis copper with fence pitch ≤ 2–3 mm.
• Across splits: use chassis springs/straps. If a capacitor is required, single-point C_limit ≤ 100 pF (SRF ≥ 300 MHz), far from the pair.
• Residual target: internal node V_RESIDUAL ≤ 80–120 V with ≥30% margin to magnetics/PHY withstand.

CT-Clamp & PoE Constraints

• CT clamp route to chassis is isolated from IEEE detection/classification network.
• Leakage near the 57 V PoE window: I_leak ≤ 100 µA (prefer ≤ 50 µA).

CMC Position vs ESD/TVS

Prefer RJ-45 → Magnetics/CMC → ESD (diff) / CM suppression → CT → chassis. Let surge energy exit to chassis before crossing the CMC.

Probe & Measurement Points

• Provide SMA/probe pads near arrays and near PHY (both sides of the channel).
• Leave a 10–15 mm clamp region on the GDT/TVS-to-chassis copper for current probe.
• Place 0603 thermistor/TC pads next to TVS/GDT for ΔT logging.

Layout Checklist (copy to review)

• X (array→RJ-45) ≤ 3 mm (10G ≤ 2 mm)
• N (parallel chassis vias) ≥ 3; fence pitch ≤ 3 mm
• L_target ≤ 1.5 nH (10G ≤ 1.0 nH)
• Return copper width ≥ 0.8–1.2 mm; route straight
• C_limit (across split) ≤ 100 pF, SRF ≥ 300 MHz
• CT clamp isolated from PoE signature path; I_leak ≤ 100 µA@57 V
• Residual goal V_RESIDUAL ≤ 80–120 V
• SMA/probe pads + current-clamp window + ΔT pads present

Compliance & Validation Playbook

Reusable test steps for IEC 61000-4-2/-4/-5 and GR-1089 with PoE compatibility. Each block defines inputs, injection points, records, and pass/fail criteria plus unified log keys.

ESD — IEC 61000-4-2

• Levels: ±8 kV contact / ±15 kV air (option ±10/±20).
• Matrix: RJ-45 shell, grouped pins (to chassis), near-array pads; 10 shots/polarity/point.
• Record: LINK_RECOVERY_MS, BER/eye delta, FAULT polarity.
• Pass: no PHY latch; LINK_RECOVERY_MS ≤ 1 s; leakage stable.

EFT — IEC 61000-4-4

• Setup: coupling clamp 1.0 kV; 5 kHz/100 kHz, 60 s each; cable & enclosure paths.
• Record: FRAME_ERR_RATE; target P_err ≤ 10⁻⁶ (project-specific).
• Pass: no link drop; PoE not falsely interrupted; FAULT_POLARITY_OK = true.

Surge — IEC 61000-4-5 (Common-Mode to Chassis)

• Wave: 1.2/50-8/20; typical 1 kV CM (extendable to 2 kV); 5 shots/polarity.
• Return: coupled to cable, return via chassis using the Ch.5 low-L path.
• Record: V_RESIDUAL_VPK, HOTSPOT_DT_MAX at TVS/GDT, LINK_RECOVERY_MS.
• Pass: V_RESIDUAL ≤ 80–120 V; ΔT ≤ 60 °C (or within SOA); recovery ≤ 2 s.

GR-1089 (If Applicable)

• External line lightning CM levels per carrier spec; wiring between outside plant and chassis as specified.
• Pass includes no permanent FER increase plus Surge criteria above.

PoE Compatibility

• IEEE detection 2.7–10 V and classification 15.5–20.5 V succeed continuously ≥ 20 cycles.
• Leakage near 57 V within I_leak ≤ 100 µA; CT clamp path bypasses signature network.

Telemetry & PG/FAULT Semantics

Map port-level events to a unified PG/FAULT bus with consistent polarity, deglitch, timestamps, and cloud fields. Prevent semantic drift when parts are substituted across brands, and define how port events drive downstream eFuse/Hot-Swap/OR-ing behaviors.

Event Set & Severity

• Events: PORT_ESD_EVENT, PORT_EFT_EVENT, PORT_SURGE_EVENT, PORT_LINK_DOWN, PORT_LINK_RECOVERY.
• Severity tiers: INFO (transient), WARN (limited protection engaged), SEVERE (needs lock/inspection).

Polarity Unification

• FAULT = active-low, PG = active-high.
• If a device uses opposite polarity: (1) board-level inverter or MCU/FPGA logic flip; (2) update polarity_map in cloud; (3) verify once in NVM self-test.

Timestamps & Deglitching

• Deglitch t_dg: 2–5 ms (ESD/EFT), 5–20 ms (Surge/Link).
• Minimum event width t_{min_event}: 1–2 ms. Report window report_window_ms: 1000 ms aggregation.
• Log keys: ts_ms, port_id, event, severity, pg, fault, optional v_residual_vpk, link_recovery_ms.

Interface to eFuse / Hot-Swap / OR-ing

• PORT_SURGE_EVENT(severe) → limit current / switch to preferred source / brief disconnect (holdoff_ms=200–500).
• PORT_LINK_DOWN(persist > t_hold) → reduce port power, or switch power source.
• EVENT_BURST_RATE > R_max → raise protection tier; assert PG=0, FAULT=1 and log.

Key Parameters (defaults)

• Input thresholds (3V3): V_il ≤ 0.8 V, V_ih ≥ 2.0 V; pull-ups 10–47 kΩ.
• Deglitch: 2–5 ms (ESD/EFT), 5–20 ms (Surge/Link). Report window 1000 ms.
• Error rate gate: FER_thresh ≤ 1e-6. Auto-rearm: 1000–3000 ms (≤ 5 s max).

{
  "port_id": "ETH0",
  "event": "PORT_SURGE_EVENT",
  "severity": "WARN",
  "ts_ms": 1730712345678,
  "v_residual_vpk": 96.4,
  "link_recovery_ms": 420,
  "pg": 1, "fault": 0,
  "polarity_map": {"pg":"active_high","fault":"active_low"},
  "deglitch_ms": 8, "burst_rate": 3
}
      

BOM Remarks & Procurement Hooks

Lock guardrails into the BOM so small-batch substitutions won’t break Ethernet port protection. Four windows to control: C_diff, V_RESIDUAL, L_loop, and PoE leakage. Define A→A / A→B / A→C paths and the telemetry semantics that must remain stable.

Copy-Paste BOM Notes (fill placeholders)

Default Windows (recommended)

• C_diff ≤ 0.2–0.5 pF (1G ≤ 0.3 pF; 10G ≤ 0.2 pF).
• V_RESIDUAL ≤ 80–120 V (internal nodes).
• L_loop ≤ 1.5 nH (10G ≤ 1.0 nH).
• I_leak@57 V ≤ 100 μA (prefer ≤ 50 μA).
• X_mm ≤ 3 mm (10G ≤ 2 mm) from RJ-45 to array center.

Receiving / Replacement Checklist

• Datasheet revision locked; package and pad pitch compatible.
• C_diff ≤ X, V_BR ≥ Y; TVS R_dyn and P_pp adequate.
• Leakage @57 V ≤ I_{leak_max}; CT clamp not tied to signature net.
• Via-fence geometry (pitch/diameter/distance to device) implemented.
• PG/FAULT polarity and t_dg match template; cloud mapping verified.
• Bring-up proves V_residual_vpk, LINK_RECOVERY_MS, and ΔT within limits.

Substitution Paths

• A→A (same brand/series): pin-compatible; first lock C_diff / V_BR, then verify TVS/GDT I_pp/P_pp; keep X_mm target.
• A→B (cross-brand): match C_diff / leakage / V_RESIDUAL window; re-run IEC 61000-4-5 CM; update polarity_map if needed.
• A→C (de-feature, only when no PoE): allow slightly larger C_diff or omit CT-Clamp; mark “limited scope” and attach a re-test job.

Brand Mapping (TI / ST / NXP / Renesas / onsemi / Microchip / Melexis)

Capability-level mapping for Ethernet port protection. Focus on differential ultra-low-C ESD/TVS families and PHY-side constraints. Common-mode surge parts are usually third-party (use numeric windows). Melexis: no direct Ethernet port protection/PHY line.

Differential ESD/TVS Families — Representative Part Numbers

• TI (TPD family): TPD1E05U06, TPD2E2U06, TPD4E05U06, TPD1E10B06.
• ST (ESDA/ESDALC/ECMF): ESDALC6V1-1, ESDALC6V1-2, ESDALC6V1-5M2, ECMF02-2AMX6 (verify bandwidth).
• NXP (Nexperia) (PESD/TrEOS): PESD5V0S1UL, PESD5V0R1BSF, PESD5V0R2B, PESD2ETH1.
• onsemi (ESD/low-C): ESD8002, ESD7002, ESD9B5.0ST5G, ESD11B5.0ST5G.
• Renesas: typically pair with third-party ultra-low-C arrays; follow windows below.
• Microchip: focus on PHY/Sw; use above low-C arrays with windows below.
• Melexis: — (no direct Ethernet port ESD/TVS line).

PHY-Side Constraints — Families & Examples

• Microchip KSZ* (e.g., KSZ9031RNX – RGMII GbE; KSZ9131MNX – GbE; KSZ8081MNX – 10/100): keep added C per line ≤ 0.2–0.3 pF (GbE); arrays ≤ 2–3 mm from RJ-45; direct low-L chassis return.
• TI DP83* (DP83867IR – GbE; DP83822I – 10/100; DP83848I – 10/100): symmetric placement; ensure PoE leakage window when applicable.
• NXP TJA110x (100BASE-T1, automotive single pair, not RJ-45): different magnetics/CT topology; follow auto-Ethernet rules (this page maps capabilities only).
• Renesas RZ/N (e.g., RZ/N2L, RZ/N1D) with external PHY: apply chosen PHY’s low-C/placement constraints.
• onsemi / ST: when using their PHY/SerDes, apply the same low-C and low-L rules.
• Melexis: — (no direct Ethernet PHY line).

A→A/A→B: lock C_diff and V_BR first, then compare R_dyn/I_pp. Maintain ≤ 2–3 mm to RJ-45 and a low-inductance chassis return.

Worked Examples

Two copy-ready port-level baselines: 1G non-PoE and 1G PoE-PD. Include numeric windows and validation cues. Use Ch.9 families/PNs for A→A/A→B selection.

Example A — 1G non-PoE (RJ-45)

• Diff-ESD: C_diff ≤ 0.3 pF; π-network or single array (e.g., TI TPD2E2U06; NXP PESD2ETH1; onsemi ESD8002; ST ESDALC6V1-2).
• CM surge: GDT/TSS + low-R_dyn TVS to chassis; V_RESIDUAL ≤ 600 V (node example; finalize per product spec).
• Layout: ≤ 2–3 mm from RJ-45; via-fence to chassis; use chassis tabs across splits.
• Validation: IEC 61000-4-2 (±8 kV contact), -4-4 (burst P_err), -4-5 (CM surge, residual & ΔT), link auto-recovery ≤ T_rec.

Example B — 1G PoE-PD (RJ-45)

• Signature/classification: CT-clamp must not interfere with the PoE signature path; leakage @57 V ≤ 100 μA (prefer ≤ 50 μA).
• Diff-ESD: tighter C_diff (≤ 0.25–0.3 pF) with symmetric placement; same low-L chassis return.
• CM surge: same cascade; ensure PD front-end SOA/energy limiting.
• Validation (extra): PoE signature/classification/power-up robustness; GR-1089 external line (if applicable).

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FAQ