Wire the stack

Minimal, robust wiring for PWM_U/V/W, /EN, /FLT across isolation, plus current/voltage sensing and Hall/encoder inputs.

Align timing

PWM update strategy + sampling trigger alignment + phase-to-phase skew budgeting with pass/fail placeholders.

Validate & sign off

Bring-up flow, fault-injection plan, and acceptance criteria templates for bench → dyno → production.

Stay non-overlapping

Each specialized mechanism is referenced as a link target rather than duplicated here.

What it is

Three half-bridges (U, V, W). Each arm has one high-side and one low-side switch driven by a matched HS/LS driver pair.

DC-link capacitor placement defines the dominant high di/dt loop and directly influences common-mode noise.

Why it matters

Arm-to-arm timing mismatch or asymmetric power routing causes phase heating and torque ripple even with correct control code.

Bridge loop inductance increases Vgs overshoot and false turn-on risk, especially under fast dv/dt transitions.

Quick check

Verify U/V/W gate waveforms are symmetric: overshoot and ringing are within X% across arms.

At no-load, confirm phase current balance: ΔIphase ≤ Y% across U/V/W.

Pass criteria

Phase-to-phase timing skew ≤ N ns.

Gate overshoot ≤ X V and ringing settles within Y ns.

Selection intent

3-shunt maximizes observability and simplifies sampling alignment, supporting higher current-loop bandwidth and tighter torque control.

1-shunt can be viable when cost/space dominate and the control method provides stable reconstruction within available sampling windows.

Sampling window reality

Sampling opportunities depend on PWM mode and conduction intervals; insufficient window margin translates into noisy current estimates and control instability.

Margin must be validated across operating points: low speed, high torque, regen, and temperature shifts.

Quick check

Measure sampling window margin: window ≥ X ns/µs at all key vectors and operating points.

Compare reconstructed vs reference current (if available): error ≤ Y% over Z seconds.

Pass criteria

Sampling window margin ≥ X.

Current estimate noise at Tsample ≤ N mV (front-end), or equivalent current ripple ≤ M A.

Fault domain partition

Define whether a fault is local (one axis can isolate) or global (bus safety requires all axes to disable).

Regen events can elevate Vbus; bus-level protection must be coordinated with axis-level shutdown.

Reset ordering

Reset must be deterministic: drive disable → bus safe check → axis isolate → controlled re-arm.

Non-deterministic retry patterns create repeated dv/dt stress and intermittent faults.

Quick check

Validate /EN sequencing per axis: no axis re-enables before Vbus is below X and fault source is cleared.

Log fault-to-disable latency across axes: max skew ≤ Y µs.

Pass criteria

No fault flapping: retries limited to N attempts per T seconds.

Vbus returns below X within Y ms before any axis re-arms.

System takeaway

Center-aligned PWM usually offers more predictable sampling placement away from edges, improving current-loop stability.

Edge-aligned PWM can be valid, but requires stricter trigger alignment to keep Tsample away from switching transitions.

Quick check → Fix

Quick check: Tsample margin from nearest switching edge ≥ X (ns/µs).

Fix: adjust PWM mode or phase-align ADC triggers to a low-noise window (avoid edge proximity).

Pass criteria

Sampling noise at Tsample ≤ Y (mV or A-equivalent).

Window margin maintained across speed/torque/regen/temp corners.

Non-overlap note

Deadtime generation details and interlock circuits are handled by the dedicated deadtime page.

Symptom chain

Skew ↑ → phase current asymmetry → FOC dq decoupling degrades → torque ripple and audible noise increase.

Jitter ↑ → Tsample/edge relative drift → current estimate variance ↑ → stable bandwidth ceiling drops.

Quick check

Measure U/V/W gate edges under identical PWM: phase-to-phase skew ≤ N ns.

At fixed operating point: phase RMS current imbalance ≤ Y%; arm temperature spread ≤ ΔT.

Fix

Select a driver/isolator chain with tighter inter-channel matching (verify using the timing page’s metric definitions).

Enforce arm-to-arm symmetry in routing and return paths (layout details belong to the design-hooks page).

Pass criteria

Skew ≤ N ns; jitter ≤ M ns (placeholder targets).

No-load + loaded torque ripple within acceptance X (system-defined).

Datasheet focus

Delay: tPLH/tPHL (or equivalents), min/typ/max, temperature drift.

Skew: inter-channel matching, phase-to-phase consistency.

Jitter: edge uncertainty that moves Tsample relative to switching events.

Acceptance placeholders

Phase-to-phase skew ≤ N ns

Edge jitter ≤ M ns

Tsample window margin ≥ X (ns/µs)

Disable latency ≤ Y µs

What can be tuned

Ipk (peak source/sink), Rg_on / Rg_off, and optional +VG / −VG rails.

Two-level edges can separate “fast cross” and “gentle settle” behavior when justified.

What must be validated

Measured tr/tf, dv/dt, ringing settle time, and EMI pre-scan margin under representative load and bus voltage.

Thermal distribution across arms must remain symmetric within acceptance limits.

Quick sizing

First-order sizing: Ipk ≈ Qg,eff / tr (and similarly for tf).

Use device gate-charge data to estimate Qg,eff for the intended gate-voltage swing.

Quick check → Fix

Quick check: measured tr/tf meet target window X/Y.

Fix: tune Rg_on/Rg_off (or select higher Ipk class) while verifying overshoot and EMI constraints.

Pass criteria

tr/tf within target band: [X..Y].

Vgs overshoot ≤ X V; ringing settles within Y ns.

dv/dt ≤ Z (system-defined) and EMI margin ≥ N dB (placeholder).

Motor/servo consequence

Edges too fast can increase CM noise and contaminate Tsample; edges too slow increase switching loss and reduce torque-per-thermal headroom.

When −VG is justified

High dv/dt environments where false turn-on risk must be reduced, especially with long motor cables and strong common-mode transients.

Use of a clamp strategy and verified Vgs headroom is implied by the acceptance plan.

Risks to manage

Additional rails increase complexity; improper sizing can raise Vgs stress and increase overshoot during fast turn-off.

UVLO thresholds must align to avoid partial conduction and thermal runaway scenarios.

Quick check

During turn-off, Vgs stays below the false turn-on boundary with margin ≥ X.

Rail UVLO behavior is deterministic: on/off thresholds meet system targets X/Y.

Pass criteria

No false turn-on events under representative dv/dt and load step tests.

Gate-rail startup/shutdown does not produce gate glitches beyond N ns (placeholder).

When it helps

Fast cross + gentle settle: cross critical gate regions quickly, then slow down to reduce ringing and EMI.

Useful when EMI limits are tight but control bandwidth must remain high.

Validation focus

Second-stage shaping reduces overshoot/ringing to within X while maintaining required switching efficiency.

EMI pre-scan shows improvement ≥ Y (placeholder) without worsening torque ripple or arm heating.

Quick check

Measure Vgs/Vds and phase-node ringing: peak and settle time meet X/Y placeholders.

Check Tsample noise before/after shaping: improvement is consistent across operating corners.

Pass criteria

Overshoot ≤ X V; ringing settle ≤ Y ns.

Control stability unchanged: no new oscillations; torque ripple within acceptance N.

Hardware shutdown (ns–µs)

Events that can violate SOA must trigger immediate gate deactivation before any software response.

Examples: severe OC/SC, UVLO-induced partial drive risk, critical driver fault assertions.

Software derating (ms–s)

Thermal and overload conditions can be managed by limiting torque/current to prevent repeated hard trips.

Goal: keep operation stable without oscillating between run/fault states.

Acceptance placeholders

fault detect → gate inactive ≤ X µs

/FLT assert → MCU observes ≤ Y µs

derating response time ≤ Z ms

Non-overlap note

Comparator thresholds, blanking filters, and soft turn-off implementations belong to the linked mechanism pages.

Action semantics

hard off immediate gate disable for high-risk events.

soft turn-off controlled decay to reduce overshoot and stress.

two-step off fast clamp then gentle settle when required.

/FLT meaning

/FLT must have a deterministic default state during reset and power sequencing.

The MCU must distinguish a real fault from a signal integrity failure (stuck-high/low, open wire).

Clear & re-arm rules

Re-arm is allowed only after explicit clearance conditions are met (cooldown, Vbus check, retries).

Retry storms are prevented using attempt limits and backoff intervals.

Pass criteria

No contradictory window where PWM commands continue while the gate is expected inactive beyond N.

Fault classification is stable: no oscillation between fault types within T seconds.

Electrical expectations

Open-drain outputs require a defined pull-up location and value; the default reset state must avoid false assertions.

Harness noise and ground shifts must not create spurious edges at the MCU input.

Diagnostics

Detect stuck-low/stuck-high behavior; treat as signal-fault distinct from power-stage faults.

Define a boot-time validation window to confirm /FLT integrity before enabling the bridge.

Quick check

Verify /FLT idle level and edge polarity across isolation match the MCU expectation under noise injection tests.

Confirm pull-up strength supports the required edge speed without excessive susceptibility.

Pass criteria

/FLT propagation ≤ Y µs; boot-time false triggers = 0 within T_boot.

Wire fault detection completes within T_det (placeholder).

Latch (lockout)

Use for high-energy risk events to prevent repeated stress cycles and thermal runaway.

Requires explicit clearance conditions before re-arm.

Auto-retry (controlled)

Use only for recoverable events with strict retry limits, cooldown gating, and stability windows.

Backoff prevents reset storms and repeated dv/dt stress.

Quick check

Induce a representative fault and verify state transitions: FAULT → COOLDOWN → RETRY are deterministic.

Confirm retry counter and cooldown thresholds block repeated rapid re-enables.

Pass criteria

Retries ≤ N per T; re-arm only when Temp < X and Vbus < Y.

Post-recovery stability ≥ T_stable with no re-trigger of the same fault class.

Mechanical angle

Encoder/Hall capture provides position and speed timing reference (T_capture).

Capture jitter directly maps into angle estimate variance.

Electrical angle (FOC)

Estimator output drives commutation and current-loop transforms.

Phase drift degrades dq decoupling and increases torque ripple.

PWM carrier phase

PWM update timing (T_update) sets when switching events occur relative to capture and sampling.

Inconsistent update boundaries cause occasional control discontinuities.

ADC sampling window

T_sample must remain inside a low-noise window with margin ≥ X.

Sampling too close to edges injects noise into current estimates.

Chain definition

ENC/HALL capture → angle estimator → PWM update → ADC sample trigger.

Time-base alignment between capture and PWM timers must be deterministic or calibrated.

What to enforce

Timer coherence: capture and PWM share a stable reference or bounded drift.

Update coherence: angle updates occur at controlled boundaries (no mid-window jumps).

Sample coherence: T_sample stays away from switching edges by ≥ X.

Jitter & drift

T_capture jitter ≤ X; T_sample jitter ≤ Y.

Electrical phase drift ≤ N over T (placeholders).

Dropouts & detection

Pulse loss detection time ≤ T_det; loss rate ≤ K (placeholders).

Signal integrity failures are classified separately from power faults.

Speed steps

During accel/decel steps, no false OC/UVLO trips and no control discontinuity beyond X.

Settling time ≤ T_settle under defined step magnitude (placeholder).

Sampling window margin

T_sample margin from nearest switching edge ≥ X (ns/µs).

Current estimate noise reduction is consistent across operating corners.

Degrade policy

Encoder/Hall invalid → enter an angle-invalid mode; limit torque/current and prevent aggressive commutation.

Re-arm and recovery follow the retry/cooldown contract to avoid storms.

Acceptance placeholders

Sync loss detection ≤ T_det; degrade action ≤ T_act.

No reset storm: retries ≤ N per T and stability ≥ T_stable.

When bootstrap becomes fragile

low-speed long ONhigh dutyregen

High-side refresh opportunities shrink; HS bias headroom can collapse and trigger UVLO or partial drive.

Common-mode transients couple into the bootstrap loop through the switch node reference.

When isolated bias is preferred

wide operating envelopestable HS railmulti-bridge

High-side rail remains stable across duty cycle, low-speed holding torque, and regenerative conditions.

Noise injection can be constrained with secondary-side decoupling and controlled return paths.

When reinforced isolation is required

high dv/dtsafety boundaryfault containment

Use reinforced isolation where safety separation and fault propagation limits are system-level requirements.

Validation focuses on CMTI robustness and deterministic fault behavior under switching stress.

Acceptance placeholders

HS bias minimum ≥ X V under worst duty/low-speed/regen corner.

HS UVLO events ≤ N per hour (placeholder).

Gate drive does not show “soft collapse” beyond Y V for > T.

Shared bias (risk profile)

One fault or load transient can perturb multiple bridges, creating coupled instabilities and wider fault impact.

Noise and return current coupling can corrupt sampling windows in adjacent axes.

Per-axis / per-bridge bias (containment)

Fault and noise are contained; phase consistency improves under dv/dt stress and cable-induced common-mode events.

Recovery is localized, reducing system-level reset storms.

Quick check

Force a fault on one bridge and measure HS rail droop and control/sense disturbance on other axes.

Verify bias rail recovery time and cross-axis coupling magnitude.

Pass criteria

Other axes HS rail droop ≤ ΔV for ≤ T.

Cross-axis sampling interference ≤ X (mV or A-equivalent placeholder).

Primary injection paths

bias → switch nodebias → sense reference

Bias ripple and spikes can shift the HS reference and contaminate current sampling around T_sample.

Return current paths are the most common coupling route in stacked motor driver assemblies.

Fastest check

Compare Tsample-window noise with bias switching enabled vs disabled.

Check whether current estimate variance tracks bias rail ripple at the same frequency components.

Fix actions

Enforce secondary decoupling close to the driver supply pins and keep the loop local.

Separate bias returns from sense/ADC reference returns; avoid cross-partition current paths.

Pass criteria

Tsample-window noise ≤ X (mV or A-equivalent).

Enabling bias switching does not degrade control stability beyond Y (placeholder).

Design gate (pre-power)

enable semanticsfault defaultrail order

Goal: eliminate catastrophic integration errors before energy is applied.

Pass: /FLT reset state stable ≥ Treset; /EN glitch < X; rails settle ≤ Y.

Bring-up gate (LV → HV static → low-speed)

Vgs limitsdeadtimeHS bias

Goal: verify timing, bias headroom, and sensing integrity with controlled risk.

Pass: overshoot ≤ X; neg-Vgs ≥ -Y; skew ≤ N ns; HS min ≥ X.

Production gate (dyno + fault + EMC + production test)

load stepfault injectrepeatability

Goal: prove repeatability and safe fault behavior under dynamic stress.

Pass: gate inactive ≤ X µs; retries ≤ N/T; pre-scan margin ≥ Y dB.

Rollback rule

Any stage failure returns to the last stage that can be evaluated safely and deterministically.

Example: HS UVLO at HV static → return to LV bench to isolate bias and reference issues.

Pass: rollback reproduces the symptom within N attempts (placeholder).

Three inputs to route the selection

Bus VSwitch techIsolation?

These define bias architecture, dv/dt stress envelope, and protection response requirements.

Outputs

Candidate class and validation hooks mapped to Design/Bring-up/Production gates.

Key placeholders: Ipk from Qg/tr, UVLO on/off, skew/jitter, SC response time, /FLT semantics.

1) DC-link / Bus voltage

Question: Bus V within <X or >Y?

Branch: higher Bus V increases dv/dt stress and typically pushes toward stronger isolation and bias stability.

Validate: HV static gate → HS bias min ≥ X V, /FLT latency ≤ Y µs.

2) Switch technology

Question: IGBT / SiC / GaN / LV MOSFET?

Branch: SiC/GaN prioritize CMTI and fast protection; IGBT prioritizes DESAT and soft turn-off behavior.

Validate: fault inject gate → gate inactive ≤ X µs (placeholder).

3) Isolation class

Question: basic vs reinforced isolation required?

Branch: reinforced isolation is chosen when safety boundary and fault containment dominate the system constraints.

Validate: HV static + EMC pre-scan → no spurious /FLT under dv/dt stress (≤ N events).

4) Peak drive current from Qg and target edge

Question: required Ipk from Ipk ≈ Qg / tr?

Branch: select a driver class whose source/sink peaks meet ≥ X A with margin ≥ M.

Validate: LV bench gate → Vgs OS ≤ X, settle ≤ T, EMI headroom maintained.

5) UVLO ON/OFF thresholds

Question: independent ON/OFF thresholds available and aligned to gate-voltage requirements?

Branch: thresholds must prevent half-conduction losses and avoid unstable re-enable behavior.

Validate: HV static + fault inject → UVLO behavior deterministic; retries ≤ N/T.

6) Delay / skew / jitter budget

Question: required inter-channel matching ≤ X ns?

Branch: servo consistency depends on tight matching to reduce phase current distortion and torque ripple.

Validate: LV bench + low-speed spin → skew ≤ X ns, torque ripple signature reduced (placeholder).

7) Protection response time

Question: SC detection + shutoff must occur within X to fit device energy limits?

Branch: faster response is required as switching tech and bus energy increase.

Validate: fault inject → gate inactive ≤ X µs; /FLT latency ≤ Y µs.

8) Inputs + fault semantics

Question: single-ended vs differential inputs, and /FLT /RDY /EN semantics defined?

Branch: noisy motor environments benefit from robust input signaling and deterministic fault/reset behavior.

Validate: Design gate + HV static → reset defaults stable, /FLT noise immunity verified (≤ N false events).

Map decisions to gates

Enable/fault semantics → Design gate

Ipk, skew, Vgs limits → LV bench

Isolation, HS bias headroom → HV static

Timing + sampling stability → Low-speed spin

Protection speed, retry policy → Fault injection

EMI robustness → EMC pre-scan

Candidate class outputs (examples)

isolated 3-phase driverreinforced class

bootstrap HS/LSbasic class

integrated iso biashigh CMTI

fast protection classtight skew