Bootstrap Capacitor Sizing (Cboot) for Gate Drivers
Core idea: Bootstrap sizing is a charge-budget problem: ensure the refresh window can replenish all required charge (Qg + driver currents + leakage) so VBS never droops below UVLO(off) with margin.
If refresh is missing (near-100% duty) or dv/dt/recovery/layout injects spikes, bootstrap becomes structurally unsafe and the design must branch to a charge-pump or isolated-bias solution.
What Bootstrap Sizing Solves (Definition & Scope)
Bootstrap sizing ensures the high-side driver remains powered by a charge reservoir that is refreshed when the switch node is low. The objective is to prevent VBS droop into UVLO and to avoid dv/dt-induced VB/VS disturbance that can trigger misbehavior.
Two acceptance targets (engineering view)
Target A: VBS(min) > UVLO(off) + margin
Target B: VB/VS remains stable under worst dv/dt
- UVLO droop type: high-side turns off after some on-time; worsens at high temperature, low frequency, or high duty.
- dv/dt disturbance type: faults appear only during fast edges; waveform “looks fine” until probe/grounding changes reveal spikes.
Scope Guard (non-overlap rule)
This page covers: Cboot sizing, ΔV budget, charge path design, diode recovery & dv/dt disturbance, layout rules, and validation criteria.
This page does NOT cover: deadtime control, half-bridge control strategy, DESAT/short-circuit protection design, or device physics deep-dives.
If needed, go to: High-Side Gate Driver • Half-Bridge/Full-Bridge Driver • Protection & Control • By Switch Technology.
Charge-Flow Model (Where Charge Comes From and Where It Goes)
Bootstrap capacitor sizing is a charge balance problem. The capacitor is refreshed only when the switch node is low, then it must supply all required charge while the high-side is on. The sizing method follows conservation of charge over the refresh interval.
One PWM cycle: two windows
- Charge window (refresh): VS is low → diode conducts → Cboot is replenished.
- Discharge window (high-side on-time): VS is high → Cboot supplies the driver + gate charge.
Ton = D / f
Long Ton increases charge demand
Insufficient refresh causes droop
Charge budget (Qtotal)
- Qg,total: total gate charge required for the high-side device under the chosen switching condition.
- Qdrv: driver consumption during Ton (commonly modeled as Iqbs · Ton plus internal dynamic draw).
- Qleak: leakage paths (driver, capacitor, PCB contamination) that increase with temperature and humidity.
- Qdyn: dv/dt-coupled charge disturbance and parasitic injection that appear during fast edges.
Cboot ≥ Qtotal / ΔVallowΔV = Qtotal / Cboot
Model boundary (important)
If the refresh window cannot replenish the consumed charge (high duty, long on-time, or near 100% duty), VBS will drift downward over time until UVLO triggers. This is a bootstrap limitation, not a tuning issue.
Identify the Loads (Defining Qg,total and Loss Terms)
Accurate bootstrap sizing depends on mapping datasheet parameters into a charge budget without missing hidden consumers. Every current-related term must be converted to charge over the on-time window, and every capacitance-related term must be converted to charge over the gate-voltage swing.
Standardize budget fields
Convert I → Q with Ton
Convert C → Q with ΔV
Pick worst-case conditions
Practical rules for Qg,total
- Use the actual gate swing: pick Qg at the intended VGS level (not a default 10 V curve if the design uses 12–18 V).
- Include the Miller region: ensure Qgd is covered; it is often the most condition-sensitive part of the switching charge.
- Account for added gate networks: any external gate capacitance contributes Q = C · ΔV and belongs inside Qg,total.
- Align to the switching condition: datasheet Qg is tied to test VDS/ID/Rg; capture the condition and pick a conservative worst-case entry.
Driver consumption and leakage mapping
- Driver supply current terms: Iqbs / IHB / level-shift draw can vary with temperature, frequency, and duty. Convert to charge using Qdrv ≈ IHB(worst) · Ton or per-cycle curves when available.
- Leakage terms: driver leakage, MOSFET gate leakage, bootstrap capacitor leakage, and PCB contamination leakage increase with temperature and humidity. Convert to charge using Qleak ≈ Ileak(total,worst) · Ton.
- Dynamic disturbance: dv/dt injection and parasitic coupling appear as an extra charge disturbance term (kept as Qdyn in the budget).
Field checklist (datasheet → budget table)
| Budget item | Datasheet source | Typical pick | Worst-case pick | Temp trend | Notes / pitfalls |
|---|---|---|---|---|---|
| Qg,total | Qg, Qgd curves vs VGS; test condition notes | Read Qg at nominal VGS, nominal VDS/ID | Read Qg/Qgd at max VGS swing + worst switching condition; add external C·ΔV | Depends | Do not ignore Qgd; record the curve condition (VDS/ID/Rg) |
| Qdrv | IHB / Iqbs vs f, duty, T; “HB supply current” curves | Use nominal f/duty/T point from curves | Use max current point over T range and operating envelope; convert with Ton | ↑ | Use UVLO-relevant supply (HB/HS supply), not logic supply current |
| Qleak | Leakage specs (driver, cap); MOSFET gate leak; PCB leakage risk | Room-temp leakage or typical spec | High-temp leakage + humidity factor; convert with Ton | ↑ | Field failures often come from leakage + capacitor derating, not Qg alone |
| Qdyn | dv/dt immunity notes; HB supply glitches; app notes if provided | Small allowance for clean layout | Larger allowance when dv/dt is high or layout loop inductance is large | Depends | Treat as a disturbance reserve; validate with VBS waveform under worst dv/dt |
ΔV Budget & UVLO (How Much VBS Droop Is Allowed)
ΔV is not an arbitrary number. The allowable droop is defined by the UVLO threshold chain and the minimum expected VBS peak after charging. The hard constraint is to keep VBS above the high-side UVLO turn-off threshold with margin under worst conditions.
Hard rule: VBS(min) > UVLO(off) + margin
ΔVallow = VBS(peak) − VBS(min,required)
VBS(peak) is not simply VDD
Define the floor and the peak (stack-up method)
- Required floor: VBS(min,required) = UVLO(off) + margin (use the turn-off threshold).
- Minimum expected peak: VBS(peak,min) is reduced by diode forward drop, charge-path resistance, and the actual switch-node low condition during refresh.
- Available droop: ΔVallow = VBS(peak,min) − VBS(min,required).
VBS(min,required) = UVLO(off) + marginΔVallow = VBS(peak,min) − VBS(min,required)
ΔV budget table (fill once, reuse everywhere)
| Item | Symbol | How to obtain | Pick for typical | Pick for worst-case | Why it matters |
|---|---|---|---|---|---|
| Bias supply (min) | VDD(min) | System supply tolerance | Nominal | Minimum supply at worst line/load | Sets the absolute ceiling of VBS peak |
| Bootstrap diode drop | Vf(worst) | Diode datasheet at expected current and temperature | Vf at nominal T | Worst forward drop at the operating point | Directly subtracts from VBS(peak) |
| Charge-path drop | ΔVpath | Rpath × Icharge (incl. resistor, trace, ESR) | Nominal estimate | Worst case with limited refresh window | Can prevent full charge and lower VBS(peak) |
| Minimum expected VBS peak | VBS(peak,min) | Stack-up: VDD − Vf − ΔVpath − node-condition penalty | Nominal stack-up | Minimum credible peak under worst conditions | Defines the top of the available droop window |
| UVLO turn-off threshold | UVLO(off) | Driver datasheet (HB/HS supply UVLO) | Typical threshold | Maximum UVLO(off) tolerance | Defines the required floor (use OFF threshold) |
| Margin | Vmargin | Engineering reserve for noise, drift, measurement | Small reserve | Conservative reserve for dv/dt environment | Prevents borderline UVLO chatter and false trips |
| Available droop | ΔVallow | ΔVallow = VBS(peak,min) − (UVLO(off)+Vmargin) | Compute | Compute | Feeds directly into Cboot ≥ Qtotal / ΔVallow |
Core Sizing Formula (Executable Steps)
Bootstrap capacitor sizing is defined by the allowable droop window and the total charge consumed between refresh events. The calculation must standardize all terms into charge units and apply capacitor derating before choosing a standard value.
Cboot ≥ Qtotal / ΔVallow
Ton = D / f
I-terms grow with Ton
Derating is mandatory
Cboot ≥ Qtotal / ΔVallowQtotal = Qg,total + Qdrv + Qleak + QdynQdrv ≈ IHB(worst) · TonQleak ≈ Ileak(total,worst) · TonTon = D / f
Critical operating insight
- Low frequency or high duty: Ton increases, so IHB·Ton and Ileak·Ton can dominate the budget.
- Near 100% duty: refresh can be insufficient, so VBS may drift downward even when Cboot is large.
- Larger Cboot is not always better: it increases charge pulse stress and must be validated against the charging path (next section).
Derating and safety factors (convert to required nominal C)
Nominal capacitance must account for DC bias derating, temperature variation, and aging. A conservative engineering method is:
Cnominal_required ≥ Cboot_min / (k_bias · k_temp · k_aging)
- k_bias: effective capacitance reduction at operating voltage (use capacitor derating curve).
- k_temp: capacitance shift over the full temperature range.
- k_aging: long-term capacitance loss reserve (technology dependent).
Calculation template (inputs → outputs)
| Input field | Symbol | How to obtain | Worst-case guidance | Output link |
|---|---|---|---|---|
| High-side gate charge | Qg,total | Device datasheet Qg/Qgd at intended VGS and switching condition | Use worst switching condition and add external C·ΔV if present | Qtotal |
| Driver HB current | IHB(worst) | Driver datasheet (HB supply current vs f/D/T) | Pick max over temperature and operating envelope | Qdrv = IHB·Ton |
| Total leakage current | Ileak(total,worst) | Driver + capacitor + MOSFET + PCB leakage estimate | High temperature + humidity reserve | Qleak = Ileak·Ton |
| Dynamic disturbance reserve | Qdyn | Engineering reserve for dv/dt injection and coupling | Increase for high dv/dt or large loop inductance | Qtotal |
| Switching frequency | f | Control setting | Use minimum frequency corner if variable | Ton = D/f |
| Duty cycle | D | Control range / operating mode | Use maximum duty corner for bootstrap stress | Ton = D/f |
| Allowable droop | ΔVallow | From UVLO stack-up (previous section) | Use minimum expected VBS peak and maximum UVLO(off) | Cboot_min |
| Derating factors | k_bias, k_temp, k_aging | Capacitor datasheet + reliability reserve | Use worst reduction across operating voltage and temperature | Cnominal_required |
| Final selection | E12/E24 | Choose nearest standard value above Cnominal_required | Round up; validate charging stress in next section | Cboot_selected |
Charging Path Design (Diode, Resistance, and Charge Time)
A correct Cboot value is not sufficient if the charging path cannot replenish charge within the minimum refresh window. Charging design verifies that the diode, series resistance, and loop parasitics can deliver the required charge without excessive stress or recovery-related spikes.
Verify the shortest refresh window
Qin (window) ≥ Qout (cycle)
Dboot: Vf vs Qrr trade-off
Rseries limits Icharge and VBS peak
Charging window rule
- Charging occurs only when VS is low and the bootstrap diode is forward-biased.
- Worst-case refresh: use the minimum credible low interval (shortest VS-low window) for the charging check.
- Pass condition: the window must replenish the cycle demand so that VBS reaches the minimum expected peak used in the ΔV budget.
Component trade-offs (within the bootstrap loop)
- Dboot: lower Vf improves VBS(peak), but recovery behavior (Qrr) can create spikes and extra loss under high dv/dt.
- Series resistance: reduces inrush and can improve edge behavior, but it also slows charging and increases path drop (reducing VBS peak).
- Larger Cboot: reduces droop but increases charging pulse current; diode stress and heating must be checked.
Charging check table (fill and verify)
| Check item | Symbol | How to estimate / measure | Worst-case pick | Pass criteria (example) |
|---|---|---|---|---|
| Minimum refresh window | tcharge_min | From control envelope / waveform observation of VS-low interval | Shortest credible VS-low time | Use this window for all charging checks |
| Charge needed per cycle | Qneed | Use Qtotal (or dominant terms) from sizing budget | Worst-case Qtotal | Qin(window) ≥ Qneed |
| Peak charging current | If_peak | Estimate from path impedance and VDD−Vf; confirm with current probe if available | Highest peak (cold/hot as applicable) | Below diode and resistor pulse limits |
| Diode forward drop | Vf@T | Diode datasheet at If and temperature | Worst Vf at operating point | VBS(peak,min) meets ΔV budget stack-up |
| Diode recovery risk | Qrr risk | Diode datasheet + dv/dt environment review | High dv/dt corner | No excessive spike; no overstress indication |
| Power dissipation | Pd | Pd ≈ Vf·Iavg + resistive loss; validate with temperature rise | Worst duty/frequency/ambient | Temperature rise within limit |
| Path drop (includes series R) | ΔVpath | Rpath·Icharge during the pulse | Worst impedance + worst pulse | Does not collapse VBS peak |
dv/dt, Recovery & False Turn-On (Failure Chain)
In high dv/dt switching, charge injection and diode recovery can disturb the bootstrap loop. VB/VS spikes and VBS ripple may trigger UVLO or logic mis-detection inside the high-side driver, leading to intermittent dropout or false turn-on even when average waveforms look normal.
dv/dt injection → VB/VS disturbance
Dboot Qrr → spike + loss
Cboot ESL → resonance
Symptom → suspect → measure point
Three dominant coupling paths (within the bootstrap loop)
- Capacitive injection: SW-node dv/dt couples through parasitic capacitance (e.g., Cgd/Ccb) and shifts VB/VS reference.
- Diode recovery: reverse-recovery current overlaps switching transients and produces additional VB/VS spikes and heating.
- Resonance: Cboot ESL/ESR and loop inductance create ringing that modulates VBS at fast edges.
Primary measurement points
- VBS = VB − VS: verify that the minimum does not cross UVLO(off) + margin during switching transients.
- VB (to COM/GND): reveal absolute spike injection into the bootstrap node.
- VS (to COM/GND): reveal switching-node disturbance as seen by the driver reference.
Fault tree (symptom → first suspect → measure point)
Symptom: High-side occasionally drops out while PWM input remains correct
First suspect: VBS dips below UVLO(off) due to dv/dt injection or recovery spikes
Measure point: VBS waveform during switching edges (VB − VS)
Pass criteria: VBS(min) ≥ UVLO(off) + margin (X/Y/N)
Symptom: False turn-on or brief HS pulse when it should be off
First suspect: VB/VS disturbance shifts internal thresholds; coupled charge alters gate control state
Measure point: VB and VS spikes aligned with dv/dt edges
Pass criteria: No spurious HS gate activity under worst dv/dt (X/Y/N)
Symptom: Works at room temperature, fails hot
First suspect: Diode recovery and leakage increase; margin to UVLO shrinks
Measure point: VBS(min) and diode behavior at hot condition
Pass criteria: VBS(min) stays above required floor at hot corner (X/Y/N)
Symptom: Failure appears only at higher bus voltage or faster edges
First suspect: dv/dt coupling dominates; Cboot/loop resonance becomes visible
Measure point: VB/VS spike amplitude vs edge rate
Pass criteria: Spike and ripple remain within driver tolerance (X/Y/N)
Layout Rules for the Bootstrap Loop (Geometric Constraints)
Bootstrap sizing assumes an ideal loop. In practice, loop inductance and return-path mistakes break the assumptions and amplify dv/dt and recovery disturbances. The layout objective is a minimal-area, local-return bootstrap loop that keeps VB/VS nodes short and well-referenced.
Shortest loop area
Cboot at VB/VS pins
No split crossing
Low via count
Absolute rules (bootstrap-only scope)
- Cboot must be placed at the VB/VS pins with the shortest possible connections and a local return.
- The Dboot charging loop must not cross a split or a gap in the reference plane.
- VB/VS traces must be short and kept away from long parallel runs next to the SW node copper.
Layout checklist (fill with project thresholds)
-
PlacementCboot-to-VB pin distance: ≤ X mmCboot-to-VS pin distance: ≤ X mmDboot placement: within X mm of driver pin
-
Return PathLoop return: same-layer local return (Y/N)No split crossing under loop: (Y/N)Bootstrap loop area minimized: (Y/N)
-
Geometry DisciplineVB trace length: ≤ X mmVS sense trace length: ≤ X mmVias in VB/VS loop: ≤ N
-
Coupling Control (bootstrap-only)VB kept away from long SW-parallel copper: (Y/N)No long flying leads on VB/VS nets: (Y/N)Local VDD decoupling near driver: (Y/N)
Corner Cases (High Duty, Low Frequency, Start-Up, Regeneration)
Bootstrap operation assumes periodic refresh. Some operating corners break that assumption and can cause dropout even when the sizing math is correct. This section provides a decision gate to determine whether bootstrap is suitable and when a refresh strategy or an alternative supply is required.
No refresh → guaranteed droop
Long Ton → I-terms dominate
Start-up can chatter UVLO
VS abnormal breaks assumptions
Structural limitation
- High duty / 100% on: if the VS-low refresh window does not exist, the bootstrap diode does not recharge Cboot. VBS only discharges toward UVLO.
- Low frequency / long Ton: supply current and leakage terms (IHB·Ton, Ileak·Ton) grow and can dominate the budget.
- Start-up sequencing: the first charge event and ramp rate can cause UVLO threshold chatter if VBS crosses the threshold repeatedly.
- Regeneration / reverse current: abnormal VS behavior can change diode bias conditions and disturb the VB/VS reference relationship.
Bootstrap suitability gate (fill with project numbers)
| Check | Input / derived | How to obtain | Result | Action |
|---|---|---|---|---|
| Max duty | Dmax | Control envelope / worst operating mode | OK / Risk / No | If refresh absent at Dmax, jump to alternative supply page |
| Min frequency | fmin | Operating corner / spread-spectrum / mode changes | OK / Risk / No | Use fmin to compute Ton_max and I-terms |
| Max on-time | Ton_max = Dmax / fmin | Derived from D and f | OK / Risk / No | If Ton_max large, re-check IHB·Ton and Ileak·Ton dominance |
| Refresh exists? | Refresh (Y/N) | Waveform observation of VS-low events | OK / No | No refresh means VBS droop is unavoidable |
| Min refresh window | trefresh_min | Worst VS-low window (shortest credible interval) | OK / Risk | If too short, charging path may not replenish Qneed |
| Margin to UVLO(off) | VBS(min) − UVLO(off) | From measurement (Validation section) | OK / Risk / No | Require ≥ X V margin (X/Y/N) |
| VS abnormal cases | Regen / reverse | System corner (braking, reverse current, unusual commutation) | OK / Risk | If present, validate VB/VS stability under that event set |
| Final gate | Suitability | Combine above checks | OK / Risk / Not suitable | OK: proceed; Risk: tighten margin; Not suitable: jump to alternative supply |
Validation & Measurement (Pass/Fail Acceptance)
Validation converts “theory is sufficient” into repeatable acceptance. The primary metric is VBS = VB − VS, evaluated at worst-case operating corners: temperature, load, maximum dv/dt, minimum refresh window, and worst supply conditions.
Measure VBS (VB − VS)
Track VBS(min), ripple, spikes
Worst-case corners only
Repeatability Y times
Required measurements
- VBS(min): minimum value across the switching window (must stay above UVLO(off) + margin).
- Ripple and spikes: edge-correlated disturbances that can trigger UVLO/logic mis-detection.
- Repeatability: repeated runs under worst corners must not produce dropout or spurious behavior.
Acceptance criteria (placeholders)
- UVLO margin: VBS(min) ≥ UVLO(off) + X V (X/Y/N)
- Absolute maximum: VB/VS/VBS spikes do not exceed absolute maximum ratings (X/Y/N)
- No dropout: repeat Y cycles / Y trials without HS dropout (X/Y/N)
- No spurious: no false turn-on or unexpected fault behavior under worst dv/dt (X/Y/N)
Acceptance matrix (fill and run)
| Condition set | What to set | What to measure | Pass criteria | Result |
|---|---|---|---|---|
| Temperature corners | Tcold / Thot (X) | VBS(min), ripple, spike | VBS(min) ≥ UVLO(off) + X V | Pass / Fail |
| Load corners | Light / nominal / heavy | Spike magnitude vs load | No abs-max exceed; no dropout | Pass / Fail |
| Maximum dv/dt corner | Highest bus V + fastest edges | Edge-correlated VB/VS spikes | No spurious; margin retained | Pass / Fail |
| Minimum refresh window | Shortest trefresh_min | VBS(min) during worst refresh | Qin adequate; VBS(min) meets margin | Pass / Fail |
| Worst supply condition | VDD low / ripple high | VBS peak and minimum | Still above UVLO(off) + margin | Pass / Fail |
| Repeatability | Y trials or Y cycles | Dropout count, spurious count | 0 events across Y runs | Pass / Fail |
H2-11 · Engineering Checklist (Design → Bring-up → Production)
This chapter converts the negative turn-off strategy into three audit-friendly gates. Each item is written as a recordable checkpoint so review, bring-up, and production acceptance use the same criteria.
Goal Repeatable pass/fail evidence
Scope −VGOFF + Miller-risk closure
Output X/Y/N placeholders
Design gate before PCB release
- Gate-voltage budget is complete: VGS_peak, VGS_min, margin ≥ X V (worst corner).
- Negative stress stays inside limits: VGS_min ≥ AbsNeg + N V (include ringing allowance).
- Negative rail capability is quantified: VNEG droop ≤ X V during max sink events.
- UVLO + sequencing policy is explicit: rail-ready conditions + default OFF-safe state.
- Division of labor is fixed: −V hold / Miller clamp / two-level turn-off roles do not overlap.
- Layout constraints are stated: Kelvin reference, minimal loop, return-path rules (no cross-split).
Example BOM (negative rail) — verify latest datasheets:
TPS63710(TI) — inverting converter for a small −V rail.LTC3260(Analog Devices) — charge-pump based dual-polarity supply.R05P05D(RECOM) — isolated DC/DC module with ± outputs.
Bring-up gate lab proof
- Waveform evidence pack: VGS, VDS, current proxy + probe setup recorded.
- Worst dv/dt condition is exercised: max VBUS / strongest drive / worst layout corner.
- No false turn-on signature: shoot-through evidence = 0 (define metric Y).
- Negative spike is bounded: VGS_min ≥ AbsNeg + N V (measured at Kelvin reference).
- Temperature corners are covered: cold/hot margins tracked (Δ margin ≥ X V).
- Sequence fault injection: late/early −V, brownout, disable path → OFF-safe state (Y/N).
Example BOM (driver candidates) — shortlist by specs:
UCC21750/UCC21732(TI)ADuM4135(Analog Devices)1ED3122MC12H/1EDI20I12MF(Infineon)ACPL-337J(Broadcom)
Production gate repeatability
- Sampling plan is defined: VNEG, VGS_peak, VGS_min, and key timing items (N samples/lot).
- Fault injection is standardized: /DIS open/short, UVLO trigger, −V drop → OFF-safe (Y/N).
- Measurement fixture is frozen: bandwidth, ground method, Kelvin point definition.
- Documentation acceptance text: the same thresholds appear in EMC/safety/FA docs (X/Y/N).
- Regression triggers are listed: device lot change / layout change / rail change → minimum re-test set.
Example BOM (consistency aids):
- Gate resistor footprints for split tuning + optional bead footprint.
- Dedicated Kelvin-sense test pads at the driver reference point.
- Rail monitor points for +V and −V (probe repeatability).
Figure (Gate checklist board) — quick scan of the three gates and the evidence required.
Diagram intent: a “single-page audit board” that aligns review, bring-up, and production acceptance.
H2-12 · Applications & IC Selection (Placed at the End, Before FAQ)
This chapter stays strictly within negative VGOFF + Miller-risk closure: application playbooks define when −V is worth the complexity, and selection lists only the fields that matter for this topic.
A) 3-Phase inverter / half-bridge (SiC/GaN)
- Risk shape: dv/dt-driven gate lift + tight VTH margin.
- Preferred combo: Miller clamp handles injected current; −V provides off-margin hold; two-level turn-off manages EMI if needed.
- Acceptance focus: VGS_peak < (VTH_min − X), VGS_min ≥ AbsNeg + N, no shoot-through evidence (Y).
Example part numbers (drivers):
UCC21750,UCC21732(TI)1ED3122MC12H,1EDI20I12MF(Infineon)
B) Totem-pole PFC / LLC
- Risk shape: EMI constraints force edge-shaping; margin can be consumed by slow transitions + coupling.
- Decision rule: clamp first for injected-current control; add −V when corner margin is still insufficient.
- Acceptance focus: EMI target (X) met while VGS_peak and VGS_min margins remain stable across temperature.
Example part numbers (drivers):
ADuM4135(Analog Devices)ACPL-337J(Broadcom)
C) Paralleled switches (VTH spread)
- Risk shape: the “weakest” device (lowest VTH corner) defines false turn-on vulnerability.
- Preferred combo: −V provides uniform off-margin across devices; clamp prevents dv/dt injection from becoming VGS lift.
- Acceptance focus: corner-based margin uses worst-VTH device; production sampling includes VGS metrics (N/lot).
Example part numbers (drivers):
UCC21750(TI)1EDI20I12MF(Infineon)
Key specs & shortlisting fields for −VGOFF topic-specific
1) Negative drive capability
- Why: defines off-margin hold and how much droop occurs during strong sink events.
- Check: supported VEE range, peak sink current, output impedance (X/Y/N).
Example part numbers:
UCC21732(TI)1ED3122MC12H(Infineon)
2) Active Miller clamp availability
- Why: provides a low-impedance path for injected Miller current when dv/dt is highest.
- Check: clamp mode entry condition + clamp strength class (X/Y/N).
Example part numbers:
ADuM4135(Analog Devices)1EDI20I12MF(Infineon)
3) UVLO & rail-valid / default OFF-safe behavior
- Why: negative-rail systems fail most often during ramp-up/down and brownout.
- Check: enable/disable defaults, UVLO thresholds + hysteresis, fault-to-off state (X/Y/N).
Example part numbers:
UCC21750(TI)1ED3122MC12H(Infineon)
4) Delay / skew (bridge safety)
- Why: not the root cause of Miller false turn-on, but still critical for shoot-through margin.
- Check: propagation delay stability and channel-to-channel matching (X/Y/N).
Example part numbers:
UCC21732(TI)ACPL-337J(Broadcom)
Negative rail generation — example BOM options (pick by noise/impedance/startup needs):
TPS63710(TI) — inverting converter for −V rails.LTC3260(Analog Devices) — charge-pump based dual-polarity rails.R05P05D(RECOM) — isolated DC/DC module with ± outputs.
Note: Part numbers are examples for shortlisting; final selection must follow the latest datasheet limits and safety requirements.
Figure (Application × knobs matrix) — which knob is typically needed, and why (one-line).
Matrix intent: prevent “−V is always the answer” misuse; choose knobs by risk shape and measurable margins.
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H2-13 · FAQs (Bootstrap Sizing)
Fixed 4-line answers only: Likely cause / Quick check / Fix / Pass criteria (placeholders X/Y/N).
High-side drops out at high duty even with a large Cboot—why?
Likely cause: Refresh window is missing (D→1), so Cboot only discharges toward UVLO(off).
Quick check: Confirm VS-low events and measure trefresh_min; monitor VBS(min) trend over long Ton.
Fix: Enforce periodic refresh or use a driver with charge pump / isolated bias (jump to the relevant page).
Pass criteria: VBS(min) ≥ UVLO(off) + X V for the longest Ton (X/Y/N).
VBS looks fine at room temperature but fails hot—what changed?
Likely cause: IHB/Iqbs and leakage increase with temperature; diode Vf/Qrr and MLCC derating shift VBS peak and droop.
Quick check: Re-run VBS(min) under hot corner at minimum refresh and lowest VDD; compare droop slope vs room.
Fix: Increase margin (ΔV), reduce I-terms impact (shorten Ton / ensure refresh), improve charge path, and apply realistic capacitor derating.
Pass criteria: At Thot, VBS(min) stays ≥ UVLO(off) + X V with N repeats (X/Y/N).
Bootstrap math passes, but VBS droops at low frequency—first suspect what?
Likely cause: Long Ton makes IHB·Ton and Ileak·Ton dominate even if Qg is modest.
Quick check: Compute Ton_max = Dmax/fmin and compare IHB·Ton_max vs Qg,total magnitude.
Fix: Re-budget Qtotal with worst I-terms, increase ΔV margin, or move to a non-bootstrap bias method for long-Ton modes.
Pass criteria: At fmin and Ton_max, VBS(min) margin ≥ X V with spike limits met (X/Y/N).
Start-up shows UVLO chatter—why does VBS oscillate?
Likely cause: First-charge is insufficient or too slow, causing repeated crossings of UVLO(on/off) during ramp and early switching.
Quick check: Capture VBS during first PWM cycles; look for threshold crossings synchronized with VS-low windows.
Fix: Ensure adequate initial recharge window, reduce charge impedance (diode/resistor), and avoid early high-duty commands until VBS is stable.
Pass criteria: No UVLO toggling; VBS crosses UVLO(on) once and remains above UVLO(off)+X V (X/Y/N).
Works on bench, fails under high dv/dt—what coupling path is most likely?
Likely cause: dv/dt coupling via parasitics (Cgd/Ccb, Cboot ESL, Dboot Qrr current) injects spikes into VB/VS and disturbs logic/UVLO sensing.
Quick check: Correlate VB/VS spikes with switching edges; verify probe method and measure VBS spike amplitude vs abs max.
Fix: Reduce loop inductance (place Cboot at VB/VS), use lower-Qrr diode, tune series R, and tighten bootstrap return geometry.
Pass criteria: Under max dv/dt, VBS spikes remain below abs max with VBS(min) margin ≥ X V (X/Y/N).
Adding series R improved EMI but caused HS dropout—what knob is wrong?
Likely cause: Series R reduced recharge current and lowered VBS(peak), so ΔV budget is consumed earlier during Ton.
Quick check: Measure VBS peak after each refresh; compare with and without series R at the shortest trefresh_min.
Fix: Reduce R, increase Cboot (with derating), or choose a faster diode; verify recharge within trefresh_min.
Pass criteria: VBS(peak) − VBS(min) ≤ usable ΔV and VBS(min) ≥ UVLO(off)+X V (X/Y/N).
Dboot runs hot—what should be checked first?
Likely cause: High recharge peaks, large Qrr loss, or excessive refresh frequency causes diode conduction and recovery dissipation.
Quick check: Estimate If_peak and measure diode temperature rise at max switching activity and worst VDD.
Fix: Select lower-loss diode (optimized recovery), adjust series R for peak limiting, and ensure short current loop to reduce ringing.
Pass criteria: Diode temperature rise ≤ X °C at worst corner and VBS margin maintained (X/Y/N).
Big VB/VS spikes are visible but no immediate failure—what is the acceptance limit?
Likely cause: Spikes may be below abs max but still reduce noise margin to UVLO/logic sensing under corner conditions.
Quick check: Compare spike peak to abs max and evaluate VBS(min) margin during the same edges (not separate runs).
Fix: Tighten layout loop, reduce Qrr injection, and validate with worst dv/dt + temperature + minimum refresh in one matrix row.
Pass criteria: Spike peak ≤ abs max − X V and VBS(min) ≥ UVLO(off)+X V across N repeats (X/Y/N).
Random false turn-on events—bootstrap related or gate loop related?
Likely cause: VB/VS disturbances can perturb driver state; gate loop parasitics can also amplify dv/dt-induced Miller current.
Quick check: Align events with switching edges; check if VBS spikes coincide with false pulses and compare phases/channels for symmetry.
Fix: Improve bootstrap loop geometry (Cboot placement) and gate loop damping (Rg split / clamp strategy where applicable), then re-validate.
Pass criteria: Zero spurious events over N stress cycles at max dv/dt and worst refresh corner (X/Y/N).
Two labs disagree on pass/fail—what should be normalized in VBS measurement?
Likely cause: Different probing method and reference points distort VB/VS spikes and VBS(min) readings.
Quick check: Standardize to VBS = VB − VS with identical probe bandwidth/grounding and identical worst-case condition set.
Fix: Publish one acceptance matrix row definition (Temp/Load/dv/dt/trefresh/VDD) and one measurement method statement.
Pass criteria: Same method yields VBS(min) within ±X V between labs and meets UVLO margin (X/Y/N).
Dropout frequency increases after weeks in the field—what degradation is typical?
Likely cause: Leakage increases due to contamination/humidity, capacitor aging/derating drift, or diode parameter shifts with thermal cycling.
Quick check: Compare VBS droop slope and VBS(min) margin between new and returned units under the same matrix conditions.
Fix: Tighten leakage controls (cleanliness/coating), increase margin, and enforce traceability for Cboot/Dboot lots and assembly conditions.
Pass criteria: After stress/aging, VBS(min) margin ≥ X V and event count = 0 in Y trials (X/Y/N).
Only one phase in a 3-phase bridge fails—what is the first bootstrap symmetry check?
Likely cause: Asymmetric layout or component tolerances create phase-specific charge path loss or spike injection.
Quick check: Compare per-phase VBS(peak), VBS(min), and spike peaks under identical PWM conditions and load.
Fix: Match Cboot/Dboot/Rseries values and tighten per-phase geometry (Cboot at VB/VS, identical return paths).
Pass criteria: Inter-phase VBS(min) mismatch ≤ X V and all phases meet UVLO margin with N repeats (X/Y/N).
Data fields used consistently: VBS(min), VBS(peak), trefresh_min, Ton_max, UVLO(off), margin (X V), spikes (abs max − X V), repeats (N/Y).
