CMTI & dV/dt Immunity for Gate Driver ICs
H2-1. Definition & Scope: What “CMTI / dV/dt Immunity” Means (in Gate Drivers)
CMTI is the gate-driver’s ability to stay logically correct during high dV/dt common-mode steps—no false switching, no false faults, no unintended reset.
What CMTI means in a gate-driver context
Condition A high dV/dt common-mode step (typically from the switching node) couples into the driver across parasitic paths.
Required behavior Inputs, outputs, and fault logic remain stable—no unintended state change.
“dV/dt immunity” is used here as the practical, system-level expression of the same requirement: immunity against dV/dt-driven displacement-current injection.
Observed “victims” under common-mode stress
- Input-side upset: false triggering due to threshold crossings or comparator disturbance.
- Output-side upset: false turn-on / false turn-off, or pulse narrowing/extension.
- Fault-path upset: /FLT chatter, false /RDY drop, unintended disable.
- Bias/logic upset: UVLO glitch, reset/lockup symptoms, state-machine corruption.
The “object list” above defines what counts as CMTI failure for this page.
In-scope vs out-of-scope (to avoid topic overlap)
In scope: dV/dt injection paths, common-mode return closure, logic/threshold robustness, bench validation and pass/fail criteria.
Out of scope: full-system EMI radiated/ conducted troubleshooting, chassis grounding philosophy, and detailed EFT/ESD standard procedures.
EFT/ESD are only referenced for terminology separation; test-level details belong to dedicated compliance pages.
Pass/Fail criteria (placeholders for project-specific thresholds)
Common-mode stress: dV/dt ≥ X kV/µs, step amplitude ≥ Y V (fixture-defined).
No false switching: false turn-on/off events ≤ N per 10M switching edges.
No false fault: /FLT glitches ≥ tmin (Y ns) = 0 events (or ≤ N allowed).
No bias/logic upset: UVLO/reset/lockup events = 0 across the stress run.
This template is the reference for all later chapters (mechanisms, layout levers, and validation).
H2-2. Why It Matters: Failure Signatures & Risk Map (SiC/GaN Hard-Switch)
CMTI failures are rarely “mysterious”: symptoms cluster into a few observable signatures that map to four root-cause families.
Four root-cause families that cover most CMTI failures
1) Input upset: thresholds/comparators cross due to common-mode reference shift or injected current.
2) Output stage upset: output structure momentarily flips or loses state during fast transients.
3) Bias collapse: isolated bias droops or glitches, tripping UVLO or internal state behavior.
4) Return-path coupling: unintended return closure through chassis/heatsink/cables injects noise into control references.
This chapter focuses on symptom recognition and fast discrimination. Mechanisms and fixes are expanded later (e.g., Coupling Mechanisms in H2-3, Isolation/Ciso in H2-7, Validation in H2-10).
False turn-on / cross-conduction
Observable: unexpected shoot-through current spikes, abnormal DC-link dip, device heating, current overshoot at switching edges.
Fast discriminator: reduce edge speed (increase turn-off shaping or add a temporary Rg-off). If the symptom collapses with lower dV/dt, common-mode injection is likely dominant.
Likely families: return-path coupling, gate-loop reference shift, input upset (threshold crossing).
Go next: Coupling paths (H2-3) → Layout/return rules (H2-8) → Gate-network levers (H2-9).
Missing pulses / pulse narrowing
Observable: PWM edges disappear, output pulse width shrinks, irregular duty behavior, control loop becomes unstable only at high bus voltage or high switching speed.
Fast discriminator: monitor UVLO and bias rails during switching. If UVLO toggles or bias droops coincide with the event, bias collapse is a primary suspect.
Likely families: bias collapse, output stage upset, return-path coupling into logic reference.
Go next: Real dV/dt waveform effects (H2-5) → Isolation/bias behavior (H2-7) → Validation method (H2-10).
False fault: /FLT chatter, /RDY drop, unintended disable
Observable: fault pin glitches during switching edges, sporadic disable events, “fault storms” that vanish at low bus voltage or slow edges.
Fast discriminator: hold the input static (IN fixed high/low) and reproduce with only dV/dt stress. If faults still appear, the fault-path pickup is dV/dt-driven rather than control-driven.
Likely families: input upset, return-path coupling, internal fault logic sensitivity to reference shift.
Go next: Input/logic immunity levers (H2-6) → Layout/return rules (H2-8) → Measurement pitfalls (H2-10).
Random reset / lock-up behavior
Observable: sporadic reset-like behavior, latched outputs, irregular state machine behavior, issues sensitive to probe wiring or cable routing.
Fast discriminator: change measurement reference points and cable routing; if behavior changes dramatically, return-path coupling and probe-induced injection are likely involved.
Likely families: return-path coupling, bias collapse, logic upset under common-mode injection.
Go next: Return-path focus (H2-8) → Bench validation discipline (H2-10).
Severity is not negotiable in hard-switch SiC/GaN
- Red (hard fail): any cross-conduction / false turn-on that increases short-circuit energy or violates SOA limits.
- Amber (must be fixed): /FLT chatter or pulse distortion that can trigger unintended shutdown or control instability.
- Green (pass): no false switching, no false fault, no bias/logic upset under the defined dV/dt stress template (X/Y/N).
Risk grading must be reported alongside the stress definition; “passed once” without a defined dV/dt and event-count rule is not an acceptance.
H2-3. First-Principles: Where the Common-Mode Current Actually Flows
CMTI is a current-path problem: high dV/dt creates displacement current, and the return closure determines which nodes experience threshold violations.
Source → Coupling → Return closure → Victim
Source The switching node produces fast common-mode steps (dV/dt events).
Coupling Parasitic capacitances inject displacement current into sensitive domains.
Return The current must close a loop—where it returns defines reference shift and noise exposure.
Victim Input thresholds, fault comparators, UVLO logic, and the gate-reference node can be disturbed.
The same dV/dt can yield different outcomes if the return closure changes (layout, cables, heatsink/chassis coupling).
Why dV/dt turns into injected current
Displacement-current magnitude is set by: i = C · dV/dt
Higher C increases injected current under the same edge. Higher dV/dt increases injected current under the same coupling.
A “high CMTI number” cannot compensate for a system that forces injected current through the wrong return path.
Ciso: barrier capacitance injects into the control domain
- What it represents: effective capacitance of the isolation barrier and package geometry.
- Injection target: control-domain ground/reference and logic thresholds.
- Typical victims: input comparator upset, fault logic chatter, UVLO/reset glitches.
Key idea: Ciso does not “create errors” by itself; errors occur when injected current forces reference shift across sensitive thresholds.
Cgd/Cgs: Miller-driven gate disturbance
- What it represents: dv/dt at the power switch couples through Miller (Cgd) into the gate node.
- Return closure: the disturbance is referenced to source/emitter; non-Kelvin returns amplify the effect.
- Typical victims: false turn-on risk, pulse distortion, loss of margin during fast transients.
Detailed gate-shaping levers (Miller clamp, -VGOFF, split Rg, two-level edges) are covered later to avoid topic overlap.
Supply/ground parasitics: return closure defines reference shift
- What it represents: parasitic capacitance and inductance in supply rails, grounds, and interconnects.
- Failure mode: injected current produces ground bounce or reference lift that narrows effective thresholds.
- Victims: UVLO, fault comparators, digital inputs, and any logic that assumes a stable reference.
The most reliable fixes target the return closure first (geometry and partition), then tune edge shape as needed.
Three questions that classify most CMTI problems
- Where is the injection point? SW node coupling into control reference vs gate node.
- Where does the current return? control GND, driver GND, power GND, chassis/heatsink.
- Which threshold is violated? input logic, fault logic, UVLO, or gate-to-source margin.
These questions are designed to keep analysis in-scope: current flow and thresholds, not general EMI remediation.
H2-4. CMTI Spec Sheets Decoded: What Vendors Mean (and What They Don’t)
A CMTI number is conditional. System immunity requires matching stress definition, device state, and event-count rules—not just comparing a single kV/µs value.
A CMTI spec is a statement under test conditions
CMTI in a datasheet typically means: no unintended output or logic behavior when a defined common-mode dV/dt is applied under a defined fixture.
Two devices with the same “150 kV/µs” label may have different fixtures, different victim definitions, and different pass criteria.
Excitation differences that change the meaning
- dV/dt waveform: clean ramp vs ringing/overshoot; separate +dV/dt and −dV/dt behavior.
- CM step amplitude: the applied common-mode step (≥ Y V) changes injected current magnitude.
- Edge polarity: rising vs falling edge can stress different internal paths.
CMTI should be interpreted together with the applied CM step, not in isolation.
Device state differences that change pass/fail
- Input state: IN=H vs IN=L can stress different thresholds and latches.
- Load conditions: output loading and gate network alter internal behavior under transients.
- Supply and bias: VDD/VSS margins and isolated bias behavior affect UVLO and logic stability.
- Temperature: threshold drift changes effective noise margin.
The “fixture vs inverter” gap
- Layout parasitics: return closure changes; reference shifts appear where the fixture stays quiet.
- Isolated bias noise: switching-synchronous ripple can trip thresholds or reduce margin.
- Gate-loop ringing: non-ideal loops convert dv/dt into gate disturbance.
- Measurement injection: probe grounds and cables can create a new unintended return path.
These are system-level effects; a datasheet number does not automatically include them.
Project-level pass/fail definition (X/Y/N placeholders)
Stress: dV/dt ≥ X kV/µs (both +/− edges), CM step ≥ Y V.
State sweep: IN=H and IN=L; representative load and bias rails present.
Event counting: false switching ≤ N per 10M switching edges.
Fault integrity: /FLT must not chatter; allowed glitches ≥ tmin = Y ns must be zero (or ≤ N allowed).
Bias/logic stability: UVLO/reset/lockup events = 0 throughout the run.
A system “passes CMTI” only when this definition is met and documented.
Pick the right lever without expanding scope
Layout/return mismatch → focus on partition and return closure rules (later Layout chapter).
Bias/rail sensitivity → focus on isolation and bias injection paths (later Isolation chapter).
Measurement artifacts → focus on validation discipline and probe reference points (later Validation chapter).
This chapter standardizes spec interpretation; implementation details are intentionally handled in dedicated chapters.
H2-5. dV/dt in Real Power Stages: Not a Ramp—It Rings, Overshoots, and Shifts Reference
Real switching events are not ideal ramps. Narrow spikes, ringing, and reference shift can dominate CMTI outcomes even when the apparent ramp slope looks modest.
What matters is the event profile, not the average slope
Main ramp sets a baseline injection level. Spikes and ringing concentrate energy at higher frequency.
Reference shift changes effective thresholds and gate margin, turning small disturbances into false triggers.
CMTI failures often correlate with the worst 10–50 ns portion of an edge, not the average dv/dt measured over a longer window.
SW-node waveform = ramp + spikes + ringing
- Main ramp: the primary transition set by drive strength and load.
- Overshoot/undershoot: narrow positive/negative spikes driven by loop L and device/node C.
- Ringing: damped oscillation that can repeatedly cross internal thresholds.
A system can “look fine” if only the ramp is measured, while spikes and ringing still inject disruptive current.
Reference shift is often a di/dt problem
Fast current changes produce voltage drops across common inductance and shared returns, lifting the source/emitter reference during the edge.
Kelvin return reduces shared impedance between power current and gate reference. Non-Kelvin allows power-loop current to modulate the gate reference.
Reference shift reduces effective Vgs/Vge margin and can force input/fault thresholds to be crossed during a transient.
How real events disturb gate-driver victims
- Input thresholds: ringing and reference shift cause false transitions.
- UVLO logic: narrow rail dips or reference lift can trip state behavior.
- Fault comparators: transient injection can create /FLT chatter or disable events.
- Output stage: momentary upset can create pulse distortion or unintended toggles.
Victim type guides the next diagnostic step: input-path immunity, bias stability, or return-path control.
What to inspect first in a failing system
- Edge micro-interval: find the sharpest sub-interval, not the averaged slope.
- Spike polarity: note negative spikes (undershoot) that can stress thresholds and structures.
- Ringing duration: longer ringing increases repeated threshold crossing risk.
- Reference baseline: check if source/emitter reference moves during the event.
This chapter explains why failures occur; implementation changes are handled in dedicated chapters to avoid overlap.
Define dV/dt using the worst-case event profile
Measure window: compute dV/dt over the sharpest interval (≥ tmin = Y ns).
Spike limit: overshoot/undershoot magnitude ≤ X V (fixture-defined).
Ringing limit: ringing amplitude decays below X V within Y ns.
No victims triggered: false switching/false fault/UVLO upsets = 0 within the defined stress run.
Event-based definition prevents the “dv/dt looks low” false confidence that ignores spikes and reference shift.
H2-6. Driver-Side Immunity Levers: Input Structure, Filtering, Blanking, and State Behavior
Driver immunity is defined by the input path and transient state behavior: threshold strategy, filtering, and how the state machine responds during a dV/dt injection window.
CMTI robustness is often decided inside the input and state logic
Under common-mode stress, immunity depends on: input structure threshold margin filtering/debounce blanking windows state behavior
This chapter stays in-scope: only behaviors directly tied to CMTI under dV/dt injection—not unrelated feature pages.
Differential vs single-ended inputs
Differential inputs reject common-mode disturbances by comparing two correlated signals, reducing false transitions when references shift.
Single-ended inputs are more sensitive to reference movement because the threshold is evaluated against a local ground that may bounce.
Selection cue: if the environment exhibits large reference shift or strong cable coupling, differential signaling is typically more robust.
Noise margin and Schmitt behavior
- Threshold margin: determines how much injected disturbance can be tolerated before a false transition.
- Schmitt (hysteresis): prevents chatter by requiring a larger reversal to switch state again.
- Limit: narrow spikes and strong ringing can still cross both thresholds if margin is insufficient.
Linkage to H2-5: reference shift effectively reduces margin during the transient even if static levels look valid.
Suppressing short glitches without breaking control timing
Filtering removes narrow pulses caused by dV/dt injection, but introduces delay and can distort very short commanded pulses.
- Protects: IN pins and internal comparators from sub-µs noise.
- Trade-off: added latency and pulse-width sensitivity.
Filter choice must match the expected disturbance width; excessive filtering can create new timing failures.
What the output does during a transient upset
- Hold-last-state: output preserves the last valid state through a short upset.
- Fail-safe off: output forces a safe off state during detected ambiguity.
- Latch vs auto-recover: behavior after an upset determines whether faults accumulate or self-clear.
The correct behavior depends on the system hazard analysis; for hard-switch stages, unintended turn-on is typically unacceptable.
Blanking / ignore windows for dV/dt injection intervals
A blanking window temporarily ignores known-bad intervals where common-mode injection is strongest, preventing false decisions from transient artifacts.
- Goal: avoid acting on short-lived glitches that do not represent the commanded state.
- Scope: described here only for CMTI-related upset behavior, not for detailed DESAT configuration.
Window definition must align with real event width from H2-5 (spikes/ringing duration), otherwise false triggers remain.
Driver-side CMTI-relevant questions (device behavior)
- Inputs: differential available? Schmitt/hysteresis present? stated input noise immunity?
- Filtering: glitch reject width defined? does it distort minimum pulse width?
- State: hold-last or fail-safe? latch or auto-retry after upset?
- Fault pins: glitch behavior defined? /FLT and /RDY stable under injection?
This list keeps focus on CMTI-critical internal behavior; external gate-network and layout levers are handled in later chapters.
Define acceptable behavior during the injection window
No false IN transitions: spurious toggles ≤ N per 10M edges.
Output behavior: no unintended turn-on; pulse distortion ≤ X ns (or ≤ X% duty).
Fault pins: /FLT must not assert from injection; /RDY stable (0 events).
State recovery: defined (latch or auto-recover) and repeatable under the stress run.
Event counting and explicit behavior rules prevent ambiguous “it seems fine” conclusions.
H2-7. Isolation & Barrier Capacitance: Ciso is Your Hidden dV/dt Injector
Isolation ratings describe safety strength, but CMTI outcomes are often dominated by high-frequency displacement current through the barrier capacitance (Ciso).
Reinforced isolation can still inject current
In fast-switching power stages, the isolation barrier behaves like an AC coupling path at high frequency. Ciso turns SW-node dV/dt into displacement current that lands in the control reference network.
A strong safety barrier does not automatically imply a small injection path for CMTI stress.
Ciso → injected current → control reference shift → victims
- What increases injection: larger Ciso and sharper dV/dt event segments.
- Where it lands: control ground and local reference nodes.
- What fails: IN thresholds, UVLO logic, fault pins (/FLT, /RDY), and internal comparators.
Return closure determines whether injected current lifts the control domain reference or is absorbed in a safer loop.
Same “reinforced” label, very different Ciso
- Package geometry: facing area and distance between high dV/dt nodes and control pins.
- Pinout: adjacency and symmetry that changes electric-field coupling paths.
- Barrier construction: internal layer structure that reshapes the field distribution.
Ciso is a geometry-driven result; isolation class is a safety-driven result. They are correlated only loosely.
The critical question: where does the injected current return?
If displacement current closes through the control reference network, thresholds move and false decisions become likely. If it closes through a controlled, low-impedance loop away from sensitive references, immunity improves.
Interpretation rule: Ciso is not “bad” by itself; uncontrolled return closure is the real amplifier.
Integrated/external bias: transient current can lift the control domain
During dV/dt events, the isolated bias system also carries transient current through parasitics. The CMTI-relevant factor is whether that transient return path flows through sensitive control references.
This section intentionally avoids topology details; it focuses only on the CMTI intersection: transient return closure.
Page-level acceptance placeholders (Ciso / injection)
Barrier capacitance: Ciso ≤ X pF (or vendor-provided equivalent).
Injection current: Iinj ≤ Y mA @ dV/dt = X kV/µs (event-based definition).
Victim rules: false switching / false fault / UVLO upsets = 0 in 10M edges.
Return closure: documented loop that does not pass through sensitive control references.
This template prevents “isolation rating” from being misused as a proxy for high-frequency injection behavior.
H2-8. PCB Layout & Return Path: The Real CMTI Spec is Your Geometry
A high datasheet CMTI number does not survive poor geometry. Return closure, loop area, and dv/dt coupling area set the practical immunity of the design.
Geometry defines practical CMTI
The dominant board-level levers are: return closure gate-loop area dv/dt coupling area
This section is intentionally scoped to CMTI-coupled layout rules, not a general “layout handbook.”
Control reference must be continuous with short return
- Requirement: control ground/reference is continuous and does not rely on cross-split returns.
- Reason: injected current that crosses sensitive reference regions creates threshold violations.
- Victims: IN/logic thresholds, UVLO, fault pins.
Gate-drive loop must be minimal, with Kelvin source/emitter
- Requirement: the gate-drive loop closes locally; Kelvin reference avoids shared impedance with power current.
- Reason: shared inductance converts di/dt into reference shift that modulates Vgs/Vge.
- Victims: false turn-on risk and pulse distortion under transients.
Minimize capacitive coupling area from dv/dt nodes to control domain
- Requirement: dv/dt nodes avoid overlapping large control reference/signal areas.
- Reason: larger coupling area increases effective parasitic capacitance and injected current.
- Victims: input/fault comparators and internal state behavior.
Fast failure triggers seen in reviews
- Cross-split return: control return crosses partition boundaries near dv/dt regions.
- Mixed grounds: driver ground and power ground share long segments or ambiguous merge points.
- Bias return crossing: isolated-bias return passes through sensitive control reference area.
These patterns convert injected current into reference shift and threshold violations.
CMTI-focused layout review items (checkable)
- ☐ Control reference plane is continuous; no return crosses a split near dv/dt nodes.
- ☐ Gate-drive loop forms the smallest possible closed loop (forward + return paired).
- ☐ Kelvin source/emitter return is dedicated to the driver reference (not shared with power current).
- ☐ dv/dt nodes avoid overlapping sensitive reference/signal areas (min coupling area).
- ☐ IN and /FLT routing stays within the control domain and away from dv/dt regions.
- ☐ Isolated-bias transient return is documented and does not traverse sensitive references.
Each item is verifiable from geometry; no “best practice” ambiguity is required to audit.
Geometry rules must align to event-count pass criteria
Event-based stress: dV/dt ≥ X kV/µs, CM step ≥ Y V.
No victims triggered: false switching/false fault/UVLO upsets = 0 in 10M edges.
Review evidence: checklist above completed and archived with layout screenshots.
This prevents “layout looks fine” subjective judgments by tying geometry to measurable outcomes.
H2-9. Gate Network Interactions: Miller, -VGOFF, Split Rg, Two-Level Edges (CMTI View Only)
Gate-network knobs matter for CMTI because they change how easily dv/dt injection becomes a false Vgs/Vge rise, a ringing threshold crossing, or a transient state upset.
Each knob targets a specific CMTI failure mechanism
Miller injection lifts the gate during turn-off. Ringing creates repeated threshold crossings. Reference shift steals noise margin under dv/dt / di/dt events.
Scope rule: only CMTI-relevant impact is described here (mechanism → when to use → acceptance).
Symptom → knob shortcut (CMTI view)
- False turn-on during OFF: prioritize Miller clamp and -VGOFF.
- Spikes / ringing dominate events: prioritize split Rg and two-level edges.
- Event width is very short (worst 10–50 ns): prioritize edge shaping and local clamping.
The goal is to reduce threshold crossings in the worst event segment defined in earlier chapters.
Mechanism: pin gate to source during OFF to block Miller lift
Mechanism: a strong clamp path reduces the effective gate impedance during turn-off, limiting Vgs/Vge rise from Miller current.
When to use: dv/dt-correlated false turn-on signatures during OFF, especially when the SW node edge is the trigger.
When it will not save the design: large reference shift or local gate ringing that crosses thresholds at the device pins.
Gate OFF peak: Vgs_off_peak ≤ X V (or stays below Vth + margin).
False turn-on: 0 events in 10M edges.
OUT integrity: no glitches ≥ Y ns in OFF state.
Mechanism: increase OFF-state noise margin against dv/dt injection
Mechanism: a negative OFF bias shifts the baseline, making the same injected Miller disturbance less likely to cross the turn-on threshold.
When to use: OFF-state false turn-on risk remains after basic loop control, or when strong dv/dt events repeatedly lift the gate.
Recommended range: -VGOFF = -X … -Y V (placeholder).
OFF margin: Vgs_off stays below the effective turn-on threshold under stress.
Events: false turn-on = 0; /FLT and UVLO do not glitch.
Note: excessive slowing or excessive bias can create other constraints; only the CMTI-facing margin effect is evaluated here.
Mechanism: control dv/dt/di/dt and damping differently on ON and OFF edges
Mechanism: separate ON/OFF resistances allow independent control of edge sharpness and ringing energy, reducing injection and threshold chatter.
When to use: one edge is the CMTI trigger (typically the faster edge), or ringing is asymmetric between transitions.
Event-based dv/dt: worst-segment dV/dt ≤ X kV/µs.
Ringing: amplitude decays below X V within Y ns.
Victims: IN/OUT/FLT/UVLO show 0 false events in 10M edges.
Mechanism: keep “worst 10–50 ns” under control while preserving switching intent
Mechanism: a fast initial transition handles switching intent, then a gentler segment reduces overshoot and ringing that commonly drive CMTI failures.
When to use: failures correlate with narrow spikes/ringing rather than the average slope; event profile needs shaping.
Spikes: overshoot/undershoot ≤ X V (fixture-defined).
Ringing duration: ≤ Y ns above threshold-sensitive amplitude.
Pulse integrity: OUT pulse-width deviation ≤ Z ns under stress.
Over-slowing can create a different failure class
- Loss/thermal: slower transitions increase switching loss and temperature stress.
- Control sensitivity: slower edges can reduce timing margin or increase deadtime sensitivity.
This page only flags the direction of risk; detailed loss and control impacts belong to dedicated pages.
Pick the knob based on what crosses a threshold
- Gate rises during OFF: clamp / -VGOFF first.
- Waveform is spiky/ringing: split Rg / two-level first.
- State upset or /FLT chatter: reduce injection amplitude and verify measurement reference integrity.
The acceptance criteria above convert “it feels stable” into event-count pass/fail.
H2-10. Measurement & Validation: How to Prove CMTI on the Bench (and Avoid Fake Failures)
A valid CMTI result requires three aligned definitions: how dv/dt is applied, which victim signals are monitored, and how pass/fail is counted—without measurement-induced artifacts.
Prove CMTI with a reproducible workflow, not a screenshot
A bench validation must be repeatable and reportable: dv/dt method victim signals event counters probe integrity
The primary failure mode in CMTI validation is a “fake fail” created by reference choice or probe grounding.
Three things that must be defined up front
- dv/dt application: real half-bridge switching or a controlled injection fixture.
- Victim set: IN, OUT, /FLT, UVLO (and /RDY if used).
- Decision metrics: false triggers, missing pulses, fault chatter, resets/lockups.
Without these definitions, “passes” and “fails” are not comparable across labs or iterations.
Real half-bridge switching (most realistic)
- Strength: includes real spikes, ringing, and reference shift.
- Risk: more variables; measurement setup must be disciplined.
Best when the goal is system-representative immunity verification.
Controlled injection fixture (most controllable)
- Strength: parameter scanning is easier and more repeatable.
- Risk: may not reproduce the full return-path and ringing environment.
Best when the goal is comparative screening and sensitivity mapping.
Victim signals must be measured with a defined reference
- OUT: measure at the gate with a Kelvin-defined reference to driver ground.
- IN: define logic threshold and count false transitions.
- /FLT: count only pulses wider than the defined glitch width.
- UVLO: monitor rail behavior and state transitions under dv/dt stress.
Reference ambiguity is the fastest route to false conclusions.
Common measurement artifacts that create fake failures
- Ground lead loop: adds inductive pickup → fake glitches.
- Wrong reference point: uses power ground as reference → fake OUT chatter.
- Bandwidth limits: hides spikes → fake pass; or distorts edges → fake fail.
- Diff-probe CM range: saturation/clipping under CM steps → fake events.
A correct result requires the probe chain to survive the same CM environment as the DUT.
Make results explainable by sweeping controlled axes
- dV/dt axis: evaluate the worst-segment dV/dt defined by this page.
- CM step axis: sweep step amplitude (fixture-defined).
- Edge count: log events over 10M switching edges.
Event-count logging prevents single-shot screenshots from driving design decisions.
Report-ready pass/fail placeholders (X/Y/N/Z/M)
dV/dt stress: dV/dt ≥ X kV/µs (worst sub-interval definition).
CM step: ΔVCM ≥ Y V.
False triggers: ≤ N per 10M edges (target: 0).
/FLT integrity: no pulses with width ≥ Y ns.
OUT integrity: pulse-width deviation ≤ Z ns under stress.
State integrity: no UVLO/reset/lockup events in the stress run.
This template is designed to be copied into a validation report without adding new scope beyond CMTI.
H2-11. Troubleshooting Playbook: Fast Localization in 30 Minutes
Goal: localize the failure to Injection Path vs Threshold/State Behavior, then choose the smallest-change fix (geometry → edge shaping → IC swap).
0–5 min: Eliminate “fake failures” first
Lock measurement reference to a Kelvin driver reference point and re-check event existence.
- Pass: event reproduces with Kelvin reference → treat as real CMTI/dv/dt behavior.
- Fail: event disappears after reference cleanup → fix probing/return loop before any hardware change.
Step 1: Classify the symptom (observable)
- False turn-on: shoot-through / current spike / OFF gate lift.
- False turn-off: missing pulse / narrowed OUT pulse width.
- False fault: /FLT chatter / spurious shutdown (no real SC).
- Logic upset: RDY drop / reset / stuck state.
Output of Step 1: choose a likely family — Input upset, Output stage upset, Bias/REF shift, or Return-path coupling.
Switch A: Reduce dv/dt (edge shaping)
- Action: increase Rg_off or enable two-level turn-off.
- Observe: event count vs dv/dt edge alignment.
- Interpretation: big improvement → injection strength dominates.
Switch B: Change reference (force Kelvin)
- Action: shorten/close driver return; force Kelvin source/emitter.
- Observe: OUT/FLT glitch amplitude changes strongly.
- Interpretation: strong change → reference shift/geometry dominates.
Switch C: Break injection (Ciso/area/Shield)
- Action: reduce coupling area from SW node to control domain; adjust shield tie.
- Observe: dv/dt correlation drops.
- Interpretation: correlation drop → coupling path confirmed.
Minimum-change fix order
- 1) Geometry/return: partition + Kelvin + minimize coupling area.
- 2) Gate shaping: split Rg, clamp enable, two-level edges.
- 3) IC swap: only after (1)(2) are verified inadequate.
Re-test must-haves (report template placeholders)
- dv/dt ≥ X kV/µs (worst sub-interval defined)
- ΔVCM ≥ Y V
- false events ≤ N per 10^M edges (target 0)
- /FLT glitch width ≥ Yns → must be 0
- OUT pulse-width error ≤ Z ns
Field “CMTI quick kit” (example material numbers)
Purpose: enable fast dv/dt reduction, return-path experiments, and temporary shielding without re-spinning PCB.
- Split gate resistors (0603): Yageo RC0603FR-072R2L (2.2Ω), RC0603FR-074R7L (4.7Ω)
- Ferrite bead (0603): Murata BLM18AG601SN1D (600Ω @ 100MHz)
- HF decoupling MLCC (0603): Murata GRM188R71H104KA93J (0.1µF, X7R)
- Conductive copper foil shield tape: 3M EMI Shielding Tape 1181
- HV differential probe (validation): Tektronix TDP0500
H2-12. Engineering Checklist: Design → Bring-up → Production (CMTI Gate)
Objective: turn CMTI/dv/dt immunity into a repeatable gate checklist with evidence packages and change-triggered re-validation.
Design gate (budget + topology constraints)
- ☐ Define worst-interval dv/dt target: X kV/µs
- ☐ Define ΔVCM step: Y V
- ☐ Define “false event”: ≤ N / 10^M
- ☐ Budget Ciso or injection current: Ciso ≤ XpF or Iinj ≤ YmA
- ☐ Reserve split Rg + optional bead footprint
- ☐ Reserve Kelvin source/emitter routing (no shared power return)
Bring-up gate (bench proof + probe rules)
- ☐ Validation method: real half-bridge or injection fixture
- ☐ Kelvin REF measurement point labeled on PCB
- ☐ /FLT glitch definition: width ≥ Yns = 0
- ☐ OUT pulse-width error ≤ Z ns
- ☐ Sweep dv/dt, ΔVCM, temperature, bias corners
- ☐ Evidence pack: waveforms + event counter table
Production gate (consistency + change triggers)
- ☐ Sample test: K units per lot
- ☐ Re-test triggers: PCB stackup / spacing / coating changes
- ☐ Re-test triggers: driver IC / iso bias / gate network changes
- ☐ Re-test triggers: layout geometry around SW node changes
- ☐ Report template fixed to X/Y/N/Z/M placeholders
- ☐ Fast failure handling: follow H2-11 decision tree
Reference BOM (CMTI-critical nodes — example material numbers)
Gate network & damping
- Split Rg footprints (0603): Yageo RC0603FR-072R2L, RC0603FR-074R7L
- Gate bead (0603): Murata BLM18AG601SN1D
Decoupling & shielding
- Local HF MLCC (0603): Murata GRM188R71H104KA93J
- Conductive shield tape: 3M 1181
- Bench validation probe: Tektronix TDP0500
Evidence package recommendation: include PCB screenshots (partition + Kelvin), probe photos (Kelvin/no-clip), dv/dt sweep table (X/Y/M), and event counters (N/10^M).
H2-13. Applications & IC Selection Logic (CMTI-centric)
Focus: map application stress profile → injection path priorities → driver features that matter for CMTI → bench validation gate (X/Y/N/Z/M).
Stress profile → what fails first
- SiC/GaN inverter: highest dv/dt + strong REF shift → false turn-on / spurious faults.
- PFC/HB/LLC: ringing + overshoot → threshold crossings + “fixture-induced” failures.
- Multiphase/VR: timing/skew sensitivity → pulse-width distortion and channel mismatch windows.
CMTI-centric selection scoring (keep it closed-loop)
- Immunity core: CMTI rating + input structure + transient state behavior.
- Injection control: Ciso (or Iinj-equivalent) + bias return behavior.
- Timing integrity: propagation delay / channel skew → defines false window.
- Control levers: availability of clamp / split outputs / disable path.
A driver “wins” only if it passes the fixed validation template: dv/dt ≥ X, ΔVCM ≥ Y, false events ≤ N/10^M, /FLT glitch=0, OUT ΔPW ≤ Z.
Representative IC material numbers (examples to anchor evaluation)
These are example parts to anchor datasheet reading and evaluation planning (verify voltage/current/temp/safety needs per application).
- Single-channel reinforced isolated (SiC/IGBT focus): TI UCC21750
- Dual-channel isolated (bridge/multiphase building block): TI UCC21520
- Isolated single-channel driver (anchor part): Analog Devices ADuM4121
- Isolated gate driver IC (high-side, anchor part): Infineon 1EDC20I12MH
- Isolated dual drivers (anchor family): Skyworks/Silicon Labs Si8239x
Selection-to-validation “starter BOM” (CMTI bench + mitigation)
- Gate shaping resistors: Yageo RC0603FR-072R2L, RC0603FR-074R7L
- Noise choke at gate/logic: Murata BLM18AG601SN1D
- Local HF decoupling: Murata GRM188R71H104KA93J
- Temporary coupling-area control: 3M 1181 conductive copper foil tape
- Validation instrumentation anchor: Tektronix TDP0500 HV differential probe
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H2-13. FAQs (CMTI & dv/dt) — Disputes, Acceptance, Fast Triage
Fixed 4-line format per question: Likely cause / Quick check / Fix / Pass criteria. All pass/fail uses the same quantified template.
Quantified acceptance template (placeholders)
- dv/dt ≥ X kV/µs (define worst sub-interval used for evaluation)
- ΔVCM step ≥ Y V (common-mode step magnitude)
- False events ≤ N per 10^M switching edges (target 0)
- /FLT glitch width ≥ Yns → must be 0 occurrences
- OUT pulse-width error ≤ Z ns (vs commanded pulse)
Datasheet CMTI = 150 kV/µs, but false turn-on still happens — suspect Ciso injection or gate-loop L first?
Likely cause: Gate-loop inductance and reference shift amplify Miller injection; Ciso injection is the second common path when cabinet geometry changes coupling.
Quick check: (1) Increase Rg_off or enable two-level turn-off and see if events collapse; (2) Force Kelvin source/emitter reference and compare OUT/Gate behavior.
Fix: First tighten gate loop (Kelvin, minimize loop area, reduce coupling area to SW node), then shape edges (split Rg / clamp), then consider a driver with stronger transient state behavior.
Pass criteria: Under dv/dt ≥ X and ΔVCM ≥ Y, false turn-on ≤ N/10^M (target 0) and OUT ΔPW ≤ Z ns.
/FLT chatters only during turn-off — input upset or fault-pin pickup?
Likely cause: Fault pin (DESAT/CS/FLT) pickup or reference bounce during the highest dv/dt interval; less often, input logic upset if the input path is single-ended and high impedance.
Quick check: Hold input constant (no PWM toggling) while switching the power stage; if /FLT still chatters, it is pickup/REF-related rather than input decoding.
Fix: First reduce pickup at the fault node (short return, Kelvin REF, minimize high-impedance loop area), then add a clean blanking/ignore window if supported, then adjust edge shaping.
Pass criteria: /FLT glitch width ≥ Yns must be 0, with dv/dt ≥ X, ΔVCM ≥ Y, and false events ≤ N/10^M.
Passes at 25°C but fails hot — threshold drift or bias droop under dv/dt?
Likely cause: Bias droop and UVLO margin shrink under dv/dt-induced return current; threshold drift is secondary unless the failure aligns with a specific input edge.
Quick check: Log bias/UVLO-related signals at temperature while holding dv/dt stress constant; verify whether failures correlate with bias dips rather than input activity.
Fix: First increase bias headroom and local decoupling at the driver reference, then fix return closure (Kelvin, partition), then refine dv/dt shaping only if needed.
Pass criteria: At hot corner with dv/dt ≥ X, no UVLO resets, false events ≤ N/10^M, and OUT ΔPW ≤ Z ns.
Works on bench, fails in inverter cabinet — return path introduced via heatsink/chassis?
Likely cause: Heatsink/chassis creates a new high-frequency common-mode return path, increasing coupling area and shifting the control-domain reference during dv/dt edges.
Quick check: Reproduce cabinet mounting while monitoring control-domain reference vs chassis; temporarily change shield/heatsink bonding point and observe event correlation with dv/dt.
Fix: First control the return path (single-point bonding strategy for HF return, reduce coupling area), then adjust barrier/placement to reduce injection, then shape edges.
Pass criteria: In cabinet configuration, meet dv/dt ≥ X, ΔVCM ≥ Y, false events ≤ N/10^M, and /FLT glitch = 0.
OUT pulse narrows or “missing pulse” appears at high dv/dt — output stage upset or UVLO dip?
Likely cause: UVLO/bias dip or internal transient state behavior forces output hold-off; pure output-stage upset is less common unless reference shift is severe.
Quick check: Compare OUT pulse-width error vs bias/UVLO flags; if pulse errors line up with bias dips, treat as bias/return issue first.
Fix: First improve bias stability at the driver reference (local decoupling + return closure), then ensure input structure is robust (differential/Schmitt where applicable), then refine edge shaping.
Pass criteria: OUT ΔPW ≤ Z ns with dv/dt ≥ X and false events ≤ N/10^M.
False turn-on happens only on high-side transitions — Miller injection or source reference shift?
Likely cause: Source/emitter reference shift plus Miller injection during the fastest dv/dt interval; the combination crosses the effective Vgs threshold.
Quick check: Measure gate-to-Kelvin-source Vgs during the HS dv/dt edge; if Vgs spikes coincide with dv/dt ring peaks, it is Miller/REF-driven.
Fix: First enforce Kelvin source/emitter and reduce loop inductance, then enable/strengthen Miller clamp or add modest -VGOFF, then tune split Rg/two-level edges.
Pass criteria: Under dv/dt ≥ X, false turn-on ≤ N/10^M (target 0) and OUT ΔPW ≤ Z ns.
Fails only when isolated bias is enabled — bias return injection or supply bounce?
Likely cause: Isolated bias return path closes through an unintended HF path, lifting the control-domain reference during dv/dt; supply bounce then triggers UVLO or logic upset.
Quick check: Switch with bias off/on under the same dv/dt and compare reference movement; if reference shift increases with bias on, the return closure is the root.
Fix: First re-route/contain bias HF return at the driver reference (short loop, local decoupling, partition), then reduce coupling area to SW node, then edge-shape as needed.
Pass criteria: With bias enabled and dv/dt ≥ X, no UVLO resets, /FLT glitch = 0, false events ≤ N/10^M.
Different probe setup flips the verdict — ground-loop artifact or probe common-mode limit?
Likely cause: Ground-lead loop injects dv/dt current into the measurement reference, or the probe exceeds common-mode range and clips, creating a fake event.
Quick check: Repeat using a verified HV differential probe and Kelvin reference; remove ground clips and keep the same bandwidth/termination.
Fix: Standardize the measurement method (Kelvin REF + differential probing + fixed bandwidth), then re-run the acceptance template before changing hardware.
Pass criteria: Using the standardized method, meet dv/dt ≥ X and false events ≤ N/10^M; /FLT glitch ≥ Yns must be 0.
One unit fails while others pass — Ciso spread or assembly-driven coupling area change?
Likely cause: Assembly variance changes effective coupling area (spacers, mounting, shield contact) more often than true Ciso spread; both appear as higher injected common-mode current.
Quick check: Swap the failing PCB into a known-good mechanical stack (heatsink/shield) and see if the failure follows mechanics or the PCB.
Fix: First control geometry (consistent mounting/bonding, reduce coupling area), then improve return closure and edge shaping; only then consider IC/isolation changes.
Pass criteria: Across units, false events ≤ N/10^M at dv/dt ≥ X; /FLT glitch = 0 and OUT ΔPW ≤ Z ns.
-VGOFF reduces false turn-on, but EMI worsens — is the edge too fast or is ringing dominant?
Likely cause: -VGOFF improves noise margin but can increase dI/dt-driven ringing if the gate loop is inductive; EMI worsens when ringing energy dominates.
Quick check: Compare gate waveform with and without -VGOFF using Kelvin reference; if ringing amplitude increases, the loop/edge shaping needs adjustment.
Fix: First reduce loop inductance and add controlled damping (split Rg / small bead), then keep -VGOFF at the minimum that achieves CMTI margin, then tune two-level edges.
Pass criteria: With -VGOFF enabled, false events ≤ N/10^M at dv/dt ≥ X while maintaining OUT ΔPW ≤ Z ns.
Reducing dv/dt “fixes” CMTI but losses rise — how to choose the minimum edge shaping?
Likely cause: The system is operating at the margin where injected current and reference shift cross the trigger threshold; dv/dt reduction moves it below the trigger point but costs switching loss.
Quick check: Sweep Rg_off (or two-level timing) and record event rate vs dv/dt worst-interval; identify the knee where events drop to 0.
Fix: First address geometry/return to raise margin, then apply the smallest dv/dt reduction that achieves “0 events,” then verify thermal impact separately (without changing CMTI fixture).
Pass criteria: Select settings where false events = 0 for 10^M edges at dv/dt ≥ X and OUT ΔPW ≤ Z ns.
/RDY drops without /FLT — transient logic upset or UVLO reset path?
Likely cause: UVLO-related internal reset or transient logic upset due to reference shift; /FLT may not assert if the shutdown path is “silent” for that condition.
Quick check: Correlate /RDY drop timing with bias/reference movement during dv/dt edges; repeat with dv/dt reduced to see if the behavior scales with injection strength.
Fix: First stabilize bias at the driver reference and close the HF return path, then reduce coupling area and add input robustness, then validate state behavior under dv/dt.
Pass criteria: /RDY must remain asserted with dv/dt ≥ X, false events ≤ N/10^M, and /FLT glitch ≥ Yns = 0.
Reporting rule: every dispute must be resolved using the same quantified template (X/Y/N/Z/M) and the same measurement method (Kelvin REF + fixed bandwidth).
