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Delay, Skew & Jitter in Gate Driver ICs

Delay, Skew & Jitter in Gate Driver ICs

← Back to: Gate Driver ICs

Delay, skew, and jitter define the real PWM timing resolution and safety margin: keep relative timing (skew/edge spread) within a quantified window across corners, then use that window to set deadtime, verify current sharing, and select matched-channel drivers with confidence.

The practical goal is simple: measure timing with a fixed contract, back-calculate allowable skew/spread from Fsw, phases, and min pulse width, and accept only designs that pass worst-case gates (VDD/Temp/load) with data-based criteria.

H2-1 · Definition & Scope

Definition & Scope: Delay, Skew, and Jitter (Timing Metrics)

What the page defines (authoritative measurement vocabulary)

Propagation delay
Time from a defined input threshold crossing to a defined output threshold crossing under stated conditions.
Channel skew
Difference of propagation delay between channels (A vs B) under identical stimulus, loading, and environment.
Timing jitter
Short-term variation of an edge timestamp around a reference (mean, ideal edge, or input-referenced TIE) over a defined observation window.

Boundary choices (Pin-to-Pin vs Pin-to-Gate)

Two boundary definitions are common. Both are valid, but they answer different engineering questions. This page locks the default to avoid review and lab disputes.

Pin-to-Pin (default)
From: PWM input pin threshold crossing (e.g., 50% VDD or VIH/VIL crossing).
To: driver output pin threshold crossing (same rule).
Use: datasheet alignment, IC comparison, chain timing budget for PWM resolution.
Pin-to-Gate (system reality)
From: PWM input threshold crossing.
To: gate node crossing a defined VGS threshold (e.g., VGS=Vth or a fixed VGS level).
Use: explaining effective deadtime distortion, bridge overlap risk, and phase alignment at the power stage.

Rule: Selection and specification mapping in this page uses Pin-to-Pin. System impact discussions may reference Pin-to-Gate only to describe consequences, without expanding into power waveform/SI/EMI theory.

Delay directionality (tPLH vs tPHL)

  • tPLH: input Low→High edge to output Low→High edge (threshold-to-threshold).
  • tPHL: input High→Low edge to output High→Low edge (threshold-to-threshold).
  • Why separate? Rise and fall paths are often asymmetric. Deadtime and overlap risk depend on the direction-specific worst case, not an average value.
  • Hard rule: Do not treat (tPLH+tPHL)/2 as a universal timing number for safety margin or deadtime verification.

Skew: engineering acceptance vs debug statistics

Skew must be stated with a statistical contract. Without it, the same hardware can “pass” in one lab and “fail” in another.

  • Guaranteed skew (max): preferred for design review, safety margin, and production gates.
  • Measured skew (max-min over N edges): useful for bring-up triage; depends strongly on sample size and window.
  • Skew distribution (σ / percentiles): debug-only; not a replacement for max-based acceptance unless contract explicitly allows it.
Minimum contract items
N edges: X (placeholder) · Window: Y ms or Y switching cycles (placeholder) · Conditions: VDD, temperature, load, probe method, and threshold definition (all explicit).

Jitter: which type is in scope

  • Primary metric: edge timing jitter (edge timestamp variation), because it directly limits edge placement accuracy (effective timing LSB).
  • Optional support: cycle-to-cycle jitter (short-term stability indicator).
  • De-scoped: period jitter deep dives (often becomes a clock/PLL topic and cross-domain).
Preferred reporting
Acceptance: p-p or P99.9 (placeholder) · Debug: RMS (placeholder) · Reference: input-referenced TIE or fixed timebase reference (explicit).

Scope guard (to prevent topic overlap)

  • In scope: definitions, boundaries, statistics, timing budgets, measurement playbooks, acceptance templates, and selection logic for delay/skew/jitter.
  • Out of scope: protection mechanism theory (UVLO/DESAT/etc.), CMTI physics, and detailed power waveform/SI/EMI analysis.
  • Rule: when those domains affect timing, they appear only as disturbance sources with measurement consequences, not as expanded theory sections.
Delay, Skew, and Jitter measurement boundaries Block diagram from controller PWM through optional isolation to gate driver outputs and gate node, with timestamp points marking delay, skew, and jitter definitions. Controller PWM IN Isolator Optional Gate Driver CH-A CH-B GATE Delay (Pin-to-Pin) Skew (A vs B) Jitter (edge spread) Timestamp point Signal path System node
Diagram: Locked measurement boundaries for Delay, Skew, and Jitter.
H2-2 · Why It Matters

Why It Matters: PWM Resolution, Deadtime Integrity, and Control Bandwidth

1) Effective timing LSB (edge placement limit)

PWM resolution is not only the controller step size. The achievable edge placement accuracy is bounded by the worst timing uncertainty in the chain:

  • Quantization floor: controller time-step or digital update granularity.
  • Channel-to-channel floor: skew (A vs B) that shifts relative phase or effective deadtime.
  • Short-term floor: edge timing jitter (percentile or p-p) that randomizes the edge timestamp.

Practical rule: if skew/jitter is already on the order of the intended PWM step, additional PWM resolution does not translate into stable control outcomes.

2) Deadtime distortion (tPLH/tPHL asymmetry)

Deadtime is implemented in the controller, but realized in hardware through the driver chain. When rise and fall delays differ, the effective deadtime shifts away from the programmed value.

  • Too small effective deadtime: overlap risk increases (shoot-through susceptibility rises).
  • Too large effective deadtime: reverse conduction time increases (loss and temperature rise).
  • Key point: the risk is edge-direction dependent; a single “average delay” cannot represent it.

Acceptance must therefore constrain worst-case direction-specific timing mismatch, not only typical delay.

3) Multiphase & multibridge consequences (phase error and current imbalance)

In interleaved multiphase and multi-bridge systems, the critical variable is often relative timing: skew becomes a phase placement error and directly maps into measurable system symptoms.

  • Phase placement error: a fixed time offset corresponds to a larger phase angle error at higher switching frequency (shorter period).
  • Observable outcomes: phase current imbalance, uneven thermal load, circulating current, and reduced soft-switching margin windows.
  • Engineering implication: absolute delay can be calibrated in some architectures, but skew and jitter are harder to remove in real time.

4) Control bandwidth ceiling (timing noise becomes modulation noise)

Edge timing jitter behaves like a modulation noise source: it randomizes duty/phase placement around the control target. As loop gain or update rate increases, timing noise can become the dominant limiter rather than controller capability.

  • Higher update rate is beneficial only if the driver chain maintains sufficiently low edge timing uncertainty.
  • Channel matching often sets the practical limit for tight phase control, especially when multiple legs must remain synchronized.

System-level requirement statement: the usable bandwidth is limited by the worst timing uncertainty in the chain, not by the controller alone.

Skew and jitter determine effective timing LSB Overlay of two PWM channels showing skew between edges and jitter as edge timestamp spread, illustrating the effective timing resolution limit. Channel A B Skew Jitter (edge spread) Effective timing LSB time Skew & Jitter limit PWM edge accuracy → deadtime integrity & control bandwidth
Diagram: Skew and jitter set the practical edge placement resolution.
H2-3 · Datasheet Mapping

Datasheet Mapping: Which Timing Numbers Are Actually Guaranteed

Objective (prevent the three most common misreads)

  • Typical ≠ guaranteed: typical values are useful for expectations, not for margin or pass/fail.
  • 25°C ≠ full range: timing metrics drift with PVT and can break matching at temperature extremes.
  • Single condition ≠ global truth: VDD, load, thresholds, and test setup can shift the reported timing numbers.

1) Delay fields: tPLH / tPHL (typical vs max)

Selection (design-in)
Use max / guaranteed values for tPLH and tPHL (directional). Typical values remain as a bring-up expectation only.
Acceptance (bring-up / production)
Acceptance must be defined against max/limit under stated conditions (VDD/Temp/Load/threshold). If datasheet lacks a max, add a measured worst-case limit to the verification gates.
Non-negotiable
Treat rise/fall paths separately. Avoid collapsing delay into a single averaged number.

2) Skew fields: matched delay / channel-to-channel skew (max)

Matching claims only become actionable when the datasheet provides an explicit contract: a max skew number plus the conditions under which it holds.

Look for
channel-to-channel skew (max), matched propagation delay, delay matching, Δt, inter-channel mismatch.
Read the conditions
Confirm VDD/VISO, temperature range, output load (C/R), threshold definition, and test setup. Without these, the skew number is not portable across systems.
Engineering verdict
For multiphase/multibridge timing integrity, prioritize max skew guarantee. “Matched” typical-only claims are not sufficient for acceptance.

3) Jitter fields: when datasheet does not specify jitter

Many gate drivers do not list jitter explicitly. A practical substitute is required to keep timing budgets and acceptance criteria defensible.

Proxy A (preferred)
Edge timing dispersion: measure propagation delay repeatedly over N edges and report p-p or P99.9 (window W) as the “edge spread” proxy for jitter.
Proxy B (diagnostic)
Threshold-crossing sensitivity: verify that input integrity (reference + noise) does not dominate edge timestamp stability. Use this to explain why single-ended vs differential inputs can change measured edge spread.
Proxy C (conservative)
Delay variation bounds: when only “delay vs VDD/temp” is provided, split requirements into short-term spread (Proxy A) and PVT drift (sweep-based), then gate each separately.

Condition checklist (minimum fields to record)

  • Threshold rule: 50% crossing or VIH/VIL crossing (must be explicit and consistent).
  • VDD/VISO: nominal and min/max used during the test.
  • Temperature: 25°C vs full range (record actual chamber or board temperature).
  • Load: output C/R (or gate-equivalent load model) and probe capacitance impact.
  • Measurement setup: trigger source, timebase, channel deskew, cable lengths.
  • Statistics: N edges, window W, metric type (max, p-p, P99.9, RMS).

Acceptance templates (placeholders for review and test plans)

Delay (directional)
tPLH ≤ X ns, tPHL ≤ Y ns @ (VDD=…, Temp=…, Load=…, Threshold=…).
Skew (max)
skew(max) ≤ Z ns across channels @ (same conditions).
Jitter proxy
edge spread ≤ J ns (p-p or P99.9) over N edges within W ms.
Datasheet field map for delay skew jitter Three-column chip map showing common datasheet field names for delay, skew, and jitter, plus a condition checklist strip for VDD, temperature, load, and threshold. Delay Skew Jitter tPD tPLH tPHL tpLH / tpHL prop delay delay vs VDD/T Δt (A–B) skew (max) matched delay delay matching inter-channel matched (cond.) edge jitter TIE cycle-to-cycle dispersion p-p / P99.9 proxy if missing Condition keys: VDD Temp Load Threshold
Diagram: Datasheet field-name map and the minimum condition keys required for a valid timing contract.
H2-4 · Timing Budget Method

Timing Budget Method: Build a Worst-Case Window Without Guesswork

1) Choose the budget target (edge-based by default)

Default target
Edge-based budget: budget edge placement for rising and falling separately. This aligns with deadtime integrity, phase alignment, and multichannel synchronization.
Optional view
Duty-based view may be used to summarize average duty error, but it must not replace edge-based acceptance when overlap risk exists.
Rule
Keep directional components separate: tPLH and tPHL are distinct budget items.

2) Decompose the chain (standard segments)

A reusable budget requires fixed segmentation. Each segment contributes different uncertainty types.

  • Controller timing: quantization / update timing variation.
  • Isolator (if used): propagation delay + skew + edge spread contribution.
  • Driver: tPLH/tPHL + channel mismatch.
  • Layout / IO: length mismatch + reference differences that shift threshold crossing time.
  • Measurement uncertainty: trigger method + probe/cable/timebase effects that create false skew/jitter.

3) Combine uncertainties (max-sum vs RSS)

Use max-sum when
acceptance affects safety margin (overlap risk), datasheet provides only max bounds, or error sources may be correlated (shared temperature or supply noise).
Use RSS when
independent random sources are supported by data (e.g., measured RMS components), and the goal is typical-performance estimation rather than acceptance.
Recommended practice
Design/production gates: max-sum default. Bring-up analysis: RSS may be included as a secondary expectation line.

4) Translate budget to requirements (X/Y/Z outputs)

Budget outputs must be expressed as enforceable requirements that map to datasheet fields or measurable proxies.

Relative alignment
skew ≤ X ns (max) across channels @ defined conditions.
Short-term stability
edge spread ≤ Y ns (p-p or P99.9) over N edges within W ms.
Directional integrity
tPLH and tPHL must satisfy deadtime margin requirements (express margin as M ns minimum under worst case).

Budget fill-in template (for reviews and test plans)

  • Target: edge-based (default) / duty-based (optional summary).
  • Edges: rising and falling separated.
  • Conditions: VDD=… · Temp=… · Load=… · Threshold rule=…
  • Window: N edges · W ms (or W switching cycles).
  • Combine rule: max-sum (acceptance) · RSS (analysis, optional).
  • Outputs: skew ≤ X ns · edge spread ≤ Y ns · deadtime margin ≥ M ns.
Timing budget chain and worst-case window Five-stage timing budget chain from controller through isolator and driver to layout and measurement uncertainty, with a final worst-case window summary outputting skew, jitter proxy, and matching requirements. Controller Isolator Driver Layout / IO Measure quantization update jitter tPD skew edge spread tPLH tPHL mismatch len diff ref shift threshold Δt trigger timebase probe C Worst-case window (outputs) skew ≤ X ns edge spread ≤ Y ns match ≤ Z ns Acceptance uses max-sum by default; RSS may be reported for typical analysis only
Diagram: A reusable timing budget chain and a clear worst-case output contract (X/Y/Z).
H2-5 · Root Causes Inside Driver Chain

Root Causes Inside the Driver Chain: What to Suspect First

Triage order (do this before blaming the power switch)

  • Step 1 — Measurement contract: lock threshold rule, trigger reference, probe loading, and window (N edges / W ms).
  • Step 2 — Input threshold stability: single-ended vs differential behavior and reference stability near the crossing point.
  • Step 3 — Isolation / combo mismatch: channel-to-channel mismatch or “matched delay” conditions not met.
  • Step 4 — High-side domain shift: HS level-shift/domain conditions changing delay relative to LS.
  • Step 5 — Output load crossing time: Cload/probe C shifts the time the edge crosses the chosen threshold.

1) Input threshold & noise: why edge timing spreads

Timing consequence
Noise or reference movement near the input threshold shifts the timestamp of the threshold crossing, appearing as edge spread (jitter proxy). Single-ended inputs are typically more sensitive to reference movement than differential inputs.
Fast check
Keep the same PWM source and compare single-ended vs differential input mode (or compare two input conditioning options) while keeping the threshold rule fixed.
Verdict
If edge spread collapses with improved input referencing, suspect threshold noise / reference shift before any power-stage changes.

2) Isolation / combo devices: channel mismatch signatures

Timing signature
Skew that is stable across switching frequency and operating point often indicates fixed channel mismatch (path length / internal routing mismatch).
Swap test
Swap A/B channel mapping (or swap isolator channels if separable). If skew follows the mapping, the dominant contributor is the isolation/combo segment.
Verdict
Prefer devices with an explicit skew(max) guarantee under stated conditions. Typical-only “matched” claims are not acceptance-grade.

3) High-side domain shift: HS vs LS delay divergence

Timing consequence
HS propagation delay can shift relative to LS when the HS domain conditions change, producing an apparent HS-only delay drift or HS/LS skew shift.
Fast check
Compare HS and LS delays using the same threshold rule and the same measurement method. Apply controlled operating-point changes and observe whether the drift is HS-dominant.
Verdict
If HS timing moves while LS remains stable, suspect level-shift / domain sensitivity rather than the power switch.

4) Output strength & load: threshold crossing time is not constant

Timing consequence
Output drive strength and total load (gate-equivalent Cload + probe C) change the edge slope, shifting the moment the waveform crosses the defined threshold. This appears as delay variation and can inflate measured edge spread.
Fast check
Standardize the load model and probe mode. If changing probe/loading changes delay/skew/jitter materially, prioritize output load + measurement loading as the root cause.
Verdict
Do not treat threshold-crossing timestamps as “intrinsic” unless Cload/probe loading is controlled and recorded.
Segmented attribution for delay skew jitter inside the driver chain Five-stage chain diagram with short keyword chips under each segment and a symptom-to-first-suspect panel to prioritize debugging order. Input Isolation HS Level Shift Output Stage Measurement 2 3 4 5 1 threshold noise ch mismatch skew(max) domain offset Cload crossing Δt trigger probe C Symptom → first suspect Jitter ↑ Input / Threshold Measurement contract Skew ↑ Isolation / Combo Thermal symmetry Delay shift HS domain Output load
Diagram: A prioritized, segmented attribution map for timing issues inside the driver chain.
H2-6 · PVT Drift & Symmetry

PVT Drift & Symmetry: Why Timing Breaks in the Field

Field pattern: lab looks fine, deployment fails

  • Delay drift shifts edge placement and can erode deadtime margin over temperature and supply variations.
  • Skew drift is driven by channel non-uniformity, often dominated by thermal gradients and asymmetry rather than uniform temperature rise.
  • Jitter amplification is often a reference/threshold stability problem under noisier environments and longer wiring.

1) Delay drift (tempco / VDD sensitivity) → deadtime & phase risk

What changes
Propagation delay varies with temperature and supply conditions. Directional delays (tPLH, tPHL) can drift differently.
Why it matters
Drift directly shifts effective edge placement, impacting deadtime integrity and phase alignment under worst-case PVT.
Pass criteria template
ΔtPLH(PVT) ≤ X ns, ΔtPHL(PVT) ≤ Y ns over defined VDD and temperature corners.

2) Skew drift → symmetry problem (thermal gradient & self-heating)

Root mechanism (timing view)
Skew is a channel difference. It grows when channels experience different conditions, most commonly thermal gradients or asymmetric self-heating.
Diagnostic action
Measure skew while recording A/B local temperatures (board sensor or spot measurement). Swap channel mapping to check whether skew follows the hotter side.
Pass criteria template
skew(max) ≤ Z ns across PVT corners, with a recorded channel temperature delta (ΔT) during the test.

3) Jitter amplification → threshold/reference stability in noisy environments

What changes
In noisier environments, threshold crossing timestamps vary more due to reference movement and local noise near the crossing point.
Control the contract
Fix the threshold rule, trigger strategy, N edges, and window W. Otherwise “field jitter” measurements are not comparable to lab results.
Pass criteria template
edge spread ≤ J ns (p-p or P99.9) over N edges within W ms, under the defined environment conditions.

PVT stress recipe (minimal, reusable)

  • Voltage corners: test at nominal and min/max VDD (and VISO if applicable).
  • Temperature corners: test at low / room / high corners with stable soak time.
  • Statistics: record N and W for edge spread; record max skew; record directional delays.
  • Symmetry notes: record channel temperature delta (ΔT) and any asymmetry in heat paths or airflow.
PVT triangle influence on delay skew jitter A PVT triangle with arrows pointing to Delay, Skew, and Jitter boxes, highlighting which corner factors dominate each timing metric and emphasizing symmetry and threshold stability. PVT T P V Delay Skew Jitter Sym A/B Threshold Record conditions (P/V/T), enforce symmetry, and keep a stable threshold/measurement contract
Diagram: P/V/T corners drive Delay/Skew/Jitter differently; skew is dominated by symmetry, jitter by threshold/reference stability.
H2-7 · Measurement Playbook

Measurement Playbook: How to Measure Without Fooling Yourself

Measurement target: IN-pin logic edge vs gate-node threshold crossing

IN-pin timing
Measures the logic-path contract (controller/isolator/driver input-to-output pin behavior) with minimal dependence on gate loading.
Gate-node timing
Measures the system-usable contract: the timestamp of a defined threshold crossing at the gate node. This includes output stage strength, load, and probe loading effects.
Rule
Use one explicit threshold rule and keep it unchanged across channels and runs. Changing the threshold rule changes the timestamp and can look like skew/jitter drift.

Trigger & timebase contract (prevent false skew)

  • Same acquisition: measure all channels in one capture using a single timebase.
  • Single trigger reference: trigger from one defined source and keep it fixed across tests.
  • Matched path delay: use matched coax/probe paths or apply recorded channel deskew.
  • Fixed bandwidth mode: keep bandwidth limiting consistent to avoid threshold-crossing timestamp shifts.

Probe & loading control (prevent false jitter)

Why it matters
Probe capacitance and grounding alter edge slope and shift the moment the waveform crosses the chosen threshold, inflating measured delay and edge spread.
Control points
Keep probe type, attenuation, ground method, and loading consistent. Record probe mode as a required field.
Rule
If delay/jitter changes materially when the probe mode changes, treat the result as measurement-induced until proven otherwise.

Statistics: window, edges, and pass/fail

Window definition
Report edge spread using an explicit window: N edges within W ms (or W switching cycles). Do not report jitter without N and W.
Primary acceptance metric
Use a conservative acceptance metric: p-p (max–min) or P99.9. Keep one primary metric consistent across the page.
Pass/fail templates
tPLH ≤ X ns, tPHL ≤ Y ns · skew(max) ≤ Z ns · edge spread ≤ J ns over N edges within W.

Report fields (bring-up & production-ready)

  • Threshold rule: 50% crossing or fixed-V crossing (explicit).
  • Trigger source: which node defines time zero (explicit).
  • Coax/probe: matched length or deskew value recorded.
  • Probe mode: type/attenuation/bandwidth limit/ground method.
  • Conditions: VDD/VISO, temperature, load model (Cload or equivalent).
  • Statistics: N edges, W window, metric type (p-p / P99.9 / RMS).
Measurement architecture for delay skew jitter Scope timebase and trigger block feeding four measurement channels connected to DUT inputs and outputs, with matched coax and fixed probe loading highlighted, and a time interval measurement block producing delay, skew, and edge spread. Scope Timebase & Trigger Same timebase Single trigger DUT Driver chain CH1: IN_A CH2: IN_B CH3: OUT_A CH4: OUT_B Matched coax Deskew Probe C fixed Time Interval Measurement Delay Skew Spread Same threshold rule · N edges · W window
Diagram: A measurement contract that keeps timebase, trigger, path delay, and probe loading controlled and auditable.
H2-8 · Layout & Interface Hooks for Timing

Layout & Interface Hooks: Timing-Only Rules (No Layout “Grab Bag”)

1) Length mismatch → skew floor

What happens
Length mismatch introduces propagation-time mismatch and creates a hard lower bound on achievable skew, even if components are perfectly matched.
Rule
Keep A/B timing-critical routes mirrored and length-matched on the same reference environment. Record length deltas as part of the timing budget evidence.
Hook
Treat the route mismatch as an explicit skew term: skew ≥ Δt(route) (budgeted and verified).

2) Reference consistency → jitter control

What happens
Inconsistent reference conditions shift effective thresholds and create crossing-time variation, appearing as jitter in edge timestamps.
Rule
Keep reference conditions consistent across A/B. Avoid any return path that crosses between domains or through discontinuities that change local reference behavior.
Hook
If edge spread grows in the field, verify reference consistency before changing timing components.

3) Differential inputs → remove common-mode timing pollution

Why it helps (timing view)
Differential inputs reduce sensitivity of threshold-crossing timestamps to common-mode disturbances, tightening edge spread when routing symmetry is maintained.
Conditions
Keep the pair symmetric and preserve a consistent reference environment. A differential interface only helps timing when the pair is treated as a pair.
Hook
Prefer differential timing signals where tight jitter/skew is required and measurement evidence shows improvement under the same contract.

4) Relative placement: isolator ↔ driver symmetry

What happens
Placement asymmetry changes route length, reference behavior, and coupling environment, converting into skew and edge spread differences across channels.
Rules
Mirror A/B placement. Keep the isolator-to-driver path short and symmetric. Prevent any “cross return” between A/B regions.
Hook
Treat symmetry as a measurable requirement: record ΔL, skew(max), and edge spread under the same test contract.
Symmetric layout hooks for timing Left and right mirrored driver paths with length matching, shared reference, differential input pair routing, and a no cross return boundary highlighted. Shared reference No cross return Isolator Driver A Gate A Isolator Driver B Gate B Diff pair Pair symmetry Match length Match length ΔL → Δt (skew) Ref → jitter
Diagram: Mirror A/B paths, match lengths, preserve shared reference, use differential inputs correctly, and prevent cross returns to protect skew and jitter.

H2-9. Gate Network Interactions: Miller, -VGOFF, Split Rg, Two-Level Edges (CMTI View Only)

Gate-network knobs matter for CMTI because they change how easily dv/dt injection becomes a false Vgs/Vge rise, a ringing threshold crossing, or a transient state upset.

Thesis

Each knob targets a specific CMTI failure mechanism

Miller injection lifts the gate during turn-off. Ringing creates repeated threshold crossings. Reference shift steals noise margin under dv/dt / di/dt events.

Scope rule: only CMTI-relevant impact is described here (mechanism → when to use → acceptance).

Mechanism map

Symptom → knob shortcut (CMTI view)

  • False turn-on during OFF: prioritize Miller clamp and -VGOFF.
  • Spikes / ringing dominate events: prioritize split Rg and two-level edges.
  • Event width is very short (worst 10–50 ns): prioritize edge shaping and local clamping.

The goal is to reduce threshold crossings in the worst event segment defined in earlier chapters.

Active Miller clamp

Mechanism: pin gate to source during OFF to block Miller lift

Mechanism: a strong clamp path reduces the effective gate impedance during turn-off, limiting Vgs/Vge rise from Miller current.

When to use: dv/dt-correlated false turn-on signatures during OFF, especially when the SW node edge is the trigger.

When it will not save the design: large reference shift or local gate ringing that crosses thresholds at the device pins.

Gate OFF peak: Vgs_off_peak ≤ X V (or stays below Vth + margin).

False turn-on: 0 events in 10M edges.

OUT integrity: no glitches ≥ Y ns in OFF state.

-VGOFF

Mechanism: increase OFF-state noise margin against dv/dt injection

Mechanism: a negative OFF bias shifts the baseline, making the same injected Miller disturbance less likely to cross the turn-on threshold.

When to use: OFF-state false turn-on risk remains after basic loop control, or when strong dv/dt events repeatedly lift the gate.

Recommended range: -VGOFF = -X … -Y V (placeholder).

OFF margin: Vgs_off stays below the effective turn-on threshold under stress.

Events: false turn-on = 0; /FLT and UVLO do not glitch.

Note: excessive slowing or excessive bias can create other constraints; only the CMTI-facing margin effect is evaluated here.

Split Rg(on/off)

Mechanism: control dv/dt/di/dt and damping differently on ON and OFF edges

Mechanism: separate ON/OFF resistances allow independent control of edge sharpness and ringing energy, reducing injection and threshold chatter.

When to use: one edge is the CMTI trigger (typically the faster edge), or ringing is asymmetric between transitions.

Event-based dv/dt: worst-segment dV/dt ≤ X kV/µs.

Ringing: amplitude decays below X V within Y ns.

Victims: IN/OUT/FLT/UVLO show 0 false events in 10M edges.

Two-level edges

Mechanism: keep “worst 10–50 ns” under control while preserving switching intent

Mechanism: a fast initial transition handles switching intent, then a gentler segment reduces overshoot and ringing that commonly drive CMTI failures.

When to use: failures correlate with narrow spikes/ringing rather than the average slope; event profile needs shaping.

Spikes: overshoot/undershoot ≤ X V (fixture-defined).

Ringing duration: ≤ Y ns above threshold-sensitive amplitude.

Pulse integrity: OUT pulse-width deviation ≤ Z ns under stress.

Trade-off (scope-limited)

Over-slowing can create a different failure class

  • Loss/thermal: slower transitions increase switching loss and temperature stress.
  • Control sensitivity: slower edges can reduce timing margin or increase deadtime sensitivity.

This page only flags the direction of risk; detailed loss and control impacts belong to dedicated pages.

Decision shortcut

Pick the knob based on what crosses a threshold

  • Gate rises during OFF: clamp / -VGOFF first.
  • Waveform is spiky/ringing: split Rg / two-level first.
  • State upset or /FLT chatter: reduce injection amplitude and verify measurement reference integrity.

The acceptance criteria above convert “it feels stable” into event-count pass/fail.

Gate-network CMTI controls: split Rg, Miller path, clamp, and edge shaping A block diagram shows driver output feeding split Rg_on and Rg_off into the gate node. A Miller coupling path is indicated from SW node to gate, and an active clamp is placed between gate and source. Two small waveforms compare fast edge versus shaped edge. Gate Network Controls (CMTI View) Reduce false Vgs/Vge rise, ringing threshold crossings, and dv/dt-driven upsets Driver OUT stage Rg_on Rg_off Gate node Source Clamp SW dV/dt Miller Edge profiles Fast Shaped CMTI goal: prevent OFF-state gate rise and reduce spike/ringing-driven threshold crossings.
Diagram intent: split Rg and two-level shaping reduce the worst dv/dt/ringing segment; clamp and -VGOFF increase OFF-state robustness against Miller injection.

H2-10. Measurement & Validation: How to Prove CMTI on the Bench (and Avoid Fake Failures)

A valid CMTI result requires three aligned definitions: how dv/dt is applied, which victim signals are monitored, and how pass/fail is counted—without measurement-induced artifacts.

Thesis

Prove CMTI with a reproducible workflow, not a screenshot

A bench validation must be repeatable and reportable: dv/dt method victim signals event counters probe integrity

The primary failure mode in CMTI validation is a “fake fail” created by reference choice or probe grounding.

Baseline trio

Three things that must be defined up front

  • dv/dt application: real half-bridge switching or a controlled injection fixture.
  • Victim set: IN, OUT, /FLT, UVLO (and /RDY if used).
  • Decision metrics: false triggers, missing pulses, fault chatter, resets/lockups.

Without these definitions, “passes” and “fails” are not comparable across labs or iterations.

Method A

Real half-bridge switching (most realistic)

  • Strength: includes real spikes, ringing, and reference shift.
  • Risk: more variables; measurement setup must be disciplined.

Best when the goal is system-representative immunity verification.

Method B

Controlled injection fixture (most controllable)

  • Strength: parameter scanning is easier and more repeatable.
  • Risk: may not reproduce the full return-path and ringing environment.

Best when the goal is comparative screening and sensitivity mapping.

Measurement points

Victim signals must be measured with a defined reference

  • OUT: measure at the gate with a Kelvin-defined reference to driver ground.
  • IN: define logic threshold and count false transitions.
  • /FLT: count only pulses wider than the defined glitch width.
  • UVLO: monitor rail behavior and state transitions under dv/dt stress.

Reference ambiguity is the fastest route to false conclusions.

Probe traps

Common measurement artifacts that create fake failures

  • Ground lead loop: adds inductive pickup → fake glitches.
  • Wrong reference point: uses power ground as reference → fake OUT chatter.
  • Bandwidth limits: hides spikes → fake pass; or distorts edges → fake fail.
  • Diff-probe CM range: saturation/clipping under CM steps → fake events.

A correct result requires the probe chain to survive the same CM environment as the DUT.

Sweep & logging

Make results explainable by sweeping controlled axes

  • dV/dt axis: evaluate the worst-segment dV/dt defined by this page.
  • CM step axis: sweep step amplitude (fixture-defined).
  • Edge count: log events over 10M switching edges.

Event-count logging prevents single-shot screenshots from driving design decisions.

Acceptance template

Report-ready pass/fail placeholders (X/Y/N/Z/M)

dV/dt stress: dV/dt ≥ X kV/µs (worst sub-interval definition).

CM step: ΔVCM ≥ Y V.

False triggers: ≤ N per 10M edges (target: 0).

/FLT integrity: no pulses with width ≥ Y ns.

OUT integrity: pulse-width deviation ≤ Z ns under stress.

State integrity: no UVLO/reset/lockup events in the stress run.

This template is designed to be copied into a validation report without adding new scope beyond CMTI.

CMTI bench validation rig: DUT, victim signals, Kelvin reference, and forbidden ground-clip points A test-rig block diagram includes a half-bridge DUT, gate driver, isolated bias, and measurement points for IN, OUT, FLT, and UVLO. A Kelvin reference point is highlighted. Forbidden ground-clip locations near the switching loop are marked as NO CLIP. Bench Validation Rig (CMTI) Define dv/dt method, victims, pass/fail metrics, and eliminate probe-induced artifacts DUT Half-Bridge Real switching dv/dt SW dV/dt Gate Driver Iso Bias Supply rails IN OUT /FLT UVLO Kelvin REF Diff probe CM range Current probe NO CLIP NO CLIP Rule: measure OUT and victim signals with Kelvin-defined reference; avoid ground clips near the switching loop to prevent fake glitches.
Diagram intent: a CMTI bench setup must define victim signals and Kelvin reference points, and must mark forbidden ground-clip locations that commonly create fake failures.
H2-11 · IC Selection Logic

IC Selection Logic: Back-Calculate Timing Needs from PWM Targets

Inputs (fill-in, then back-calc)

Use system requirements to compute timing limits first. Then select gate drivers whose guaranteed matching/skew/spread specifications meet those limits under the intended corners.

  • Fsw: switching frequency (Hz) → Tsw = 1/Fsw
  • Nph: number of phases / legs (interleaving)
  • t_min_pulse: minimum commanded pulse width (ns)
  • ΔDT_allow: allowable deadtime error (ns)
  • Corner set: VDD/VISO min/max, Temp min/max, consistent load & probe contract

Back-calc templates (selection math, not control theory)

Skew → phase
Convert timing skew to phase error: Δφ(°) = 360° · (skew / Tsw). Start from an allowed phase error budget, then compute: skew_allow = (Δφ_budget/360) · Tsw.
Min-pulse fidelity
Reserve a positive effective time-LSB: t_LSB_effective = t_min_pulse − (skew_wc + spread_wc + meas_unc). Require t_LSB_effective > 0 at the worst-case corner.
Deadtime margin
Tie allowable deadtime error to directional mismatch: ΔDT_effective_wc ≈ Δt_edge_mismatch_wc + spread_margin, so enforce: Δt_edge_mismatch_wc ≤ ΔDT_allow − spread_margin.
Must-check datasheet fields (guaranteed, with conditions): channel-to-channel delay matching / skew(max), tPLH/tPHL(max), pulse width distortion, prop delay vs V/T, min pulse width

Decision rules (when “matched channels” is mandatory)

  • Matched channels required when skew_allow is in the ns range (high Fsw, high Nph, tight Δφ_budget).
  • Matched channels required when t_min_pulse is close to (skew + spread) and narrow pulses lose fidelity.
  • Directional matching required when ΔDT_allow is small and HS/LS (or A/B) edge mismatch consumes deadtime margin.
  • Absolute delay can be large if it is calibratable, but relative error (skew/spread) must still meet the computed limits.

Example part numbers (PN) by selection outcome

The list below provides concrete, commonly-used PNs for timing-driven selection. Package/grade suffixes depend on safety, creepage, and automotive requirements.

A) Matched channels required (tight skew / matched delays)
  • TI LMG1210 (half-bridge MOSFET/GaN driver; HS↔LS matching-focused)
  • Infineon 2EDN7524F (dual-channel low-side driver; delay matching-focused)
  • onsemi NCP51561 (isolated dual-channel driver; matched delays-focused)
  • TI UCC21520DW (isolated dual-channel driver; propagation delay matching-focused)
Use when skew_allow is ns-level
B) Low skew priority (absolute delay can be calibrated)
  • TI UCC21750DW / UCC21750DWQ1 (single-channel isolated driver; bounded part skew specified)
  • Analog Devices ADuM4136 (single-channel isolated driver; skew definitions and timing parameters provided in datasheet)
  • Analog Devices ADuM4121 (single-channel isolated driver; channel/part skew terminology defined in datasheet)
Prefer for multi-board consistency (part-to-part behavior bounded)
C) Low spread (edge timing “tightness”) priority
  • TI UCC21520DW (dual-channel isolation+drive; pulse width distortion explicitly characterized)
  • Infineon 2EDN7524F (dual-channel low-side; tight matching enables predictable relative timing)
  • Skyworks / Silicon Labs Si8239x (dual isolated drivers; evaluate skew/variation vs temperature in the datasheet)
Use when min-pulse fidelity is at risk

Selection workflow (executable)

  1. Compute skew_allow from Δφ_budget and Tsw; compute the min-pulse window with t_LSB_effective.
  2. Decide if matched channels are mandatory (ns-level skew_allow, narrow t_min_pulse, or small ΔDT_allow).
  3. Filter by guaranteed max fields and their test conditions (VDD, load, temperature).
  4. Verify on hardware using the measurement contract (same thresholds, trigger, timebase, deskew, and N/W).
Decision tree: from PWM targets to timing requirements and example PNs A left-to-right selection flow: input boxes for Fsw, phases, min pulse, and allowed deadtime error feed back-calculation boxes for skew_allow, spread_allow, and mismatch_allow. Decision diamonds route to three output buckets with example part numbers. Inputs Fsw Phases (Nph) Min pulse ΔDT allow Corners VDD / Temp Load / Contract Back-calc skew_allow (Δφ/360)·Tsw spread_allow t_min_pulse − … t_LSB_effective > 0 mismatch_allow ΔDT_allow − margin Matched needed? Delay cal? A) Matched channels LMG1210 2EDN7524F NCP51561 B) Low skew (delay cal) UCC21750DW ADuM4136 C) Low spread (tight edge) UCC21520DW Si8239x
Diagram: System inputs back-calculate timing limits, then route to matched-channel vs low-skew vs low-spread driver categories with concrete PN examples.

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H2-12 · FAQs

FAQs: Field Debug & Acceptance for Delay / Skew / Jitter

These FAQs lock down debug and acceptance definitions for timing only. Each answer provides a fastest check path and a measurable pass/fail template.

Datasheet delay looks fine, but phase current sharing is bad—skew or deadtime mismatch?
Likely cause:Relative timing error dominates: either channel-to-channel skew creates phase error, or directional HS/LS delay mismatch shifts effective deadtime.
Quick check:Measure tPLH/tPHL per channel under one contract, then compute Δφ = 360·skew/Tsw and ΔDT_effective_wc from worst-case edge placement.
Fix:Lock threshold/trigger/deskew; length-match inputs; enforce HS/LS symmetry; increase deadtime margin using worst-case mismatch+spread or select a matched-channel driver/driver+isolator combo.
Pass criteria:skew(max) ≤ X ns; Δφ ≤ Y° @ Fsw; DT_effective_wc ≥ Z ns; spread(metric) ≤ J ns over N edges within W; corners: VDD=Vmin..Vmax, Temp=Tmin..Tmax.
One leg runs hotter with same PWM—first suspect channel mismatch or layout-induced skew?
Likely cause:A relative edge offset (skew or directional mismatch) causes phase/current imbalance; layout length/reference mismatch is a common amplifier of “matched” parts.
Quick check:Swap channels (A↔B) or swap probe/cable paths; if the measured skew follows the channel, suspect device mismatch; if it stays with the leg, suspect routing/reference asymmetry.
Fix:Match input trace length and reference; co-locate timing-critical paths; enforce symmetric return; use a driver with guaranteed inter-channel skew(max) if required by the computed skew_allow.
Pass criteria:skew(max) ≤ X ns across Tmin..Tmax; ΔTemp(leg-to-leg) ≤ Y °C over Z minutes at defined load; swap-test delta ≤ S ns (measurement chain control).
Jitter appears only at high dv/dt—input threshold noise or reference bounce?
Likely cause:Edge timing noise is entering through input threshold sensitivity or reference instability, increasing edge spread only under high switching stress.
Quick check:Compare spread at IN-pin timestamp vs OUT/gate-threshold timestamp; correlate spread with dv/dt and VDD ripple; repeat with differential input (if available) under the same contract.
Fix:Stabilize the timing reference (return + local decoupling); prefer differential inputs; minimize measurement ground loops; keep probe loading consistent and documented.
Pass criteria:spread(P99.9 or p-p) ≤ X ns at dv/dt=Y kV/µs; VDD ripple ≤ Z mVpp; N edges ≥ N0 within W; same threshold rule and deskew record.
Skew is small at room temp, large at hot—PVT drift or thermal gradient?
Likely cause:Channel-to-channel drift is driven by unequal temperature exposure (thermal gradient) or unequal PVT sensitivity between channels/paths.
Quick check:Thermal soak and log skew vs temperature; repeat after swapping channels or swapping measurement paths to separate device drift from placement gradient.
Fix:Improve thermal symmetry and coupling; select devices with guaranteed skew(max) across temperature; avoid asymmetric routing that turns tempco into skew.
Pass criteria:skew(max) ≤ X ns over Tmin..Tmax; |d(skew)/dT| ≤ Y ps/°C; N edges per point ≥ N0; VDD fixed or swept per policy.
Rising edges match, falling edges don’t—tPLH vs tPHL asymmetry?
Likely cause:Directional delay asymmetry: tPLH and tPHL do not match equally across channels, creating edge-dependent mismatch and pulse-width distortion.
Quick check:Measure ΔtPLH and ΔtPHL separately under identical threshold/load; compute pulse-width distortion and the implied deadtime shift on each edge.
Fix:Apply edge-specific margin (rising vs falling); choose a driver with tighter directional matching specs; avoid mixing channels with different loading paths.
Pass criteria:|ΔtPLH| ≤ X ns; |ΔtPHL| ≤ Y ns; PWD ≤ Z ns; spread(metric) ≤ J ns over N edges; corners covered per policy.
Measured skew differs between labs—trigger/reference definition mismatch?
Likely cause:Measurement contract mismatch: threshold rule, trigger source, timebase, channel deskew, or cable/probe path length differences.
Quick check:Re-run using a single contract: identical threshold definition, same trigger reference, same scope timebase, recorded deskew, matched coax/probe paths.
Fix:Publish a one-page timing measurement contract; require it for all reports; prohibit “threshold swapping” or trigger changes between datasets.
Pass criteria:Inter-lab Δskew_report ≤ X ns under the same contract; N edges ≥ N0; W fixed; deskew record present; corners declared.
Delay is large but stable—can calibration remove it safely? what must remain matched?
Likely cause:A constant pipeline delay exists that is largely calibratable, while relative timing (skew/spread) still sets phase and deadtime safety.
Quick check:Sweep VDD and temperature to confirm delay drift is bounded; verify skew(max) and spread(metric) meet computed limits at corners.
Fix:Calibrate only the absolute delay offset; keep channels matched by design (routing/reference symmetry) and by selection (guaranteed skew(max)).
Pass criteria:|Δdelay_drift| ≤ X ns over corners; skew(max) ≤ Y ns; spread(metric) ≤ Z ns over N edges; calibration residual ≤ R ns.
Differential input improves EMI but jitter stays—where else can timing noise enter?
Likely cause:Timing noise is not dominated by input common-mode; it can enter through supply/reference instability, output threshold timing sensitivity, or measurement-chain loading.
Quick check:Correlate spread with VDD ripple and reference conditions; verify the same probe loading and deskew; compare IN-pin timestamp vs OUT/gate timestamp.
Fix:Strengthen local decoupling and reference integrity; keep measurement loading controlled; enforce a stable timing reference path and consistent threshold rules.
Pass criteria:spread(metric) ≤ X ns with VDD ripple ≤ Y mVpp; N edges ≥ N0 in W; same threshold/trigger/deskew; corners stated.
Multichannel driver claims “matched,” yet in system it isn’t—what wiring/measurement mistake is most common?
Likely cause:External asymmetry dominates: unequal input trace length, inconsistent reference/return, missing channel deskew, or unmatched coax/probe path delays.
Quick check:Swap A/B signal routing (or swap probe/cable paths) and re-measure; if skew moves, the measurement/wiring chain is the culprit, not the silicon claim.
Fix:Length-match and reference-match the timing paths; co-locate isolator/driver for symmetric delay; document and apply deskew before reporting skew(max).
Pass criteria:Swap-test sensitivity ≤ X ns; final skew(max) ≤ Y ns under declared load/probe; N edges ≥ N0; W fixed; corners covered.
Deadtime set correctly but shoot-through still happens—effective deadtime shifted by propagation mismatch?
Likely cause:Effective deadtime is reduced by worst-case directional mismatch (tPLH/tPHL) plus edge spread, even when the commanded deadtime looks correct.
Quick check:Compute DT_effective_wc = DT_cmd − Δt_edge_mismatch_wc − spread_margin; measure under VDD/Temp corners using one contract.
Fix:Increase DT_cmd by the measured worst-case terms; improve HS/LS symmetry; select a driver with tighter guaranteed mismatch and skew(max) if DT_allow is small.
Pass criteria:DT_effective_wc ≥ X ns across corners; Δt_edge_mismatch_wc ≤ Y ns; spread(metric) ≤ Z ns; N edges ≥ N0; W fixed.
Only high-side edges drift—bootstrap domain bias variation or level-shift path? (timing consequence only)
Likely cause:High-side timing is more sensitive to its local domain conditions, shifting propagation delay vs duty cycle/operating corner through the high-side path.
Quick check:Sweep duty cycle and temperature while logging HS delay; compare HS drift to LS stability under the same measurement contract.
Fix:Choose a high-side path with bounded delay drift; tighten domain stability; constrain the operating window (Dmin..Dmax) if required and include it in acceptance.
Pass criteria:HS delay drift ≤ X ns over D=Dmin..Dmax and Temp=Tmin..Tmax; HS-LS drift delta ≤ Y ns; N edges ≥ N0; W fixed.
Production test passes delay but field fails—what additional skew/jitter screening is missing?
Likely cause:Production screens only absolute delay at a single condition; missing skew(max), edge spread, and corner coverage allows field failures driven by relative timing uncertainty.
Quick check:Audit the production test: confirm whether skew(max) and spread(metric) are measured, whether N/W is sufficient, and whether VDD/Temp corners are represented.
Fix:Add skew(max) and spread(metric) to the reduced production set; enforce a fixed contract and explicit corner policy; add a stop-ship rule when thresholds are exceeded.
Pass criteria:skew(max) ≤ X ns; spread(metric) ≤ Y ns; N edges ≥ N0 within W; corners include VDD min/max and Temp Tmin/Tmax per policy; stop-ship triggered at ≥1 fail.
Metric: delay (tPLH/tPHL) Metric: skew(max) Metric: spread (p-p / P99.9) Counters: N edges / W window Corners: VDD / Temp / Load

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