Differential / Single-Ended Inputs for Gate Drivers
Definition & Scope: Differential vs Single-Ended Inputs (for Gate Drivers)
Differential and single-ended inputs define how a gate driver interprets PWM/EN/SD control signals under high dv/dt and strong EMI.
The success criteria are simple and measurable: no false turn-on/off, no missing pulses, and pass/fail validation that is repeatable across benches, cabinets, and test labs.
What “input” means on a gate driver
“Input” refers to the driver’s logic/control pins that command switching behavior, such as: PWM (HI/LI), EN (enable), SD (shutdown), IN+/IN− (differential), and similar control channels.
This page focuses on the control-input signal path (controller → isolator (optional) → driver input), not the gate output stage or power-loop switching node.
Engineering definitions (usable on real boards)
One signal conductor is interpreted against a reference (logic ground / COM / local return). The receiver decides with VIH/VIL thresholds (and sometimes hysteresis).
- Strength: simplest wiring, fewer pins, common in short on-board links.
- Main risk: reference shift (ground bounce) changes the effective threshold margin.
- Typical failure signature: clean-looking logic level, but sporadic toggles during switching events.
Two conductors (P/N) are interpreted by their difference: VOD = VIN+ − VIN−, while staying within the receiver’s common-mode range (VCM).
- Strength: rejects common-mode noise when the pair is symmetric and well-referenced.
- Main risk: any asymmetry converts common-mode noise into differential error.
- Typical failure signature: “differential used” yet glitches remain (layout/cable asymmetry).
Key take-away: differential is not “magic immunity.” It is a system: pair symmetry + reference continuity + termination discipline.
Scope boundaries (to prevent content overlap)
This page owns “input interpretation and noise survival.” Related topics are intentionally scoped to their dedicated pages:
- CMTI / dv/dt immunity: this page only points out where common-mode transients enter inputs; the definition/test method belongs to CMTI / dv/dt Immunity.
- Propagation delay & matching: this page notes that filtering/receiver choice can distort pulse width; full delay/skew budgeting belongs to Propagation Delay & Matching.
- Deadtime/interlock: this page focuses on “input glitches” that break the interlock assumption; deadtime design belongs to Deadtime & Shoot-Through Interlock.
Three field symptoms this page targets
- False turn-on/off: unexpected switching during high dv/dt transitions (often “only under load”).
- Missing pulses: short PWM commands disappear or shrink after wiring/filters/isolators.
- Non-repeatable validation: passes on bench, fails in cabinet/vehicle, or differs between labs due to measurement reference issues.
Figure 1 — Control-input signal chain. The key distinction is how the receiver “decides” logic state: single-ended uses a reference; differential uses the pair difference and survives common-mode noise only when symmetry is preserved.
When Inputs Fail: Real Noise Paths That Create False Turn-On/Off
Input failures are almost never “random.” They follow a small set of repeatable noise paths that can be classified and quickly discriminated.
The purpose of this chapter is to map field symptoms to physical injection mechanisms, so debugging starts with the most discriminating measurement, not trial-and-error changes.
A practical taxonomy: 3 injection mechanisms + 2 amplifiers
High dv/dt nodes couple through parasitic capacitance into the input conductors, creating narrow spikes that can cross thresholds.
- Signature: glitches line up with switching edges (phase-locked to dv/dt).
- Fast discriminator: change dv/dt (gate slew) and watch glitch amplitude scale immediately.
- Common trap: probe ground lead creates or hides the spike (measurement artifact).
Large current transitions induce voltage in any nearby loop. If the input signal and its return are not tightly coupled, the loop behaves like an antenna.
- Signature: worst at high load current edges; sensitive to routing/loop geometry.
- Fast discriminator: temporarily shrink loop area (short twisted pair / closer return) and see rapid improvement.
- Common trap: focusing on logic levels instead of loop return integrity.
Shared impedance in the reference path shifts the receiver’s effective VIH/VIL. This is the most common root cause for single-ended inputs that “look fine.”
- Signature: behavior changes with reference point (local vs remote ground).
- Fast discriminator: measure input relative to the driver’s local reference (not chassis or controller ground).
- Common trap: assuming “ground is ground” across partitions.
- Asymmetry (CM→DM conversion): differential pairs reject common-mode only if P/N are matched (routing, impedance, return environment).
- Threshold margin too small: slow edges, weak hysteresis, or tight VIH/VIL spacing allow “threshold chatter,” turning noise into extra toggles.
These two amplifiers explain why a “differential system” can still fail: the noise path exists, and the receiver is forced into an ambiguous decision region.
Failure modes as symptom → likely path → fastest discriminator
Symptom: false turn-on during high-side switching events.
Likely path: capacitive dv/dt coupling + threshold margin too small.
Fast discriminator: correlate glitch rate with dv/dt; reduce edge rate and check if toggles drop immediately.
Symptom: short PWM commands disappear after wiring/filters/isolator.
Likely path: receiver threshold + edge conditioning (pulse-width distortion) rather than EMI alone.
Fast discriminator: measure minimum pulse width at driver pins and compare to the controller output at the source.
Symptom: differential inputs used, but false toggles persist.
Likely path: CM→DM conversion from asymmetry (routing, connector, cable, shield bond).
Fast discriminator: swap P/N at the receiver (if allowed) or compare P and N waveforms to detect mismatch-induced differential spikes.
Symptom: passes on bench, fails in cabinet/vehicle or varies by lab.
Likely path: reference/ground bounce + measurement reference differences.
Fast discriminator: re-measure at the driver reference node with proper probing; compare with chassis-ground measurements.
Figure 2 — Three dominant injection mechanisms. Differential inputs reject common-mode noise only when pair symmetry prevents CM→DM conversion. Single-ended inputs are most vulnerable to reference/ground-bounce shifts that reduce effective VIH/VIL margin.
Electrical Models: Thresholds, Hysteresis, Common-Mode Range, and Input Impedance
Input robustness is determined by how the receiver decides logic state: thresholds, hysteresis, common-mode limits, and the input loading seen by the source.
Noise does not need to “look big” to cause failure; it only needs to push the receiver across its decision boundary (or force the receiver into a non-linear region).
Single-ended input model (SE)
A single-ended receiver compares the input pin against a local reference and decides using VIH/VIL (often with hysteresis). Over-voltage events can trigger input clamps, and even small input currents can reshape edges when the source is weak.
Practical interpretation: “logic high” is not a nominal voltage; it is a minimum margin above VIH at the driver pin relative to the driver’s local reference.
Differential input model (DIFF)
A differential receiver decides from VOD = VP − VN, while both pins must remain inside the receiver’s common-mode range (VCM). Input impedance and termination determine how reflections and asymmetry create unwanted differential error.
Practical interpretation: differential helps only when common-mode noise remains common-mode. Any asymmetry can convert it into differential spikes.
Eight datasheet fields that must be captured
- VIH / VIL requirements: defines the single-ended decision boundaries.
- Hysteresis (HYS): determines whether threshold-region noise becomes extra toggles.
- Input leakage / IIH / IIL: critical for weak drive, open-drain sources, and RC edges.
- Max input voltage + clamp behavior: indicates when over-voltage injects current or reshapes edges.
- Input capacitance (CIN): sets edge-rate loading and pulse-width distortion risk.
- VOD threshold (DIFF): minimum differential amplitude required to be interpreted correctly.
- VCM common-mode range (DIFF): hard boundary; outside this range, a receiver may saturate or misinterpret.
- Differential input impedance / termination (DIFF): dictates reflection behavior and whether external termination is required.
Engineering spec language (formula placeholders)
The following expressions define pass/fail margins without requiring a large table. Thresholds are evaluated at the driver pins.
SE high margin: Margin_H = VHIGH_min(at driver) − VIH_req ≥ X_V
SE low margin: Margin_L = VIL_req − VLOW_max(at driver) ≥ X_V
Chatter risk: Noise_pkpk(at driver) ≤ (Hysteresis − X_V)
DIFF VOD margin: Margin_OD = VOD_min(at driver) − VOD_req ≥ X_mV
DIFF VCM compliance: VCM_min + Y ≤ VCM(at driver) ≤ VCM_max − Y
Reflection risk: |ΔV_reflection| ≤ X_mV (symmetric on VP/VN)
These placeholders are meant to be populated with project-specific targets (X/Y) and verified using the validation playbook later in this page.
Pass vs risk (decision-boundary checklist)
- Pass: margins are positive (≥ X), differential common-mode stays within VCM limits, and the waveform does not repeatedly traverse the threshold region.
- Risk: margins approach zero, VCM is near a boundary, hysteresis is insufficient for observed noise, or clamp currents reshape edges and shrink pulse width.
Figure 3 — Decision boundaries. SE depends on VIH/VIL relative to a local reference and benefits from hysteresis. DIFF depends on VOD while remaining inside VCM limits; impedance/termination controls reflection and asymmetry.
Noise Immunity Principles: Why Differential Helps—and When It Doesn’t
Differential is not “automatic immunity.” It improves robustness only when symmetry, reference continuity, and termination discipline are maintained.
The engineering goal is not to eliminate noise completely, but to keep noise as common-mode so it does not become a differential decision error.
Why differential usually helps
- Common-mode rejection: noise coupled equally onto VP and VN largely cancels in VOD.
- Decision variable is differential: the receiver triggers on VOD crossing a threshold rather than absolute voltage level.
- Pair coupling suppresses differential pickup: tightly coupled pairs tend to pick up external fields as common-mode.
These benefits require the pair to experience similar environments and similar source/termination conditions.
When differential fails (how CM becomes DM)
- Symmetry breaks: one conductor is closer to a noise source, routed differently, or sees different return conditions.
- Reference discontinuity: plane splits / slots alter field lines, making VP and VN experience different coupling.
- Pair mismatch: impedance or length mismatch creates unequal reflections, producing differential spikes.
- VCM near boundaries: common-mode excursions push the receiver into saturation/non-linear behavior.
The failure mechanism is consistent: common-mode disturbances are converted into differential error that crosses VOD_th.
Differential wins / Differential fails (fast decision cards)
- Pair symmetry: equal length/spacing and consistent routing geometry.
- Continuous reference: both lines share the same reference environment; no plane splits under the pair.
- Controlled termination: reflections are limited and balanced on VP/VN.
- Common-mode stays common-mode: external fields couple similarly into both conductors.
- One line detours: different proximity to noisy nodes or different return path.
- Crossing a split/slot: discontinuous reference makes coupling unequal.
- Unbalanced reflections: no termination or mismatched impedances creates VP/VN asymmetry.
- Receiver pushed to edges: VCM excursions approach the common-mode boundary.
Design principle: preserve symmetry so noise remains common-mode; avoid structures that manufacture differential error.
Figure 4 — Differential works when the pair remains symmetric over a continuous reference environment. Splits, detours, and imbalance convert common-mode disturbances into differential error that can cross VOD_th.
Direct Wiring from Digital Isolators: Output Types, Levels, Defaults, and Termination
The isolator-to-driver link must define a deterministic logic state under noise and power transients while preserving pulse integrity.
Robustness depends on four checks: output type (PP/OD/DIFF), level/threshold alignment, default/power-off behavior, and termination or damping appropriate to the interconnect.
Isolator output types (PP / OD / DIFF) — what changes electrically
- Push-pull (PP): strong drive and fast edges; primary risk is overshoot/ringing causing threshold re-crossing.
- Open-drain (OD): requires external pull-up; primary risk is slow rise eating minimum pulse width and undefined state when floating.
- Differential output (DIFF): decision is based on VOD; primary risk is CM→DM conversion from asymmetry or missing termination.
Levels & thresholds: alignment rules (driver pin is the reference)
Compatibility is confirmed by comparing isolator output guarantees to driver input requirements at the driver pins (not at the controller, and not at the isolator package).
- SE link: verify VOH/VOL (after interconnect) meets VIH/VIL with margin ≥ X_V.
- DIFF link: verify VOD(min) meets VOD_th with margin ≥ X_mV and VCM stays inside VCM limits.
- Edge integrity: verify rise/fall times do not collapse minimum on/off pulse width (limit: X_ns or X_%).
Defaults & power-off behavior: avoid floating and back-powering
- No floating inputs: every input must have a defined state during normal operation and during any single-rail power loss.
- Failsafe must be measurable: when “off,” the input voltage must settle into a stable band (X to Y) with no threshold chatter.
- Back-power risk: external pull-ups or strong outputs must not inject current through input clamps beyond X_mA.
- Isolator output state when its VDD is off: Hi-Z / forced-high / forced-low (must be known).
- Driver input behavior when its VDD is off: clamp present / leakage (must be known).
- External pulls (if used): confirm default state and rise-time target simultaneously.
Termination & damping: when it is mandatory
- Board-to-board cable: treat as transmission line; use termination for DIFF if no internal termination is present.
- Short on-board: prefer series damping (RS) for PP/SE; full termination is rarely the first step.
- High dv/dt same board: geometry and reference continuity come first; termination cannot compensate for split-plane routing.
Practical trigger: if ringing causes multiple crossings of VIH/VIL (SE) or VOD_th (DIFF), damping/termination is required.
Connection playbook: three scenarios (3 hard rules + 1 acceptance each)
- Prefer PP: OD requires a deliberate pull-up sized to meet rise-time ≤ X_ns and noise margin ≥ X_V.
- Use RS damping: place a series resistor (RS) to limit ringing and overshoot at the receiver.
- Define default state: no input may float during reset, brownout, or isolator power cycling.
- At driver pin: overshoot/ringing settles within X cycles and does not re-cross the decision region (X/Y placeholders).
- Prefer DIFF: maintain pair symmetry through connector and cable; avoid “single-line detours.”
- Terminate DIFF: if the receiver lacks internal termination, add termination at the receiver (RTERM placeholder).
- Control defaults: failsafe behavior must remain deterministic with cable connected and disconnected.
- At receiver: VOD margin ≥ X_mV, VCM within limits, and false toggles = 0 over Y minutes (placeholders).
- Route with return: SE must keep the return path adjacent; DIFF must stay tightly coupled on a continuous reference.
- No split crossing: do not cross plane gaps/slots; if unavoidable, redesign the partition or provide a continuous reference strategy.
- Damping after geometry: add RS/RTERM only after geometry and reference continuity are correct.
- Under worst-case dv/dt events: input state remains stable with 0 false toggles over X events (placeholders).
Figure 5 — Interconnect essentials. PP/SE typically needs RS damping; OD/SE requires RPU to define both timing and default state; DIFF links require symmetry and termination (if not internally provided).
Layout & Routing Rules: Reference, Return, Pair Geometry, and Shielding
Inputs survive high dv/dt when routing preserves reference continuity and prevents common-mode noise from becoming a decision error.
Single-ended routing is dominated by return path integrity. Differential routing is dominated by pair symmetry and continuous reference environment. Shielding is handled here only as an input-side principle.
Do / Don’t rules (field-executable)
- Route signal + return as a pair with a continuous reference nearby.
- Measure and reason about the signal relative to driver REF (not chassis or remote ground).
- Keep the input path away from high dv/dt copper and fast power-loop edges.
- Do not cross plane gaps/slots; it forces return currents to detour and creates ground bounce.
- Do not share long impedance with power returns; threshold margin collapses under di/dt.
- Do not rely on “high logic level” alone; reference shifts dominate failures.
- At driver pin: reference shift and glitch amplitude stay below X_mV; no repeated threshold crossings over Y events (placeholders).
- Keep the pair tightly coupled and symmetric (same layer, same environment).
- Maintain a continuous reference under both conductors; avoid any split under the pair.
- Terminate or damp reflections when needed, and keep it balanced on VP/VN.
- Do not let one conductor detour or cross a split; it converts CM noise into DM error.
- Do not route VP and VN near different aggressors; asymmetry manufactures VOD spikes.
- Do not ignore VCM boundaries; common-mode excursions near edges reduce receiver linearity.
- At receiver: VP/VN waveforms remain symmetric within X, VOD margin ≥ X_mV, and VCM remains inside limits (placeholders).
- Bond shield strategy to preserve return continuity and pair symmetry at the receiver.
- Ensure shield connection does not force return currents into large detours.
- Keep shield termination consistent between endpoints to prevent asymmetry.
- Do not leave shield floating near the receiver; it can behave as an antenna.
- Do not connect shield in a way that breaks VP/VN symmetry across connectors.
- Do not use shielding as a substitute for routing over a continuous reference.
- With shield strategy applied: glitch counts remain stable and do not increase with cabinet/door state over Y minutes (placeholders).
Figure 6 — Geometry dominates input robustness. Keep reference continuous and preserve pair symmetry. Split crossings, detours, return loops, and floating shields convert common-mode disturbances into decision errors.
Timing Side Effects: Delay, Pulse-Width Distortion, and Edge Conditioning
Input conditioning changes the decision instant and can silently reduce effective pulse width at the driver input.
This section stays strictly at the input-link level: RC networks, pull-ups, and receiver thresholds can introduce fixed delay, pulse-width distortion, and threshold-region chatter. Control-loop bandwidth and multi-channel skew are out of scope.
Engineering definitions (test at the driver pin)
- Delay (tPD): time shift from source edge to receiver decision point (fixed offset).
- Pulse-width distortion (ΔPW): difference between source PW and effective PW above the decision region.
- Edge conditioning: dv/dt reduction that increases time spent near the threshold region and raises sensitivity to noise.
Three common pitfalls (symptom → fastest check → fix direction)
Short pulses get swallowed (effective PW collapses at higher frequency or low duty).
- At driver pin: confirm PW_eff(above threshold) ≥ X_ns under worst-case rise time and loading.
- Reduce RC time constant, strengthen pull-up/output drive, or move filtering upstream with verified PW margin.
Slow rise causes threshold chatter (noise creates multiple crossings near VIH/VIL or VOD_th).
- Measure dwell time near threshold: t_th_region ≤ X_ns, and verify no multiple toggles per edge.
- Restore edge rate with RS damping (not over-filtering), improve reference/return, add hysteresis where available, or use DIFF correctly.
Isolator output saturates and recovers after EFT/ESD or strong CM events.
- After disturbance: verify signal integrity recovers within Y_us and false toggles remain 0 over the recovery window.
- Limit injected current (RS/clamps), prevent floating states, and avoid protection choices that load the line excessively.
Acceptance criteria (placeholders for review & test)
- Minimum effective pulse width: PW_eff(above threshold) ≥ X_ns at the driver input.
- Pulse-width distortion limit: |ΔPW| ≤ X_ns (or ≤ X_% for duty-based criteria).
- Post-disturb recovery: recovery ≤ Y_us with false toggles = 0 over Y-window.
Measurements are taken at the driver input pins because interconnect loading and reference behavior define the true decision waveform.
Figure 7 — RC/loading can shift threshold crossing (tPD) and reduce the effective pulse width (PW_eff). If PW_eff falls below the minimum requirement, short pulses are swallowed.
Input Hardening: Filtering, Clamps, and Safe-State Design
Input protection must reduce injected noise without converting common-mode disturbance into decision errors or killing pulse width.
This section focuses on three hardening tools at the input chain: series R, RC filtering, and clamps. Safe-state behavior is enforced so that open-cable, floating nodes, or isolator power loss default to OFF.
The “three-piece kit”: what each tool protects — and what it can break
- Series R (RS): damps ringing and limits injected current; can be tuned without large PW loss.
- RC filter: removes high-frequency glitches; can introduce ΔPW and swallow short pulses if over-sized.
- Clamp: limits over-voltage and injection; adds capacitance and may trigger recovery effects if misapplied.
Protect what matters: threat → preferred tool → acceptance (no tables)
ESD/EFT injection at connector or cable that couples into input lines.
- Clamp close to entry + RS to limit injected current into the isolator/receiver.
- Injected current into receiver stays below X_mA; false toggles = 0 over Y events (placeholders).
High-frequency glitches that are shorter than the system’s meaningful pulse width.
- Light RC or controlled edge conditioning, validated against minimum PW requirements.
- PW_eff(above threshold) ≥ X_ns and |ΔPW| ≤ X_ns under worst-case conditions (placeholders).
Ringing and reflections that cross the decision region multiple times.
- RS damping (SE) or balanced termination (DIFF) at the receiver if internal termination is absent.
- Decision re-crossings ≤ X per edge; stable logic with 0 spurious toggles over Y minutes (placeholders).
Open cable / floating node / isolator power loss causing undefined states.
- Deterministic pulls or verified failsafe states so the driver input defaults to OFF.
- Under fault injection: driver input remains in OFF band (X to Y) and no valid turn-on pulses appear (placeholders).
Safe-state design (input-side only): OFF by default under faults
- No-float rule: any single-point fault that disconnects the signal must still force a deterministic OFF input state.
- Power sequencing rule: isolator and driver power loss must not create transient ON pulses at the receiver.
- No back-power rule: external pulls must not forward-bias input clamps beyond X_mA under any rail-off condition.
- Fault cases (open, short-to-REF, isolator VDD off, driver VDD off): input stays OFF and remains stable for Y minutes (placeholders).
Over-filtering risk points (must be prevented)
- RC too large: PW_eff collapses and short pulses are swallowed (must meet H2-7 PW criteria).
- Clamp too capacitive: edge deformation increases ringing sensitivity and shifts decision timing.
- Injection + recovery: clamps that dump charge into the isolator/receiver can trigger saturation/recovery windows.
Figure 8 — Hardening placement. Clamp at the connector limits injection. RS/RC near the isolator controls edge/glitches but must pass PW criteria. Termination/damping at the driver input stabilizes the decision waveform.
Validation & Debug Playbook: What to Measure, Where to Probe, How to Decide
Debug decisions must be made at the driver input pins with a fixed probing doctrine to avoid measurement-induced false conclusions.
The goal is a repeatable workflow: first classify common-mode vs differential-mode behavior, then confirm threshold margin, then validate pulse integrity and recovery under disturbances.
Measurement doctrine (avoid probe artifacts)
- Probe at the receiver: all acceptance metrics are taken at the gate-driver input pins, not at the source.
- SE reference is explicit: single-ended probing must reference driver REF/SGND to avoid ground-bounce illusions.
- DIFF requires VOD + VCM: differential probing must capture VP, VN, VOD, and VCM to separate CM from DM errors.
- No long ground leads: long ground clips form loops and can convert dv/dt fields into fake “glitches”.
- Glitches appear only with a ground clip: loop pickup, not true input behavior.
- SE looks clean but system fails: wrong reference point; verify against driver REF.
- DIFF looks clipped: probe common-mode range/bandwidth is insufficient; VCM excursion is being hidden.
Fast 10-minute debug path (each step has pass placeholders)
Confirm probe point and reference. Measure at driver IN pins; SE reference = driver REF.
- Reference shift at probe point < X_mV (placeholder).
Classify noise: CM or DM. For DIFF links, check VOD margin and VCM boundaries.
- VOD margin ≥ X_mV (placeholder).
- VCM stays within the receiver range (placeholder).
Confirm threshold margin. SE: VIH/VIL margin; DIFF: VOD_th margin (no multiple crossings).
- Threshold margin ≥ X (placeholder) and re-crossings ≤ X per edge (placeholder).
Validate pulse integrity. Check PW_eff and ΔPW at the driver input (link-level only).
- PW_eff(above threshold) ≥ X_ns (placeholder).
- |ΔPW| ≤ X_ns (or ≤ X_%), placeholders.
Check post-disturbance recovery. Apply worst-case dv/dt event or injection test and observe recovery.
- Recovery ≤ Y_us (placeholder) and false toggles = 0 over Y-window (placeholder).
Apply minimal fixes in priority order. Geometry/REF → RS/termination → RC/clamp (only after PW criteria holds).
- Threshold margin, PW_eff, and false-toggle metrics pass simultaneously (X/Y placeholders).
Symptoms → first checks (short list)
- Narrow pulses disappear: check PW_eff and RC/pull-up timing first.
- False toggles only at high dv/dt: check reference continuity and CM→DM conversion before adding filters.
- After EFT/ESD it stays unstable: check clamp injection and isolator recovery window.
- Scope looks clean but counters fail: re-validate probe reference and bandwidth; eliminate artifact paths.
Figure 9 — Debug flow. Probe at driver pins, classify CM vs DM, verify margin and PW integrity, apply minimal fixes, and close with pass criteria placeholders (X/Y/N).
Engineering Checklist: Design → Bring-up → Production Gates
Gate the input-link design with checkable criteria so failures are prevented early and regressions are detectable in production.
The checklists below are written as copyable review items with placeholders for X/Y/N thresholds and injection levels. Scope is limited to the input chain.
Checklists (copyable into review forms)
- Select input type (SE/DIFF) matched to interconnect scenario (on-board / cable / high dv/dt).
- Define default OFF state for open, floating, or isolator power loss cases.
- Confirm level/threshold margin at driver pins: margin ≥ X (placeholder).
- Specify RS/termination placement and values (placeholders), including internal-termination assumptions.
- Enforce routing rules: no split crossing; continuous reference; DIFF symmetry (checked in layout review).
- Allocate PW budget: PW_eff ≥ X_ns and |ΔPW| ≤ X (placeholders) captured in requirements.
- Specify clamp strategy and injection-current limit < X_mA (placeholder).
- Define probe doctrine and test points in the design package (driver pin + REF).
- Define recovery requirement: recovery ≤ Y_us and false toggles = 0 (placeholders).
- Document fault injection cases: open/short/rail-off must force OFF (X/Y placeholders).
- Verify probing at driver pins with correct reference; eliminate ground-clip artifacts.
- Capture baseline waveforms: SE (VIH/VIL) or DIFF (VOD/VCM) with margin ≥ X (placeholder).
- Measure PW_eff and ΔPW at nominal and worst-case loading; meet PW criteria (placeholders).
- Check re-crossings near threshold: ≤ X per edge (placeholder).
- Apply dv/dt worst-case switching condition and confirm false toggles = 0 (placeholder).
- Run disturbance event (EFT/ESD proxy) and confirm recovery ≤ Y_us (placeholder).
- Validate safe-state under open-cable and isolator power-off: input stays OFF band (X to Y).
- Record debug metrics: VOD/VCM, PW_eff, ΔPW, recovery, false toggles (template fields).
- Validate clamp/RS choices do not create saturation/recovery windows (pass = none observed).
- Freeze “known-good” settings and routing notes for production handoff.
- Manufacturing test confirms default OFF behavior for open or disconnected input (pass criteria placeholder).
- Sample test verifies PW_eff (or approved proxy) ≥ X_ns on Y% of units (placeholders).
- Sample test verifies false toggles = 0 over Y-window under defined switching condition (placeholders).
- Define injection sampling: ESD/EFT level placeholders (X kV / Y ns / N shots) per project spec.
- Define traceable test records: firmware/build + board revision + measurement setup captured.
- Define change triggers: isolator/connector/cable/termination changes require regression items list.
- Verify fixtures preserve the same reference point (driver REF) to avoid false pass/fail.
- Log any recovery anomalies; quarantine rule if recovery > Y_us (placeholder).
- Define acceptance limits for input leakage/back-power under rail-off (X_mA placeholder).
- Archive pass evidence and keep a golden-unit waveform baseline for audits.
Figure 10 — Gate flow. Design locks defaults/margins/routing rules; bring-up verifies probe doctrine, PW_eff, and recovery; production enforces fault-injection coverage, sampling tests, and traceability.
Applications & IC Selection: Choosing Inputs by Noise, Distance, and Isolation Topology
Select single-ended vs differential gate-driver inputs using only three variables: Noise type (CM vs DM), Interconnect distance, and Isolator output form. Then freeze the choice as measurable spec clauses at the driver pins so acceptance is unambiguous.
- Noise: CM / DM
- Distance: on-board / board-to-board / cable
- Topology: isolator output + defaults
- Acceptance: margin + pulse integrity
Classify the interconnect first; avoid “one-size-fits-all” input assumptions.
1) On-board short link (same PCB)
- Typical: MCU/FPGA → short trace → driver input.
- Main risk: ground-bounce shifting VIL/VIH reference at the receiver.
- Input tendency: single-ended can be sufficient if reference is continuous and return is controlled.
2) Board-to-board (connector between control & power board)
- Typical: control PCB → mezzanine/connector → driver PCB.
- Main risk: reference discontinuity + CM step injection at the connector.
- Input tendency: differential preferred; enforce symmetry + termination rules.
3) Cable / harness (cabinet or system-level)
- Typical: twisted pair through noisy environments.
- Main risk: dominant common-mode noise + external ESD/EFT injection.
- Input tendency: differential strongly preferred; define fail-safe default state.
4) High dv/dt vicinity (hard-switching nodes nearby)
- Typical: control wiring adjacent to switching node planes or power modules.
- Main risk: CM→DM conversion from asymmetry; false toggles around thresholds.
- Input tendency: differential + strict geometry/return rules; avoid “floating reference” ambiguity.
Rule of thumb: when the receiver reference is not guaranteed, treat the signal as a “pair problem,” not a “single wire problem.”
Each answer must produce: (1) input type recommendation and (2) a non-negotiable hard-rule bundle.
Q1 — Distance / medium?
- On-board short → go to Q2.
- Board-to-board or cable → DIFF preferred → go to Q3.
Q2 — Is receiver reference “trustworthy” under worst dv/dt/EMI?
- Yes (continuous reference/return) → SE allowed with REF+margin rules.
- No (splits/connector/ground bounce) → DIFF preferred with symmetry+termination rules.
Q3 — What is the isolator / source output form and default state?
- SE push-pull → SE can work only if Q2=Yes; otherwise convert to DIFF at the source/receiver.
- Open-drain / Hi-Z default → must specify external pull and a failsafe OFF behavior at the driver.
- Two complementary inputs (IN+/IN- or VI+/VI-) → can enforce polarity + enable/disable via dual-input logic; still validate margin at pins.
Output: Single-Ended (SE) — Hard rules
- Define REF: specify the receiver reference node and forbid “return across splits.”
- Define margins: VIH/VIL margin at driver pins ≥ X mV under worst ground-bounce.
- Define pulse integrity: effective pulse width PWeff ≥ X ns.
- Define default: open/Hi-Z/isolator loss must force OFF.
Output: Differential (DIFF) — Hard rules
- Define VOD: differential threshold margin at pins ≥ X mV.
- Define VCM: common-mode at pins must stay within receiver range across dv/dt steps.
- Enforce symmetry: pair geometry/length/return continuity; no single-line detours.
- Termination: specify 100 Ω (or internal) and placement rules for the interconnect class.
These fields must appear in the review checklist and the purchase specification.
For Differential (DIFF)
- VOD threshold and the project-defined VOD margin ≥ X at pins.
- Input VCM range and behavior when VCM exceeds range (no false toggles).
- Input impedance / internal termination availability; external 100 Ω placement rule.
- Channel symmetry requirements when DIFF is carried over two channels (skew budget placeholder).
For Single-Ended (SE)
- VIH/VIL thresholds, hysteresis, and allowed negative/overshoot handling at input pins.
- Input clamp / injection current limits and recovery behavior after transients.
- 3.3 V / 5 V compatibility and default behavior for floating input.
- Any input deglitch/filter function and its impact on minimum pulse width.
Common (Both)
- Failsafe default OFF definition for open/Hi-Z/isolator power loss.
- Acceptance metrics at pins: margin, PWeff, false toggles = 0 in a window Y.
- Recommended external network envelope: series R / RC / clamp (values as placeholders).
What to freeze in the design spec
- Interconnect class (on-board / board-to-board / cable) and routing constraints.
- Reference definition (SE) or symmetry/termination definition (DIFF).
- Validation plan: probe points and injected disturbance level placeholders.
Use “shall” language to prevent lab-to-lab ambiguity. Replace X/Y/N placeholders.
Interconnect & input type
- Shall classify the control link as on-board / board-to-board / cable and apply the corresponding routing rules.
- Shall use DIFF input for board-to-board or cable links above length X (placeholder) or when receiver reference is not guaranteed.
Margins
- DIFF: Shall guarantee VOD margin ≥ X mV at driver pins under worst-case VCM + noise.
- SE: Shall guarantee VIH/VIL margin ≥ X mV at driver pins under worst-case ground-bounce.
Pulse integrity
- Shall guarantee effective pulse width PWeff ≥ X ns at driver pins with the chosen input conditioning network.
- Shall limit pulse-width distortion |ΔPW| ≤ X ns (placeholder) at driver pins.
Failsafe default
- Shall force OFF for open input, isolator power loss, and Hi-Z states (no floating ambiguity).
- Shall demonstrate false toggles = 0 under injected disturbance level X (EFT/ESD placeholder) over observation window Y.
These are practical “starting BOMs” for the input chain. Verify package suffix, qualification, and availability per program.
Recipe 1 — On-board short SE (lowest complexity)
- Gate driver (SE input examples): TI UCC27511 (split outputs, low-side) — verify input handling rules per project.
- Series resistor (edge conditioning): Yageo RC0402FR-0710RL (10 Ω, 0402, 1%).
- Optional RC (anti-glitch, small): Murata GRM1555C1H101JA01D (100 pF, C0G, 0402) + pull/pad as needed.
- ESD clamp at connector/pin (if exposed): Nexperia PESD5V0S1BA (SOD323) placed at the entry point.
Acceptance focus: VIH/VIL margin at pins ≥ X, PWeff ≥ X, floating/Hi-Z → OFF.
Recipe 2 — Board-to-board / high dv/dt (isolation-first, dual-input capable)
- Isolated gate driver with dual inputs (IN+/IN- type): TI UCC21750 family (single-channel isolated gate driver; dual-input pins are commonly used as non-inverting/inverting control/enable depending on configuration).
- Alternative isolated driver with VI+/VI- dual inputs: Analog Devices ADuM4121 family (VI+ and VI− CMOS logic inputs on the input side).
- Digital isolator for PWM (SE channel isolator): TI ISO7821 (reinforced digital isolator, high CMTI class) when using a non-isolated driver on the secondary side.
- Digital isolator w/ integrated isolated power (bias simplify): TI ISOW7821 when integrated isolated power is desired on the isolated side.
- Input-side R/C/Clamp (typical): RC0402FR-0710RL (10 Ω), GRM1555C1H101JA01D (100 pF), PESD5V0S1BA (ESD).
Acceptance focus: default OFF under isolator loss, no false toggles under dv/dt stress, PW integrity preserved with conditioning.
Recipe 3 — Cable / harness DIFF (long distance, best noise robustness)
- LVDS DIFF transmit/receive: TI SN65LVDS31 (driver) + TI SN65LVDS32 (receiver). Place receiver close to the gate-driver input stage.
- How to interface to gate driver: LVDS receiver outputs single-ended CMOS into driver input (SE). If DIFF must be preserved, use two-channel mapping and validate symmetry/skew per project placeholder.
- Termination (DIFF pair): 100 Ω across the pair at the receiver side (or per interconnect rule); value and placement frozen as a spec clause.
- Protection at cable entry: PESD5V0S1BA on each line (or equivalent) + series R near entry if required.
Acceptance focus: VOD margin ≥ X at receiver pins, VCM within range, termination present, failsafe OFF when link opens.
Procurement note: For every “example MPN,” freeze the exact ordering suffix (package, temp grade, isolation rating, AEC-Q100 where applicable) inside the purchase specification.
