Digital Isolator + Gate Driver Combo for Tight Skew

Q: Skew looks fine in the lab, but phase current sharing is still uneven—first suspect what?

Likely cause: skew was verified at a different reference point than the power-stage edge (DIN→GOUT vs GOUT→VG at the device), or only typical conditions were measured. Quick check: measure channel-to-channel Δt at the same physical node (device gate or Kelvin-referenced VG) with identical probe chain and trigger reference. Fix: redefine the measurement contract (node, trigger, bandwidth limit) and re-run the skew report across temperature and supply corners. Pass criteria: ΔtPD(measured at device gate) ≤ X ns across Y temperature points; N samples/channel per point.

Q: ΔtPD meets datasheet typical, but worst-case timing still fails—what definition is likely mismatched?

Likely cause: datasheet “typ” was compared to system “worst-case,” or the edge threshold definition differs (e.g., 50% crossing vs input threshold vs output slew point). Quick check: restate the budget with explicit threshold and measurement points for each segment (controller → input shaping → barrier → output stage). Fix: convert the budget to worst-case (min/max VDD1/VDD2, temperature, load) and allocate margin to each segment including measurement uncertainty. Pass criteria: worst-case ΔtPD_budget ≤ X ns and measurement uncertainty ≤ Y ns; N repeats per corner.

Q: Only one channel misbehaves under load—routing skew or VDD2 droop first?

Likely cause: local VDD2 droop or decoupling placement causes output drive strength and timing to shift, masquerading as “channel skew.” Quick check: scope VDD2 at the IC pins for that channel during the failing load step and compare against a healthy channel using the same probe method. Fix: move/upgrade VDD2 decoupling to pin-level, reduce supply loop impedance, and re-check channel timing at the device gate node. Pass criteria: VDD2 droop ≤ X mV under Y A step; ΔtPD shift ≤ N ns vs idle condition.

Q: Works with single-ended input, fails after switching to differential (or vice versa)—which immunity assumption broke?

Likely cause: return-path or common-mode noise moved the input threshold crossing timing; differential/common-mode limits were not respected at the receiver. Quick check: measure input pin common-mode (and for differential, the pair balance) during switching events and count spurious transitions within a defined window. Fix: enforce the recommended input wiring (short loop, controlled return), add input damping/threshold conditioning where allowed, and standardize the default/fail-safe state. Pass criteria: spurious input transitions = 0 over X minutes; common-mode stays within Y V; N repeats across stress cases.

Q: No false triggers at low dv/dt, but misfires appear at higher dv/dt—first check which coupling path?

Likely cause: barrier capacitance and return-path geometry inject common-mode current into the secondary ground, shifting input/output thresholds and creating false toggles. Quick check: reproduce at a defined dv/dt (X kV/µs), then correlate false triggers with secondary ground bounce and input pin disturbances. Fix: tighten secondary return, avoid copper under the barrier keep-out, improve decoupling at VDD2 pins, and reduce loop areas that convert CM current into voltage. Pass criteria: false triggers = 0 at dv/dt = X kV/µs over Y minutes; N repeats and N boards.

Q: Turning on the isolated DC-DC makes timing jitter worse—ripple fold-in or reference bounce?

Likely cause: VDD2 ripple and/or secondary ground bounce modulates the internal shaping and output stage, increasing cycle-to-cycle jitter and apparent delay drift. Quick check: inject a controlled ripple (X mVpp at switching freq Y) and measure ΔtPD and jitter response with a fixed trigger and window. Fix: add pin-local decoupling, reduce DC-DC output impedance, and re-route returns so ripple current does not flow through sensitive reference nodes. Pass criteria: added jitter ≤ X ns (p-p) and ΔtPD drift ≤ Y ns at ripple = N mVpp.

Q: UVLO never trips, but outputs still weaken under bursts—what supply metric is missing?

Likely cause: dynamic droop and high-frequency impedance cause momentary drive-current reduction without crossing the UVLO threshold. Quick check: measure VDD2 droop at IC pins with high bandwidth during burst load; compare against output edge rate and gate plateau behavior. Fix: lower supply impedance (better decoupling + shorter loop), verify DC-DC transient response, and allocate ripple/droop limits in the power budget. Pass criteria: VDD2 droop ≤ X mV and edge-rate change ≤ Y% during burst of N cycles.

Q: Two boards with the same BOM show different skew—first normalize what measurement setup detail?

Likely cause: probe loading, bandwidth limit, trigger reference, or measurement node differences dominate the reported ns-level skew. Quick check: lock the “measurement contract” (same probe, same attenuation, same bandwidth limit, same node, same trigger threshold) and rerun both boards. Fix: publish the measurement contract as a release artifact and require it for every acceptance run. Pass criteria: inter-board Δ(ΔtPD) ≤ X ns using the fixed setup; Y repeats; N channels per board.

Q: Intermittent shoot-through despite combo integration—what protection responsibility is most commonly missing?

Likely cause: the system assumes “combo = full protection,” but fast short-circuit response, clamp strategy, or a deterministic shutdown chain is not actually implemented. Quick check: map protections into a matrix (built-in vs external) and time-stamp the actual disable path latency end-to-end. Fix: add the missing external blocks (e.g., fast fault detect / clamp / shutdown gating) and validate response under fault injection. Pass criteria: fault-to-shutdown latency ≤ X µs; no shoot-through events over Y injected faults; N repeats per condition.

Q: /FLT asserts but the system still doesn’t shut down fast enough—first check which link in the shutdown chain?

Likely cause: /FLT is treated as an informational signal, while the real disable action depends on a slower path (firmware polling, slow opto, or miswired enable). Quick check: scope /FLT, DISABLE input, and gate output simultaneously to measure fault→disable→output-off latency. Fix: enforce a hardware interlock path for immediate disable, and keep the reporting path separate from the safety shutoff path. Pass criteria: /FLT to output-off ≤ X µs; disable path is hardware-only; N fault injections with 0 misses.

← Back to: Gate Driver ICs

A Digital Isolator + Gate Driver Combo reduces interface and routing uncertainty so multi-phase/multi-bridge systems can close timing (ΔtPD/skew/jitter) more deterministically under high dv/dt.

It helps by tightening the signal path from isolated input to gate output—then the remaining work is to budget, measure, and verify power-noise coupling, CMTI false-trigger immunity, and protection partitioning with clear pass criteria (X/Y/N).

H2-01 · Definition & Scope Boundary

A Digital Isolator + Gate Driver Combo integrates the digital isolation path and the high-current gate-drive output stage into one package, reducing interconnect uncertainty so channel-to-channel skew (ΔtPD) is easier to control in multi-phase and multi-bridge systems.

Engineering Definition

Structure: Digital front-end (input conditioning/encoding) → isolation barrier → decoding → gate-drive output stage.
Primary value: Removes the isolator→driver interface + routing segment that often dominates ΔtPD variation in two-chip solutions.
System goal: More predictable timing closure (tPD / ΔtPD / drift) under dv/dt stress and supply noise.

tPD ΔtPD (skew) drift vs T/VDD CMTI robustness

Scope Contract (Anti-Overlap)

Owned here: one-package timing determinism, skew sources, integration trade-offs, and how to choose between 3 integration models.
Not owned here: isolation standards deep-dive, switch-physics gate-voltage cookbooks, DESAT mechanism tutorials (handled by sibling pages).
Allowed: short comparisons + “what to read next” links (no re-defining full topics).

Decision Triggers (When to Use Combo)

Use Combo when multi-channel ΔtPD must stay within a tight budget for current sharing, deadtime consistency, or phase alignment.
Prefer separate parts when the system is single-channel and skew is not a limiter, or when the layout is unconstrained and isolation/channel count is low.
Prefer fully isolated gate drivers when the design needs more integrated protection or isolation-side features beyond “tight skew”.

H2-02 · Where It Fits: Multiphase & Multibridge Timing Closure

The Combo package is most valuable when multi-channel edge alignment directly impacts current sharing, deadtime margin, and system EMI. In these systems, the timing budget is frequently limited by channel-to-channel skew and its drift with temperature, supply ripple, and dv/dt stress.

Why Tight Skew Matters (Cause → Effect)

ΔtPD grows → phase edges spread → effective phase alignment degrades → ripple cancellation weakens → EMI becomes harder to close.
HS/LS relative delay shifts → deadtime gets eaten under worst-case drift → higher shoot-through risk or extra switching loss if deadtime is over-inflated.
Inconsistent edges → per-leg loss differs → thermal imbalance increases → current sharing and long-term reliability suffer.

Multiphase VR (What to Watch)

Symptom pattern: one or two phases run hotter at the same load; ripple/EMI varies with phase count enabled.
Timing risk: phase-to-phase ΔtPD competes with the controller’s intended phase offset accuracy.
Verification focus: measure ΔtPD at the gate outputs across temperature and supply ripple; verify current balance stays within X% over Y minutes.

Multibridge / 3-Phase Inverters (What to Watch)

Symptom pattern: occasional overlap events only at high dv/dt; EMI spikes in specific operating regions; leg-to-leg thermal mismatch.
Timing risk: HS/LS skew reduces effective deadtime margin under drift, forcing conservative deadtime that increases loss.
Verification focus: confirm no overlap under worst-case dv/dt and temperature; maintain deadtime margin ≥ X ns with drift included.

Continue the timing closure path

Scope · H2-04 Timing Budget · H2-05 Input Robustness · H2-10 Layout & EMI

Diagram · Where skew enters in multiphase VR and multibridge systems

H2-03 · What’s Inside: Channel Architecture & Signal Path

A combo device can be analyzed as a five-segment signal path from DIN to GOUT. Each segment contributes delay, variation, and potential coupling. The key advantage comes from keeping the post-isolation-to-output path short and consistently matched across channels inside one package.

Signal Path Segments (DIN → GOUT)

Use a consistent engineering view across all channels: Delay Variation Coupling Drift

Input conditioning: thresholds and edge cleanup that define what becomes a valid transition.
Encoding / modulation: internal transmit path that maps logic edges into a barrier-safe representation.
Isolation barrier: the crossing element where dv/dt and barrier capacitance can inject common-mode disturbance.
Decoding / receiver: edge reconstruction that is sensitive to supply noise and temperature drift.
Gate output stage: push-pull buffer where ground bounce and VDD2 headroom affect edge timing and strength.

Per-Segment Engineering Card (Role → Error Source → Control Lever)

Input conditioning — Role: define valid edges. Error source: threshold drift / glitches / minimum pulse ambiguity. Control lever: clean input routing, stable VDD1 decoupling, avoid noisy reference returns.
Encoding / modulation — Role: barrier-safe transport. Error source: internal timing quantization and modulation clock noise. Control lever: select devices by tPD / jitter specs; keep within recommended input patterns.
Barrier crossing — Role: isolation transfer. Error source: dv/dt injection via barrier capacitance and common-mode surge. Control lever: manage dv/dt environment, minimize coupling loops, keep barrier-side references quiet.
Decoding / receiver — Role: reconstruct edges. Error source: VDD noise coupling, temperature drift, receiver threshold mismatch. Control lever: strong local decoupling on both sides, stable grounds, avoid shared noisy return paths.
Output stage — Role: deliver peak current to gate network. Error source: ground bounce and VDD2 droop shifting effective edge timing. Control lever: tight output loop placement, short gate-drive return, local bulk + high-frequency decoupling.

Why One Package Is More Controllable (ΔtPD & Drift)

Removes the isolator→driver interface as a board-level uncertainty segment (threshold and routing mismatch).
Shortens post-barrier routing so channel matching is less dominated by PCB geometry differences.
Improves intra-package matching, enabling tighter channel-to-channel consistency under temperature and supply variation.

Multi-Channel Organization Patterns (Structure Only)

2-channel symmetric: CH1/CH2 are identical for tight skew pairing.
HS/LS paired: channel pairing focuses on relative timing consistency inside a half-bridge leg.
3-phase 6-channel grouping: A/B/C phases each with HS/LS; critical checks are within-leg skew and phase-to-phase skew.

Continue the deterministic timing path

H2-04 Timing Budget · H2-05 Input Interface & Robustness · H2-07 Powering Both Sides

Diagram · Internal signal path (DIN → GOUT) with delay / variation / coupling sources

H2-04 · Propagation Delay, Skew & Jitter: How to Budget It

Timing closure improves when the budget explicitly separates tPD, ΔtPD (channel-to-channel skew), and cycle-to-cycle jitter. A useful budget model groups contributors into Upstream (controller), Inside Combo (isolation + receiver + output), and Board-level (routing + supply coupling).

Engineering Definitions (On-Page Measurement Contract)

tPD: time from a valid input edge at DIN to the corresponding edge at GOUT (use consistent edge threshold in lab).
ΔtPD (skew): difference in tPD between two channels measured under the same conditions (temperature, supplies, load).
Cycle-to-cycle jitter: variation of tPD over repeated cycles for the same channel and condition window.

Why Combo Budgets Close Easier

Eliminates an external interface segment (isolator→driver) that commonly adds mismatch via thresholds, routing, and reference noise.
Reduces board-level mismatch terms by shortening post-isolation routing and keeping critical matching inside the package.
Makes drift more correlated across channels, improving worst-case ΔtPD predictability over temperature and VDD variation.

Pass-Criteria Templates (Placeholders)

Multiphase: phase-to-phase ΔtPD ≤ X ns over Y°C with VDD ripple ≤ Z mV.
Half-bridge: HS–LS relative skew ≤ X ns under dv/dt = Y kV/µs (no overlap).
Stability: cycle-to-cycle jitter ≤ X ns over Y cycles within a defined measurement bandwidth.

Budget item	Impacts	Control lever	Pass criteria (placeholders)
Upstream: controller edge jitter	tPD jitter / ΔtPD via edge ambiguity	Stable clocking, consistent PWM generation settings, verify edge quality at source.	jitter ≤ X; stable over Y minutes
Upstream: input routing mismatch	ΔtPD (channel skew)	Length-match and keep return paths consistent before the combo input.	ΔtPD_in ≤ X ns
Inside Combo: isolation transmit/receive	tPD / drift vs T/VDD	Select by tPD/ΔtPD specs; keep VDD1/VDD2 within recommended ranges.	tPD drift ≤ X over Y°C
Inside Combo: decoder sensitivity	jitter / drift under noise	Strong local decoupling; avoid noisy shared returns; reduce CM injection.	no false edges under dv/dt = X
Inside Combo: output stage strength	edge timing shift under VDD2 droop	Place bulk + HF capacitors close; ensure VDD2 headroom; minimize output loop inductance.	edge shift ≤ X under ripple Y
Board-level: output trace mismatch	ΔtPD at gate	Match trace length and coupling environment; keep symmetric reference planes.	ΔtPD_gate ≤ X ns
Board-level: gate loop parasitics	effective edge timing & ringing	Short loop, Kelvin source, avoid via-stacks on critical returns; consistent Rg placement.	ringing ≤ X; stable edge
Board-level: supply ripple coupling	jitter / false edge susceptibility	Separate quiet/dirty domains, filter/decouple, keep high di/dt loops away from logic references.	ripple ≤ X; no upset

Diagram · Timing budget comparison (Separate adds an extra uncertainty segment)

H2-05 · Input Interface & Logic Robustness (SE/Diff, Thresholds, Immunity)

Input robustness is defined by edge integrity, reference stability, and common-mode injection paths. A combo device can improve determinism by providing more consistent input conditioning, threshold behavior, and fail-safe state definition across channels—while board-level return paths still decide whether the input is interpreted correctly under noise.

Input Types (Engineering Meaning)

CMOS/TTL (push-pull): fast edges; sensitive to ground bounce and routing-induced glitches when reference returns are poor.
Schmitt input (if available): stabilizes slow/noisy edges by adding hysteresis; may introduce stricter minimum pulse behavior.
Differential input (if available): improves immunity by rejecting common-mode disturbance and reducing dependency on a perfect shared ground reference.
Fail-safe default: defines safe output state under open input / disconnect / undefined input conditions.

Top Noise Mechanisms (What Causes False Triggering)

Ground bounce / reference shift: controller ground and combo input ground move relative to each other, shifting effective thresholds.
Common-mode injection: dv/dt and di/dt events inject current through parasitic capacitance, distorting input edges.
Cable / connector transients: reflections and contact bounce create narrow pulses that can be misclassified as valid edges.

What Combo Improves (Without Becoming an Isolator Handbook)

Consistent conditioning across channels: similar threshold and shaping behavior reduces channel-to-channel input ambiguity.
Fewer external interface uncertainties: removes an extra isolator→driver threshold handoff that can amplify mismatch under noisy references.
Clearer default state definition: fail-safe behavior reduces “floating input” surprises in field wiring scenarios.

Recommended Wiring · Short traces

Prefer single-ended push-pull when the ground reference is local and stable.
Keep input traces short and over a continuous reference plane.
Do not cross split planes; keep return paths continuous.
Pass: no false edges under normal switching; error rate ≤ X / Y hours.

Recommended Wiring · Long traces / connectors

Prefer differential input if supported; otherwise enforce a strong paired return strategy.
Route signal and return together; avoid large loop area through connectors.
Reduce reflection sources (avoid stubs; keep consistent impedance).
Pass: stable edge recognition with cable length = X m.

Recommended Wiring · Harsh noise environments

Prefer differential; treat the input as a noise-susceptible sensor line.
Separate from power switching nodes; avoid parallel routing near high dv/dt nets.
Validate under worst-case dv/dt = X kV/µs and load current = Y.
Pass: no spurious toggles; timing stays within budget.

Related pages (scope clean)

Propagation Delay & Matching · CMTI / dv/dt Immunity · Layout & Grounding

Diagram · SE vs Diff input, return path, and common-mode injection points

H2-06 · Gate Output Stage: Peak Current, VG Range, Slew Shaping

The gate output stage determines how quickly gate charge is moved and how repeatably the edge is executed under supply droop and parasitics. Selection and sizing should start from Qg and a target t_edge, then verify that the driver can meet the needed I_PEAK and voltage range while maintaining stability in the real gate loop.

Output-Stage Parameter Map (What Each One Controls)

Peak source / sink current: sets how fast Qg is charged/discharged; impacts switching loss and transient EMI.
Effective output resistance: limits current and shapes the edge; influences ringing sensitivity.
Gate voltage range (VG+ / VG−): defines headroom for turn-on strength and turn-off robustness against Miller coupling.
Slew shaping capability: whether edges can be tuned using external Rg networks or internal shaping (if provided).
VDD2 sensitivity: droop and noise on the drive supply can shift edge timing and effective drive strength.

Sizing Card · From Qg to IPEAK

I_PEAK ≈ Q_g(ΔV_G) / t_edge

Q_g(ΔV_G): total gate charge over the intended gate swing (includes plateau region).
t_edge: target rise/fall time chosen by the loss vs EMI trade-off.
Practical note: the realized edge is also shaped by R_DRV + R_g and loop inductance (see gate-loop diagram below).

Typical Design Decision Points (Speed vs EMI vs Robustness)

Faster edges: increase IPEAK or reduce total Rg → lower switching loss, but increases ringing/EMI risk.
Cleaner EMI: add slew shaping (Rg networks) → reduces dV/dt and ringing, but can raise loss and heat.
More robust turn-off: stronger sink path and suitable VG− margin → improves immunity against dv/dt induced turn-on.

Common Missing Features in Combo Devices (External Implementations)

Separate Rg_on / Rg_off: implement with a diode + resistor network to shape turn-on and turn-off differently.
Two-step drive / soft turn-off: often external networks are used when not available internally.
Fine-grain drive strength control: may be limited; verify with gate waveform under worst-case VDD2 ripple and temperature.

Pass-Criteria Templates (Placeholders)

Edge settling within X ns; ringing ≤ Y% of V_G.
No spurious turn-on under dv/dt = X kV/µs.
Gate waveform repeatable over Y°C with VDD2 ripple ≤ Z mV.

Diagram · Gate loop: driver output + parasitics + Rg shaping

H2-07 · Powering Both Sides: VDD1/VDD2, Bias Strategy & Noise

A combo device is powered by two domains: VDD1 (primary logic side) and VDD2 (secondary drive side). VDD1 stability protects input decision integrity, while VDD2 stability determines drive strength, edge repeatability, and drift in propagation timing under ripple and load transients.

Two-Rail Contract (What Each Supply Must Guarantee)

VDD1 (logic side): stable thresholds and robust input recognition under ground bounce and common-mode events.
VDD2 (drive side): consistent peak current and gate swing; avoids edge slowdown, timing drift, and UVLO chatter.
Key coupling: VDD2 ripple can map into delay drift, false triggering, and drive-strength variation.

Topology · Isolated DC-DC → VDD2 (direct)

Use when: multi-bridge / multi-phase, high dv/dt, strong isolation boundary required.
Pros: clear supply partition; scalable drive power.
Risks: ripple and common-mode noise inject into secondary reference.
Check: VDD2 ripple ≤ X mVpp under load step = Y A.

Topology · Isolated DC-DC → LDO/Filter → VDD2 (cleaned)

Use when: skew/timing closure is tight; edge repeatability dominates performance.
Pros: reduced ripple-driven drift; cleaner VDD2 for consistent drive strength.
Risks: dropout and heat; slower transient response if filtering is too heavy.
Check: dropout headroom ≥ X mV; thermal margin ≥ Y °C.

Topology · Auxiliary winding / secondary rail → VDD2

Use when: the system already provides an isolated auxiliary rail (power-stage ecosystem).
Pros: BOM-efficient; may improve overall efficiency.
Risks: rail variation with load; startup sequencing can drift.
Check: VDD2 stays inside datasheet range across light/heavy load.

Topology · Bootstrap-like supply (when applicable)

Use when: a floating reference structure exists and the system architecture supports it.
Pros: reduced isolated supply complexity in specific arrangements.
Risks: headroom loss and UVLO boundary events under duty-cycle extremes.
Check: UVLO does not chatter at duty extremes; headroom ≥ X V.

Noise → Timing Coupling (How Ripple Becomes Drift)

VDD2 ripple → drive-strength drift: edge rate changes and channel behavior diverges under the same command.
VDD2 droop → UVLO boundary: intermittent disable or edge truncation under load steps and dv/dt stress.
Common-mode injection → reference bounce: timing and threshold behavior shift during fast switching events.

Datasheet Checks (Selection & Integration)

VDD1 and VDD2 operating ranges and recommended conditions.
VDD2 UVLO thresholds (ON/OFF) and hysteresis to avoid chatter near the boundary.
Drive-side supply current behavior (static + dynamic vs switching frequency).
Propagation delay / skew drift vs supply and temperature (if provided).
Recommended decoupling placement and minimum bulk requirements per side.

Acceptance Templates (placeholders)

VDD2 ripple ≤ X mVpp under load step = Y A.
No UVLO chatter across Y cycles at dv/dt = X kV/µs.
ΔtPD drift ≤ X ns over Y °C with VDD2 ripple ≤ Z mV.

Diagram · VDD1/VDD2 domains, supply options, decoupling, and noise injection

H2-08 · Isolation & Package Reality: CMTI, Barrier Capacitance, Creepage

Isolation performance is not defined only by “kV rating”. In combo devices, CMTI, barrier capacitance, and package creepage/clearance geometry directly determine false triggering risk, timing drift under dv/dt, and board-level layout constraints required for system acceptance.

Metric (what to read)

CMTI test conditions and stated dv/dt capability.
Cbar / barrier capacitance (or a proxy spec, if given).
Creepage / clearance numbers and package geometry notes.

Risk (what it breaks)

dv/dt events can induce spurious toggles and timing drift.
Barrier capacitance converts dv/dt into common-mode current that disturbs secondary reference.
Insufficient creepage/clearance fails safety spacing and forces keepout rules in layout.

Board actions (what to do)

Keep high dv/dt nodes away from sensitive receiver and secondary reference paths.
Define a short, controlled secondary return path for CM current; keep decoupling loops tight.
Honor creepage keepout; avoid copper/ vias near the isolation boundary; apply slots only when required.

Acceptance Templates (placeholders)

No spurious toggles at dv/dt = X kV/µs; ΔtPD drift ≤ Y ns.
Secondary reference disturbance ≤ X (units) under worst-case dv/dt.
Creepage keepout ≥ X mm; clearance ≥ Y mm per package geometry constraints.

Diagram · dv/dt → Cbar → Icm injection, plus creepage/keepout constraints

H2-09 · Protection Partitioning: What Combo Gives You vs What You Still Need

A combo device improves timing determinism by integrating isolation + drive, but it does not automatically provide a complete protection stack. Protection should be partitioned into (1) what is typically inside the combo and (2) what must be implemented externally for fast fault response and safe shutdown closure.

Typically Included (common cases)

UVLO (maybe): prevents partial conduction when VDD2 droops near the boundary.
Default output state: defines a safe behavior under missing/undefined input conditions.
/FLT or status (maybe): improves observability, not necessarily protection speed.

Often Missing or Incomplete (common cases)

DESAT / short-circuit fast turn-off: required for short-circuit energy control in high-power stages.
Active Miller clamp: required to suppress dv/dt induced false turn-on in fast switching environments.
Two-step / soft turn-off: required to reduce overshoot/ringing while still meeting short-circuit constraints.
Fine deadtime control: required for multi-bridge / multi-phase alignment and shoot-through risk reduction.

Protection function	Typical in combo?	External module (typical)	Link (scope clean)
UVLO (VDD2)	Maybe	Supply supervision / cleaned VDD2 rail	UVLO thresholds
Default output state	Often	System shutdown chain validation	Fault reporting & disable
/FLT, /RDY (status)	Maybe	Latch / retry policy in controller	Fault reporting & disable
DESAT / SC detect	No	DESAT sense + blanking + fast turn-off path	DESAT short-circuit detection
Active Miller clamp	Maybe	Gate clamp network / dedicated clamp function	Active Miller clamp
Two-step / soft turn-off	Maybe	External shaping network / turn-off clamp strategy	Two-level turn-on/off
Deadtime control	No	PWM/controller deadtime + hardware interlock	Deadtime & interlock
Current / temp telemetry	No	Isolated sensing (shunt / temp) + protection loop	Driver with sensing

System Shutdown Closure (placeholders)

Trigger sources: DESAT / over-current / over-temp / loss of control.
Shutdown path: PWM disable + gate disable + safe-latch strategy.
Acceptance: response time ≤ X ns; short-circuit energy ≤ Y; recovery criteria = Z.

Diagram · Responsibility split: combo vs external protection modules

H2-10 · Layout & EMI: Interconnect Removal Helps, But Not a Free Lunch

A combo device removes the isolator→driver interconnect, reducing interface loop area and mismatch sources. However, layout success is still determined by the gate loop, Kelvin return integrity, decoupling placement, and whether any return path crosses a split boundary under high dv/dt conditions.

What Interconnect Removal Improves

Less interface wiring: fewer loop opportunities for noise pickup and threshold ambiguity.
More consistent channel behavior: fewer interface-induced skew and mismatch terms.
Cleaner partitioning: fewer places where return currents can “choose” unintended paths.

Still-Game-Over Traps

Large gate loop → ringing and EMI rise; timing repeatability degrades.
Missing Kelvin source → the driver sees a moving reference under di/dt.
Decoupling not at pins → VDD2 droops; edge strength and delay drift increase.
Return crossing a split → reference bounce and false behavior under dv/dt.

EMI Trade-offs (control knobs)

Rg and optional ferrite: set edge speed vs ringing margin.
Partition: keep noisy switching loops away from sensitive input/receiver paths.
Validation: ringing ≤ X%, overshoot ≤ Y, false turn-on = 0.

Do

Place the combo as close as possible to the power switch gate connection.
Route a tight gate loop with a defined Kelvin source return.
Place HF decoupling directly at VDD2 pins with minimum loop area.
Maintain a continuous return reference; keep isolation keepout clear.
Keep high dv/dt nodes away from the input/receiver region.

Don’t

Do not run long gate traces or allow stubs in the gate path.
Do not mix driver reference return with high-current power returns.
Do not place decoupling far from pins or behind narrow choke points.
Do not allow any return current to cross a split/slot boundary.
Do not route sensitive inputs parallel to switching nodes for long distances.

Diagram · Recommended placement vs avoidable pitfalls (return across split)

H2-11 · Engineering Checklist (Design → Bring-up → Production)

This chapter turns “spec talk” into a gate-based execution path. Each gate locks inputs, required artifacts, and pass criteria placeholders (X/Y/N) to prevent review and lab argument loops.

Goal: make timing closure + immunity verifiable Output: repeatable artifacts, not opinions Rule: every item has Pass criteria (X/Y/N)

Boundary: mechanism deep dives stay in their own chapters/pages (timing budget, power noise coupling, protection circuits). This gate list only enforces what must be checked and proven.

Design Gate

Lock definitions, constraints, and board rules before layout or procurement.

Timing budget worksheet finalized
Artifact: budget table for tPD, ΔtPD, cycle jitter; includes “separate vs combo” segment delta.

Pass criteria: ΔtPD ≤ X ns; cycle jitter ≤ Y ns; measurement definition fixed (N = window length).
VDD1 / VDD2 margin & UVLO headroom written
Artifact: supply worst-case table (min/max/step-load ripple) and UVLO thresholds vs system rails.

Pass criteria: VDD2 ripple ≤ X mVpp under Y A step; UVLO never enters chatter across N cycles.
Isolation reality constraints captured
Artifact: PCB keep-out/creepage rules and barrier parasitic path assumptions documented.

Pass criteria: creepage ≥ X mm; clearance ≥ Y mm; no copper under barrier within N mm.
Protection partition matrix approved
Artifact: “built-in vs external” responsibilities list (UVLO / clamp / DESAT / system shutdown chain).

Pass criteria: all missing protections have assigned external blocks; response path ≤ X µs with N-step fault injection.
Layout constraints converted into placement rules
Artifact: gate-loop, Kelvin-source, decoupling-to-pin rules; forbidden return crossings defined.

Pass criteria: gate loop area ≤ X; decoupling distance ≤ Y mm; 0 prohibited return crossings (N = review checklist items).
Bring-up measurement plan is defined early
Artifact: probe points, trigger reference, bandwidth limit, and test scripts listed.

Pass criteria: repeatability error ≤ X ns across Y repeats; instrument + probe chain fixed (N = setups).

Bring-up Gate

Prove real switching behavior, skew, and immunity under defined stress.

Double-pulse test (DPT) window captured
Artifact: VDS/IDS/VG waveforms + ringing metrics and edge times for on/off transitions.

Pass criteria: overshoot ≤ X%; ring decay ≤ Y cycles; tr/tf within target ±N%.
Skew measurement method validated
Artifact: channel-to-channel delay report with identical triggering and probe chain.

Pass criteria: ΔtPD(measured) ≤ X ns across Y temperature points; N = sample size per point.
CMTI false-trigger test executed
Artifact: dv/dt condition definition + false pulse count vs time window.

Pass criteria: false trigger count = 0 over X minutes at Y kV/µs; N = repeats.
Supply-noise → timing coupling quantified
Artifact: ΔtPD and output strength shift vs controlled VDD2 ripple injection.

Pass criteria: ΔtPD drift ≤ X ns at ripple = Y mVpp; no spurious toggles over N cycles.
Fault injection proves shutdown chain closure
Artifact: /FLT behavior, disable latency, and recovery policy trace.

Pass criteria: shutdown latency ≤ X µs; recovery does not oscillate (N = injected faults).

Production Gate

Convert lab success into batch-stable shipping criteria: consistency, drift, and regression.

ΔtPD sampling plan defined by lot + temperature
Artifact: sampling matrix (lot/board/temp) and recorded ΔtPD distribution.

Pass criteria: ΔtPD p99 ≤ X ns; mean drift ≤ Y ns across N boards per lot.
EMI/ESD regression ties to a baseline configuration
Artifact: regression checklist bound to PCB revision, firmware, BOM, and test setup.

Pass criteria: no new failures vs baseline across X tests; N = configuration hashes.
Documentation “measurement contract” is frozen
Artifact: probe model, bandwidth limit, trigger definition, and script versions recorded.

Pass criteria: repeatability error ≤ X ns across Y labs; N = repeated runs.

Typical release package artifacts: timing budget sheet, DPT waveforms, skew report, CMTI false-trigger log, fault-injection traces, and production sampling summary (all with X/Y/N placeholders filled).

Reference BOM Examples (Part Numbers)

These part numbers are examples for planning and prototyping. Verify voltage, isolation rating, package creepage, and safety approvals against the end system requirement.

Combo / “Isolator + Driver in one package” examples

ADuM3223 (isolated half-bridge gate driver, 4 A class)
ADuM4223 (isolated half-bridge gate driver, higher isolation variant)
Si8233 (Si823x family, isolated driver, 4 A class)
1EDB8275F (Infineon EiceDRIVER™ isolated gate driver family example)
ACPL-332J-000E (optically isolated gate-driver optocoupler, 5 kVrms class)

Separate approach examples (for comparison)

ISO7721 (dual-channel digital isolator, robust EMC)
UCC27531 (single-channel gate driver with split outputs)
BLM18AG601SN1 (ferrite bead, 0603 class, for input/drive noise shaping)
GRM188R71C105KA12D (MLCC 1 µF 0603 X7R, typical decoupling placeholder)
ERJ-3RQF2R0V / CRCW06032R00FKEA (0603 resistor examples for Rg,on/off placeholders)

Isolated bias / housekeeping examples (VDD2 supply planning)

MGJ2D241505SC (isolated gate-drive power DC-DC example, ± rails variant)
NXJ1S0505MC (isolated DC-DC 1 W class example)
BAS21 (high-voltage switching diode example for protection/blanking networks where applicable)

If DESAT or advanced protection is required, consider a fully integrated isolated driver class (example: UCC21750) or an isolated gate driver with clamp features (example: ADuM4135), then re-run the “Protection partition” matrix to avoid missing response-time requirements.

Diagram 11 — Gate-based workflow with required artifacts (use X/Y/N thresholds for pass criteria).

H2-12 · Applications & IC Selection (Before FAQ)

Selection must start from system timing pain, not from a catalog filter. The decision tree below enforces a top-down priority: ΔtPD closure → dv/dt immunity → drive strength → power strategy → protection responsibilities.

Owner: Separate vs Combo vs Full isolated driver Metric first: ΔtPD, CMTI, IPEAK/VG Always: re-check supply + layout + protection split

Where Combo Is Worth It (Tight Timing Closure)

Multiphase VR (N phases)
Pain: phase-to-phase edge alignment limits current sharing and transient control.

Why combo helps: removes isolator→driver interconnect uncertainty; improves channel matching behavior.

Must validate: ΔtPD ≤ X ns across Y temp points; N = samples per phase.
Multi-bridge / 3-phase inverter stacks
Pain: deadtime consistency and edge matching influence shoot-through risk and loss balance.

Why combo helps: reduces interface segments and skew sources near the output stage.

Must validate: worst-case skew + jitter stays within deadtime margin (X/Y/N).
High dv/dt noisy isolation boundaries
Pain: dv/dt injection creates false triggers or timing drift via common-mode paths.

Why combo helps: consistent internal shaping from input to output, but still depends on CMTI and parasitics.

Must validate: false trigger count = 0 at Y kV/µs over X minutes (N repeats).
Dense multi-channel layouts
Pain: long routing and mismatched return paths inflate skew and EMI variability.

Why combo helps: fewer packages and fewer nets reduce uncontrolled loop areas.

Must validate: layout rules + decoupling placement meet X/Y/N constraints.

Spec Priority (Must / Should / Nice)

Must: ΔtPD, CMTI, IPEAK/VG, UVLO (if required) Should: barrier parasitics (Cbar hints), creepage/clearance, temp drift data Nice: status pins, fail-safe defaults, optional input types

Quick Selection Worksheet (fill-in)

System topology
Phases/bridges = X; switching freq = Y; control bandwidth target = N.
Timing closure target
ΔtPD limit = X ns; allowed cycle jitter = Y ns; measurement window = N cycles.
dv/dt environment
Worst-case dv/dt = X kV/µs; ground bounce expectation = Y; false-trigger budget = N.
Drive requirement
Qg,total = X nC; target tr/tf = Y ns → IPEAK estimate = N A (then verify with DPT).
Power strategy
VDD1 rail = X V; VDD2 rail(s) = Y/(-Y) V; isolated bias available? (Yes/No); N = ripple budget.
Protection responsibilities
Built-in: X; External: Y (DESAT/clamp/shutdown chain). Close the response-time budget (N = total µs).

Example Part Numbers by Architecture

Use these as starting points to map requirements → datasheet fields. Final selection must match insulation class, creepage, and system safety needs.

Separate (Isolator + Driver)

ISO7721 (digital isolator) + UCC27531 (gate driver)
Noise shaping placeholders: BLM18AG601SN1 ferrite bead; GRM188R71C105KA12D MLCC
Gate resistor placeholders: ERJ-3RQF2R0V or CRCW06032R00FKEA (value as required)

Combo (Isolator + Driver in one package)

ADuM3223 (isolated half-bridge driver example)
ADuM4223 (higher isolation variant example)
Si8233 (Si823x family example)
1EDB8275F (Infineon isolated driver family example)
ACPL-332J-000E (optical gate driver optocoupler example)

Full isolated driver (when advanced protection is mandatory)

UCC21750 (isolated gate driver class with DESAT & clamp features)
ADuM4135 (isolated gate driver class with Miller clamp feature)

If the system requires DESAT/fast short-circuit turn-off, the “combo” category may be insufficient. Enforce the protection partition matrix and response-time budget first, then choose an architecture.

Diagram 12 — Decision tree from “timing pain” to Separate vs Combo vs Full isolated driver.

Request a Quote

Name

Company

Part Number(s) / BOM

Quantity & Target Lead Time

Alternates Allowed

Temperature Grade

Package / Footprint

Compliance

Budget Window

Lot Size / Qty

Message

Attachment

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

H2-13 · FAQs (Field Debug & Acceptance Criteria)

Scope: field troubleshooting and acceptance criteria only. All answers stay within this page boundary: timing/skew budgets, input robustness, VDD1/VDD2 noise coupling, CMTI false-trigger behavior, and protection partitioning.

Format: Likely cause / Quick check / Fix / Pass criteria Data: X/Y/N placeholders are mandatory No new domains: no standards primer, no device physics lecture

1) Skew looks fine in the lab, but phase current sharing is still uneven—first suspect what?

Likely cause: skew was verified at a different reference point than the power-stage edge (DIN→GOUT vs GOUT→VG at the device), or only typical conditions were measured.

Quick check: measure channel-to-channel Δt at the same physical node (device gate or Kelvin-referenced VG) with identical probe chain and trigger reference.

Fix: redefine the measurement contract (node, trigger, bandwidth limit) and re-run the skew report across temperature and supply corners.

Pass criteria: ΔtPD(measured at device gate) ≤ X ns across Y temperature points; N samples/channel per point.

2) ΔtPD meets datasheet typical, but worst-case timing still fails—what definition is likely mismatched?

Likely cause: datasheet “typ” was compared to system “worst-case,” or the edge threshold definition differs (e.g., 50% crossing vs input threshold vs output slew point).

Quick check: restate the budget with explicit threshold and measurement points for each segment (controller → input shaping → barrier → output stage).

Fix: convert the budget to worst-case (min/max VDD1/VDD2, temperature, load) and allocate margin to each segment including measurement uncertainty.

Pass criteria: worst-case ΔtPD_budget ≤ X ns and measurement uncertainty ≤ Y ns; N repeats per corner.

3) Only one channel misbehaves under load—routing skew or VDD2 droop first?

Likely cause: local VDD2 droop or decoupling placement causes output drive strength and timing to shift, masquerading as “channel skew.”

Quick check: scope VDD2 at the IC pins for that channel during the failing load step and compare against a healthy channel using the same probe method.

Fix: move/upgrade VDD2 decoupling to pin-level, reduce supply loop impedance, and re-check channel timing at the device gate node.

Pass criteria: VDD2 droop ≤ X mV under Y A step; ΔtPD shift ≤ N ns vs idle condition.

4) Works with single-ended input, fails after switching to differential (or vice versa)—which immunity assumption broke?

Likely cause: return-path or common-mode noise moved the input threshold crossing timing; differential/common-mode limits were not respected at the receiver.

Quick check: measure input pin common-mode (and for differential, the pair balance) during switching events and count spurious transitions within a defined window.

Fix: enforce the recommended input wiring (short loop, controlled return), add input damping/threshold conditioning where allowed, and standardize the default/fail-safe state.

Pass criteria: spurious input transitions = 0 over X minutes; common-mode stays within Y V; N repeats across stress cases.

5) No false triggers at low dv/dt, but misfires appear at higher dv/dt—first check which coupling path?

Likely cause: barrier capacitance and return-path geometry inject common-mode current into the secondary ground, shifting input/output thresholds and creating false toggles.

Quick check: reproduce at a defined dv/dt (X kV/µs), then correlate false triggers with secondary ground bounce and input pin disturbances.

Fix: tighten secondary return, avoid copper under the barrier keep-out, improve decoupling at VDD2 pins, and reduce loop areas that convert CM current into voltage.

Pass criteria: false triggers = 0 at dv/dt = X kV/µs over Y minutes; N repeats and N boards.

6) Turning on the isolated DC-DC makes timing jitter worse—ripple fold-in or reference bounce?

Likely cause: VDD2 ripple and/or secondary ground bounce modulates the internal shaping and output stage, increasing cycle-to-cycle jitter and apparent delay drift.

Quick check: inject a controlled ripple (X mVpp at switching freq Y) and measure ΔtPD and jitter response with a fixed trigger and window.

Fix: add pin-local decoupling, reduce DC-DC output impedance, and re-route returns so ripple current does not flow through sensitive reference nodes.

Pass criteria: added jitter ≤ X ns (p-p) and ΔtPD drift ≤ Y ns at ripple = N mVpp.

7) UVLO never trips, but outputs still weaken under bursts—what supply metric is missing?

Likely cause: dynamic droop and high-frequency impedance cause momentary drive-current reduction without crossing the UVLO threshold.

Quick check: measure VDD2 droop at IC pins with high bandwidth during burst load; compare against output edge rate and gate plateau behavior.

Fix: lower supply impedance (better decoupling + shorter loop), verify DC-DC transient response, and allocate ripple/droop limits in the power budget.

Pass criteria: VDD2 droop ≤ X mV and edge-rate change ≤ Y% during burst of N cycles.

8) Two boards with the same BOM show different skew—first normalize what measurement setup detail?

Likely cause: probe loading, bandwidth limit, trigger reference, or measurement node differences dominate the reported ns-level skew.

Quick check: lock the “measurement contract” (same probe, same attenuation, same bandwidth limit, same node, same trigger threshold) and rerun both boards.

Fix: publish the measurement contract as a release artifact and require it for every acceptance run.

Pass criteria: inter-board Δ(ΔtPD) ≤ X ns using the fixed setup; Y repeats; N channels per board.

9) Intermittent shoot-through despite combo integration—what protection responsibility is most commonly missing?

Likely cause: the system assumes “combo = full protection,” but fast short-circuit response, clamp strategy, or a deterministic shutdown chain is not actually implemented.

Quick check: map protections into a matrix (built-in vs external) and time-stamp the actual disable path latency end-to-end.

Fix: add the missing external blocks (e.g., fast fault detect / clamp / shutdown gating) and validate response under fault injection.

Pass criteria: fault-to-shutdown latency ≤ X µs; no shoot-through events over Y injected faults; N repeats per condition.

10) /FLT asserts but the system still doesn’t shut down fast enough—first check which link in the shutdown chain?

Likely cause: /FLT is treated as an informational signal, while the real disable action depends on a slower path (firmware polling, slow opto, or miswired enable).

Quick check: scope /FLT, DISABLE input, and gate output simultaneously to measure fault→disable→output-off latency.

Fix: enforce a hardware interlock path for immediate disable, and keep the reporting path separate from the safety shutoff path.

Pass criteria: /FLT to output-off ≤ X µs; disable path is hardware-only; N fault injections with 0 misses.

11) CMTI rating looks high, yet the input toggles—threshold/edge conditioning or ground return first?

Likely cause: the limiting factor is not the barrier rating but board-level conversion of common-mode current into input pin voltage via return impedance.

Quick check: measure input pin waveform relative to its local return under dv/dt stress and compare against the effective input threshold window.

Fix: reduce return impedance, tighten local reference, and apply input conditioning consistent with the chosen interface mode.

Pass criteria: input pin noise stays ≥ X mV away from threshold during dv/dt = Y kV/µs; N runs with 0 false toggles.

12) EMI improves after slowing edges, but timing margin collapses—what should be re-budgeted first?

Likely cause: slew-rate change alters the effective switching event definition and increases timing uncertainty at the control boundary (threshold-crossing moves).

Quick check: re-measure timing using the same event definition (e.g., 50% VG or a defined VDS point) before and after the edge-slowing change.

Fix: update the timing budget to include event-definition sensitivity, and allocate margin for the new edge shape across channels.

Pass criteria: updated timing margin ≥ X ns across Y corners after edge shaping; N samples/channel and N boards.

Digital Isolator + Gate Driver Combo for Tight Skew

Digital Isolator + Gate Driver Combo for Tight Skew

H2-01 · Definition & Scope Boundary

Engineering Definition

Scope Contract (Anti-Overlap)

Decision Triggers (When to Use Combo)

H2-02 · Where It Fits: Multiphase & Multibridge Timing Closure

Why Tight Skew Matters (Cause → Effect)

Multiphase VR (What to Watch)

Multibridge / 3-Phase Inverters (What to Watch)

H2-03 · What’s Inside: Channel Architecture & Signal Path

Signal Path Segments (DIN → GOUT)

Per-Segment Engineering Card (Role → Error Source → Control Lever)

Why One Package Is More Controllable (ΔtPD & Drift)

Multi-Channel Organization Patterns (Structure Only)

H2-04 · Propagation Delay, Skew & Jitter: How to Budget It

Engineering Definitions (On-Page Measurement Contract)

Why Combo Budgets Close Easier

Pass-Criteria Templates (Placeholders)

H2-05 · Input Interface & Logic Robustness (SE/Diff, Thresholds, Immunity)

Input Types (Engineering Meaning)

Top Noise Mechanisms (What Causes False Triggering)

What Combo Improves (Without Becoming an Isolator Handbook)

Recommended Wiring · Short traces

Recommended Wiring · Long traces / connectors

Recommended Wiring · Harsh noise environments

H2-06 · Gate Output Stage: Peak Current, VG Range, Slew Shaping

Output-Stage Parameter Map (What Each One Controls)

Typical Design Decision Points (Speed vs EMI vs Robustness)

Common Missing Features in Combo Devices (External Implementations)

Pass-Criteria Templates (Placeholders)

H2-07 · Powering Both Sides: VDD1/VDD2, Bias Strategy & Noise

Two-Rail Contract (What Each Supply Must Guarantee)

Topology · Isolated DC-DC → VDD2 (direct)

Topology · Isolated DC-DC → LDO/Filter → VDD2 (cleaned)

Topology · Auxiliary winding / secondary rail → VDD2

Topology · Bootstrap-like supply (when applicable)

Noise → Timing Coupling (How Ripple Becomes Drift)

Datasheet Checks (Selection & Integration)

Acceptance Templates (placeholders)

H2-08 · Isolation & Package Reality: CMTI, Barrier Capacitance, Creepage

Metric (what to read)

Risk (what it breaks)

Board actions (what to do)

Acceptance Templates (placeholders)

H2-09 · Protection Partitioning: What Combo Gives You vs What You Still Need

Typically Included (common cases)

Often Missing or Incomplete (common cases)

System Shutdown Closure (placeholders)

H2-10 · Layout & EMI: Interconnect Removal Helps, But Not a Free Lunch

What Interconnect Removal Improves

Still-Game-Over Traps

EMI Trade-offs (control knobs)

Do

Don’t

H2-11 · Engineering Checklist (Design → Bring-up → Production)

H2-12 · Applications & IC Selection (Before FAQ)

Request a Quote

Accepted Formats

Attachment

H2-13 · FAQs (Field Debug & Acceptance Criteria)

Explore

Categories

Get in Touch