Gate-Transformer Driver (GDT): Push-Pull Primary, Sync Secondary
Gate-Transformer Driver is a high-isolation gate-drive approach that delivers strong, fast switching pulses through a transformer, and it wins when dv/dt is harsh and common-mode coupling must be minimized. The core success condition is guaranteed volt-second balance and reset plus matched secondary networks, so Vgs amplitude, droop, skew, and dv/dt immunity remain within acceptance limits.
H2-1. Gate-Transformer Driver — Definition & When It Wins
A gate-transformer driver (GDT) transfers gate-drive energy across an isolation barrier using magnetic coupling. It excels in high dv/dt and pulsed environments, but it imposes hard constraints on duty-cycle balance, droop, reset, and channel matching.
Scope Boundary
Coverage: push-pull excitation, volt-second balance & reset, droop mechanisms, transformer parasitics, synchronous secondary networks, channel symmetry, dv/dt coupling paths, and layout/validation hooks specific to GDT drive.
Out of scope: general digital isolator theory, isolated driver IC internals, and detailed DESAT/UVLO mechanisms. If protection behavior must be programmable and self-contained inside the driver chain, isolated driver ICs typically fit better.
Use It When (3 decision triggers)
- Common-mode stress is extreme (fast switching nodes, large dv/dt) and the goal is to minimize capacitive injection into the control side. GDT drive can reduce sensitivity to electric-field coupling, especially when the winding structure and return paths are controlled.
- Very high isolation is required and the gate side must remain floating and robust under pulsed operation. Magnetic coupling supports high isolation stacks while keeping the signal path simple.
- Drive behavior is pulse-dominant (short on/off transitions and bounded on-time) rather than “DC gate level hold”. GDT constraints align naturally with pulsed and RF-like drive patterns.
Don’t Use It When (3 hard stop conditions)
- Long gate-level hold is mandatory (very high effective duty, near-DC on-time). Without guaranteed reset, volt-second imbalance drives flux walk → saturation → gate amplitude collapse.
- Protection and diagnostics must be integrated and feature-rich inside the driver chain (advanced fault state machines, telemetry, programmable blanking). GDT systems often require more external protection architecture and validation discipline.
- Multi-channel symmetry cannot be controlled (winding mismatch, inconsistent secondary networks, uncontrolled gate loop differences), especially in half-/full-bridge hard-switching where turn-off strength and delay matching define shoot-through risk.
Decision Gate (engineering thresholds)
The following gates are meant to be auditable. Replace X/Y/N with program-specific targets after bench correlation.
Figure 1 — Three isolated high-side drive approaches. The key differentiator is where the isolation barrier sits and how bias energy reaches the gate side.
H2-2. Topology Overview: Push-Pull Primary + Synchronous Secondary
The topology is best understood as two coordinated subsystems: (1) a symmetric primary excitation that guarantees reset margin, and (2) a secondary network that shapes gate current, clamps overshoot, and enforces a strong, repeatable turn-off path.
Canonical Architecture (functional blocks)
- Primary driver stage: creates balanced push-pull excitation (symmetry is the first safety constraint).
- Gate drive transformer (GDT): provides magnetic isolation and sets droop + parasitic behavior.
- Per-switch secondary network: rectifies/shapes drive, enables fast discharge, and clamps gate stress.
- Gate interface: split Rg,on / Rg,off, optional clamp, optional −Vg rail (if required by the risk model).
- Return reference: Kelvin gate-source return is mandatory for valid Vg measurement and repeatable behavior.
Deep formulas (core selection and volt-second math) are intentionally deferred to the operating-principle chapter. This chapter locks the block-level blueprint and the “where current flows” view.
Primary Driver Stage Options (selection by constraints)
Primary excitation choices are not “feature picks”; they set symmetry control, device stress, and bring-up friction. Keep the comparison on three axes only (avoid drifting into magnetics math here).
- Push-pull: strong symmetry potential, efficient excitation; demands careful balance and reset discipline.
- Half-bridge / full-bridge: can improve controllability and stress distribution; increases complexity and layout sensitivity.
- Per-channel primary segmentation: improves channel isolation and matching at the cost of parts and routing complexity.
Synchronous Secondary Networks (three implementation families)
“Synchronous secondary” describes enforcing a controlled turn-off current path and gate clamp behavior that remains consistent across channels and operating corners. The implementation can be grouped into three families:
- Diode steering / passive shaping: simplest and robust; turn-off strength and ringing control depend heavily on parasitics and placement.
- Active synchronous discharge / clamp: tight control of turn-off and overshoot; demands disciplined layout and validated fault modes.
- Bidirectional drive + optional −Vg: strongest immunity in high dv/dt environments; requires a clean return reference and strict channel symmetry.
The critical validation question is not “which circuit is used”, but “whether the gate discharge path is low-impedance, repeatable, and channel-matched under dv/dt stress.”
Figure 2 — Standard GDT blueprint. The secondary network and Kelvin return define turn-off strength, ringing behavior, and dv/dt robustness.
H2-3. Operating Principle: Volt-Second Balance, Reset, and Why Duty-Cycle Matters
In a gate-transformer driver (GDT), predictable gate voltage depends on flux returning to its starting point every cycle. Volt-second imbalance causes flux walk, pushes the core toward saturation, and can collapse gate amplitude and turn-off strength.
Key Concepts (must-have vocabulary)
- Volt-second (V·s): time-integral of applied primary voltage. Any net imbalance accumulates into flux walk.
- Magnetizing current (Im): current that establishes flux in the core. A rising Im trend indicates shrinking reset margin.
- Reset window: time and polarity that drive flux back toward the initial point. Missing reset accelerates bias buildup.
- Core saturation symptoms: primary current spikes, gate amplitude collapse, increased channel divergence, abnormal temperature rise.
Scope rule: this chapter defines the physics constraints and validation gates only. Detailed parasitic attribution and ringing paths are handled in the equivalent-model chapter.
Causal Chain (why duty-cycle is not “free”)
- Balanced excitation requires complementary pulses with matched effective volt-seconds.
- Any imbalance (duty, amplitude, timing, load asymmetry) creates a non-zero net volt-second per cycle.
- Net volt-second accumulates into flux walk (bias shift), moving the operating point toward saturation.
- Approaching saturation reduces effective magnetizing inductance, forcing magnetizing current to surge.
- Gate delivery collapses: secondary headroom drops → Vg droop grows → turn-off margin shrinks and timing mismatches amplify.
Hard Rules (auditable gates with X/Y placeholders)
Rule 1 — Max Effective Duty
Rule: Max effective duty ≤ X% unless reset is guaranteed by symmetry and timing.
Quick check: at worst-case duty, confirm no cycle-to-cycle rise in primary current peak and no drift in Vg peak.
Fix knobs: enforce complementary pulse balance, ensure reset window, add explicit reset path if needed.
Pass criteria: primary peak current trend ≈ flat over N cycles and Vg amplitude drift ≤ Y%.
Rule 2 — Gate Droop Budget
Rule: ΔVg droop ≤ X V within Y ns/µs during worst-case on-time.
Quick check: measure Vg(t) using Kelvin gate-source; record droop slope and end-of-pulse Vg.
Fix knobs: increase effective Lm margin, reduce secondary impedance, strengthen discharge/clamp paths.
Pass criteria: droop meets X/Y and channel-to-channel droop mismatch ≤ Z%.
Rule 3 — Complementary Pulse Balance
Rule: imbalance between complementary pulses ≤ X% (effective pulse area).
Quick check: capture both primary phases; compare effective pulse width and amplitude across corners.
Fix knobs: tighten timing alignment, match drive strength, remove asymmetry in primary path and loading.
Pass criteria: area difference ≤ X% from cold to hot, and from min to max supply.
Measurement rule: Vg must be probed across Kelvin gate-source. Non-Kelvin probing can falsely report “good Vg” while actual gate margin is poor.
Fast Saturation Signatures (field-usable)
- Primary peak current grows with duty → reset window is shrinking or pulse balance is drifting.
- Vg collapses abruptly at certain duty/temperature → operating point is near saturation boundary.
- Channels diverge over time → small imbalance is integrating into flux walk; symmetry is insufficient.
- Ringing worsens as duty increases → parasitic resonance is being excited harder; proceed to equivalent-model attribution.
Figure 3 — Balanced volt-seconds enable reset and stable Vg. Imbalance accumulates flux walk, increases droop, and can drive saturation signatures.
H2-4. Transformer Equivalent Model: Leakage L, Magnetizing L, Interwinding C (and Their Failure Signatures)
The GDT behaves like a power transfer element plus a parasitic injection network. A minimal equivalent model ties field symptoms (ringing, slow turn-off, dv/dt false turn-on) to specific parasitics and the fastest verification actions.
Minimal Equivalent Model (only what matters for gate drive)
- Lm (magnetizing inductance): sets droop and reset margin. Too low → droop increases and saturation risk rises.
- Llk (leakage inductance): drives resonance with gate-loop capacitance/inductance. Higher Llk → stronger ringing and overshoot.
- Cps (primary-to-secondary capacitance): common-mode injection path under dv/dt. Higher Cps → larger gate disturbance risk.
- Cpw/Csw (winding capacitances): shapes high-frequency edges and can amplify ringing/EMI if poorly damped.
- Secondary load: shaping + clamp + split Rg and the gate loop. High impedance during turn-off increases susceptibility.
Scope rule: this chapter links parasitics to symptoms and verification actions. Protection mechanism internals (DESAT/UVLO logic) remain in protection-focused pages.
Failure Signature Cards (symptom → likely parasitic → fastest proof → fix)
Signature 1 — Slow Turn-Off Tail
Likely parasitic: Lm too small and/or turn-off discharge path too weak (effective impedance too high).
Quick check: measure Vg discharge slope (Kelvin) and compare channels; check if tail worsens at higher duty or temperature.
Fix: lower turn-off impedance, strengthen synchronous discharge/clamp path, increase Lm margin if droop is dominant.
Pass criteria: turn-off transition ≤ X ns/µs and channel-to-channel spread ≤ Y%.
Signature 2 — Vg Ringing / Overshoot
Likely parasitic: Llk resonating with gate-loop L/C; damping is insufficient or misplaced.
Quick check: step Rg,off or add series damping; if ringing frequency stays similar but amplitude changes, parasitic resonance dominates.
Fix: minimize gate loop, apply controlled damping (series R/ferrite/RC), reduce leakage excitation by layout symmetry.
Pass criteria: overshoot ≤ X V and ringing settles within Y ns.
Signature 3 — dv/dt False Turn-On
Likely parasitic: Cps injection under dv/dt plus a high-impedance gate-off state.
Quick check: dv/dt stress test with gate commanded off; measure Vgs spike magnitude and duration using Kelvin reference.
Fix: strengthen clamp/fast discharge path, reduce off-impedance, control coupling paths (shield/return strategy).
Pass criteria: at dv/dt = X kV/µs, Vgs_peak ≤ Y V (below device turn-on risk threshold).
Fast Verification Actions (no wide tables)
- Damping sweep: adjust Rg,off / add series damping and record ringing amplitude and settling time.
- Kelvin vs non-Kelvin probe: confirm measurement integrity; reject conclusions from non-Kelvin waveforms.
- Single-channel isolation: enable one channel at a time to separate transformer mismatch from layout asymmetry.
- dv/dt injection test: apply worst-case dv/dt while gate is off; log Vgs spike and recovery.
- Corner sweep: temperature and supply extremes; check whether droop and primary current signature trend toward saturation.
- Channel swap test: swap secondary networks (controlled) to determine whether the symptom follows the transformer or the channel circuitry.
Attribution rule: “same symptom, different knob response” distinguishes dominant parasitics. Damping changes ringing amplitude quickly; Lm limitations show as droop and duty sensitivity.
Figure 4 — Parasitic-to-symptom map for GDT drive. Use the fastest knob response (damping, duty sensitivity, dv/dt test) to identify the dominant path.
H2-5. Synchronous Secondary Networks: Fast Discharge, Clamp, and Optional Negative Gate
“Synchronous secondary” becomes real only when the secondary network guarantees a strong, repeatable turn-off path, clamps Vgs stress under ringing, and (when required) adds negative gate margin against dv/dt-induced false turn-on.
Core Objective (two auditable outcomes)
- Turn-off strength: Vg discharges from VON to VOFF within X ns/µs using Kelvin gate-source measurement.
- Repeatability: channel-to-channel turn-off delay/shape mismatch ≤ Y ns and Vg amplitude mismatch ≤ Z%.
Scope rule: this chapter focuses on secondary current paths and device stress. Switch-technology specifics (SiC/GaN/IGBT) are referenced only as sensitivity hints and belong to dedicated switch pages.
Current Paths & Stress Points (what must be controlled)
- Turn-on charge path: drives gate charge quickly but must not excite uncontrolled ringing. Keep turn-on and turn-off paths explicitly separated when split resistors are used.
- Turn-off discharge path: the primary safety path. Low impedance, shortest return loop, and consistent behavior across channels are mandatory.
- Clamp / reverse-current path: absorbs overshoot energy and suppresses dv/dt-induced disturbance. The clamp element must tolerate reverse gate current and peak power.
Three Implementation Families (trade-offs)
A) Diode Steering / Passive Shaping
- Speed: moderate; turn-off strength depends on effective discharge impedance and parasitics.
- Loss: diode conduction and recovery can add heating under high frequency edges.
- Complexity: low; fewer active failure modes.
- Consistency: sensitive to layout and tolerance; channel symmetry must be verified, not assumed.
Use when simplicity and robustness dominate, and when measured turn-off tail and dv/dt immunity meet X/Y acceptance gates.
B) Active Synchronous Discharge / Clamp
- Speed: strong and programmable; can enforce deterministic turn-off behavior.
- Loss: switching losses move into the clamp/discharge element; thermal design must be validated.
- Complexity: higher; introduces additional device stress and fault modes.
- Consistency: best repeatability when driven and laid out symmetrically across channels.
Prefer when false turn-on margin is tight and turn-off path must remain strong under dv/dt and temperature corners.
C) Add −Vg Rail + Clamp (optional)
- Speed: strongest off-state margin; improves robustness against dv/dt-induced gate disturbance.
- Loss: depends on clamp strategy and reverse current handling; may increase dissipated energy in the clamp path.
- Complexity: highest; −Vg reference integrity and noise control become first-class constraints.
- Consistency: requires strict symmetry and verified reference/return strategy across channels.
Consider when dv/dt tests show Vgs_spike approaching risk thresholds, or when off-state margin must be widened to meet system safety targets.
Acceptance Checkpoints (measurable gates)
- Discharge impedance: no long turn-off tail; Vg reaches VOFF within X and remains stable.
- Clamp behavior: Vgs_peak ≤ X V and ringing settles within Y ns under worst-case load.
- Reverse-current capability: clamp/discharge elements survive Irev_peak ≤ X A with acceptable temperature rise.
- Off-state dv/dt immunity: at X kV/µs, Vgs_spike ≤ Y V and no false turn-on events.
Gate sensitivity hint: devices with low Vth and high dv/dt environments typically demand stronger off-state impedance control; detailed device-specific guidance belongs to switch-technology pages.
Figure 5 — Three secondary network families. The differentiator is turn-off discharge impedance and clamp behavior under ringing and dv/dt stress.
H2-6. Timing & Symmetry: Multi-Switch Coordination, Deadtime, and Channel Matching
In multi-switch stages, symmetry is a safety specification. Small differences in winding, layout, or secondary impedance translate into measurable delay and droop mismatch, which can break deadtime assumptions and increase shoot-through risk.
Why Symmetry Is a Safety Spec
- Turn-off weaker on one leg → effective deadtime shrinks → cross-conduction risk increases.
- Turn-on delay mismatch → PWM timing resolution degrades → current ripple and loss increase.
- Vg amplitude mismatch → different effective switching speed → thermal imbalance and drift.
Validation rule: matching must be proven by measurement. Identical schematics do not guarantee identical gate waveforms.
Matching Checklist (auditable acceptance gates)
1) Turn-on Delay Matching
Measure: PWM edge → Vgs crosses a defined threshold (Kelvin TP).
Fix knobs: equalize secondary impedance, minimize gate loop differences, match drive path lengths.
Pass criteria: inter-channel Δt_on ≤ X ns across corners.
2) Turn-off Delay Matching
Measure: off command → Vgs falls below the same threshold (Kelvin TP).
Fix knobs: strengthen and match discharge paths, match clamp behavior, reduce parasitic spread.
Pass criteria: inter-channel Δt_off ≤ X ns (often the primary safety metric).
3) Vg Amplitude Matching
Measure: Vg_peak and plateau level using Kelvin gate-source probe.
Fix knobs: match winding coupling and loading, avoid asymmetric clamp engagement.
Pass criteria: |Vg_peak,ch − Vg_peak,ref| ≤ Y%.
4) Droop Slope Matching
Measure: droop slope over the same on-time window for all channels.
Fix knobs: improve Lm margin, match secondary impedance, enforce reset symmetry.
Pass criteria: droop slope mismatch ≤ Z% and no trend drift with duty.
Deadtime Gate (only the hard rule)
- Hardware interlock is mandatory for half-bridge/full-bridge coordination.
- Deadtime budget must cover worst-case turn-off skew and waveform variation.
- If matching cannot be proven, deadtime must be conservative, increasing loss and thermal stress.
Detailed deadtime strategies belong to the dedicated Deadtime & Shoot-Through Interlock page. This chapter defines the measurement gates that deadtime must cover.
Field Validation Playbook (3-step)
- Baseline capture: record all channels Vgs with Kelvin TP points under the same load and timing.
- Corner sweep: temperature, supply, and duty extremes; log Δt_on, Δt_off, Vg_peak, droop slope.
- Stress injection: dv/dt and load transients; confirm no false turn-on and no collapse of turn-off strength.
Figure 6 — Channel matching blueprint. Symmetry must be validated at identical Kelvin test points, then budgeted into deadtime and safety margins.
H2-7. Isolation & dv/dt Immunity (CMTI) — What GDT Solves, What It Doesn’t
A gate-drive transformer can reduce certain cross-domain couplings, but dv/dt immunity is still set by displacement-current paths, reference integrity, and the return loop that closes common-mode current. This chapter maps the coupling paths and the knobs that remain controllable.
Expectation Calibration
What GDT Helps
- Decouples DC bias supply crossing in some architectures (signal energy transferred magnetically).
- Supports high dv/dt environments when coupling paths are deliberately controlled (winding + layout).
- Enables compact isolated gate delivery without relying on a dedicated isolated driver IC (system choice, not a replacement).
What GDT Does Not Automatically Fix
- Cps injection: primary-to-secondary capacitance still injects displacement current under dv/dt.
- Gate reference drift: shared impedance and return mixing can lift the apparent Vgs.
- Common-mode EMI: coupling often shifts locations; the CM loop still must be engineered and verified.
Scope rule: no isolation standards, creepage/clearance, or isolated-driver CMTI scorecards here. This chapter stays on GDT-specific coupling paths and measurable immunity outcomes.
Coupling Paths (3-path map)
Path 1 — Cps Injection (dominant dv/dt path)
Source: HS switch node dv/dt.
Coupling: interwinding capacitance Cps (primary ↔ secondary).
Victim: secondary reference and gate loop.
Result: Vgs spike (gate is lifted) and larger common-mode current.
Path 2 — Shield / Layer-to-Layer Coupling (trade-off path)
Source: high field gradients around switching edges.
Coupling: shield capacitance / layer coupling changing where the CM loop closes.
Victim: secondary reference or chassis/ground depending on termination strategy.
Result: dv/dt immunity can improve, but CM EMI spectrum may shift and must be re-validated.
Path 3 — Reference Drift (return-path dominated)
Source: ground bounce and shared-impedance return under fast current edges.
Coupling: return mixing between power and gate reference paths.
Victim: gate-source reference (Kelvin integrity).
Result: measured Vgs deviates from device-effective Vgs; false turn-on risk increases.
Two Risks (measurable acceptance gates)
Verification rule: dv/dt immunity and EMI must be validated together. Improving one path can relocate the other if the CM loop closure changes.
Knobs That Stay Controllable (action → impact → trade-off)
- Reduce Cps (winding/structure): lowers displacement injection; trade-off is magnetic implementation complexity.
- Shield strategy (termination): moves CM loop closure; trade-off is EMI spectrum shift that must be re-tested.
- Kelvin return integrity: hardens Vgs reference; trade-off is stricter routing and partition constraints.
- Strong off-impedance + clamp: suppresses Vgs spikes; trade-off is clamp stress and dissipation.
- Minimize gate loop area: reduces induced voltage; trade-off is layout freedom and component placement constraints.
- Partition high dv/dt zones: reduces field coupling; trade-off is stack-up complexity and routing detours.
Figure 7 — Common-mode coupling map for GDT drive. Cps injection, shield coupling, and return mixing define Vgs spikes and EMI. Knobs mark where control remains possible.
H2-8. Primary Driver Stage Design: Drive Voltage, Current, and Core Excitation Budget
The primary stage must close an excitation and power budget: Vpri, pulse width, and frequency must deliver the required gate energy while maintaining reset margin, avoiding saturation signatures, and keeping driver and transformer losses within thermal limits.
Primary Design Inputs (what must be specified)
Drive & Timing
- Vpri: primary drive amplitude (sets excitation and transfer headroom).
- f: effective pulse repetition / switching frequency.
- Duty / pulse width: sets reset margin and droop behavior (see volt-second constraints).
Primary Switch/Stage Capability
- Ipri_peak: peak current capability and any limit strategy.
- Rds_on / Rdrive: conduction loss and edge control.
- Overlap control: prevent push-pull shoot-through under timing skew.
Constraint reminder: volt-second balance and reset margin dominate saturation risk; validation uses primary current trend and Vg stability under worst duty corners.
Excitation & Saturation Gates (auditable checks)
- Peak magnetizing / primary current: Ipri_peak ≤ X A at worst duty and temperature.
- No drift signature: no cycle-to-cycle growth of Ipri_peak over N cycles (reset margin proven).
- Waveform integrity: Vpri and Ipri edges show no abnormal collapse or clipping in the on-window.
- Thermal limit: primary-stage temperature rise ≤ X °C at steady state.
Power Budget Card (flow must close)
Validation Flow (budget-driven)
- Measure Vpri and Ipri: record waveforms and Ipri_peak under nominal and worst duty corners.
- Check reset margin: sweep duty and temperature; confirm no Ipri_peak drift over N cycles.
- Estimate budget blocks: compute placeholder P_gate and compare to measured input and thermal data.
- Thermal acceptance: confirm primary driver and transformer temperature rise meets X/Y limits at steady state.
Link rule: primary knobs (Vpri, f, duty) affect both saturation risk and coupling/EMI behavior. Any knob change must re-check dv/dt immunity gates from H2-7.
Figure 8 — Budget flow for the primary stage. Measure Vpri/Ipri and temperatures, allocate losses, and verify reset margin under worst duty corners.
H2-9. Layout & Parasitics: Gate Loop, Kelvin Return, Damping, and Measurement Points
Layout for GDT drive is not generic “good practice.” It is a defined set of loops, references, and measurement points that must stay clean under dv/dt injection. This chapter focuses on secondary-side gate loops, Kelvin reference integrity, damping choices, shield termination, and a single correct Vgs measurement method.
Board Partition (3-zone rule)
- Power loop zone: HS node and large di/dt return (noise source).
- Gate drive zone: GDT secondary + secondary shaping + gate loop (sensitive and fast-edge).
- Sense / control zone: sampling and controller references (must not be a CM loop closure point).
Hard constraint: no return current is allowed to cross partitions. Any “shortcut return” typically becomes the hidden CM loop that lifts the gate reference.
Five Hard Rules (auditable gates)
Rule 1 — Gate loop area ≤ X (relative minimization)
Quick check: gate-to-Kelvin return forms a tight loop on the same layer with immediate return adjacency.
Fix: keep the gate path and Kelvin return paired; avoid detours and long stubs in the secondary network.
Pass criteria: loop length ≤ X mm or loop area ≤ X mm² (placeholder); no partition crossing.
Rule 2 — Kelvin source return must be dedicated
Quick check: Kelvin return does not share copper/through-vias with power-source return or clamp current.
Fix: route a dedicated Kelvin reference back to the secondary reference point; keep it out of CM current closure loops.
Pass criteria: shared-impedance between Kelvin and power return ≤ X mΩ (placeholder) and no shared vias.
Rule 3 — Rg,on / Rg,off placement rule
Quick check: Rg components are placed at the gate pin side, not near the transformer or controller.
Fix: place Rg,on and Rg,off close to the gate; keep routing symmetric across channels.
Pass criteria: Rg-to-gate trace ≤ X mm; channel-to-channel placement mismatch ≤ Y mm (placeholders).
Rule 4 — Damping strategy must be explicit
Quick check: Vgs ringing is measured at Kelvin points; overshoot and settle time are recorded.
Fix: choose one primary damping knob first: series R, ferrite bead, or RC snub in the gate loop.
Pass criteria: Vgs overshoot ≤ X V and ringing settles within Y ns (placeholders) with acceptable temperature rise.
Rule 5 — Measurement point is differential Vgs (Kelvin)
Quick check: Vgs is not measured against power ground; it is measured gate-to-Kelvin source with a differential probe.
Fix: define TP_G and TP_KS at the device pins; keep these test points identical across channels.
Pass criteria: Vgs_spike and delays are repeatable within X% over N repeats (placeholders).
Minimum Measurement Point Set (standardized)
- TP_G: gate pin neighborhood (device-side).
- TP_KS: Kelvin source pin neighborhood (device-side).
- TP_SEC_REF: secondary reference near the secondary shaping network.
- TP_HS_NODE: HS node (for dv/dt reference only; not a Vgs reference).
Symmetry requirement: all channels must use the same test-point definitions to support matching gates and deadtime budgeting.
Bring-up / Production Acceptance (example gates)
- Waveform quality: Vgs overshoot ≤ X V, ringing settle ≤ Y ns.
- dv/dt immunity: dv/dt = X kV/µs with gate OFF, Vgs_spike ≤ Y V at Kelvin points.
- Channel symmetry: Δt_on and Δt_off skew ≤ X ns across corners.
Figure 9 — GDT-specific layout discipline. Partition power, gate, and control; keep Kelvin return dedicated; define TP_G/TP_KS and use differential Vgs measurement.
H2-10. Applications Playbook: Pulsed Power / RF Supplies / Very-High Isolation Stacks
This chapter is a field playbook: when GDT drive is the better choice, the minimum viable architecture, and the first validation gates. It avoids expanding into generic PFC/LLC textbooks and stays within pulsed/RF, very-high isolation stacks, and strong dv/dt environments.
Bucket 1 — Pulsed Power / RF Supplies
- When it wins: short pulses, high repetition, and isolation with low control-side burden.
- Minimum architecture: PWM/controller → primary push-pull → GDT → per-switch secondary network → gate.
- Primary constraint: reset margin and pulse symmetry under the maximum effective duty.
- First validation: Vgs overshoot ≤ X V, settle ≤ Y ns, and no Vg droop beyond X V in the on-window.
- Common signature: ringing grows with pulse width → suspect leakage + loop inductance and damping selection.
Bucket 2 — Very-High Isolation Stacks
- When it wins: stacked/segmented isolation domains where DC bias crossing is undesirable.
- Minimum architecture: isolated controller domain → primary driver local supply → GDT boundary → floating secondary gate delivery.
- Primary constraint: reference integrity and controlled CM loop closure (shield termination matters).
- First validation: TP_KS reference drift stays within X V and dv/dt-induced Vgs_spike ≤ Y V at gate OFF.
- Common signature: lab-to-lab EMI differences → suspect shield/return termination and partition crossings.
Bucket 3 — Strong dv/dt Environments
- When it wins: hard-switching nodes with dv/dt so high that reference drift and Cps injection become first-order risks.
- Minimum architecture: primary stage tuned for symmetry + secondary off-impedance strong clamp + dedicated Kelvin return.
- Primary constraint: Cps injection and CM loop closure must be engineered, not assumed.
- First validation: dv/dt = X kV/µs with gate OFF: Vgs_spike ≤ Y V and no false turn-on over N repeats.
- Common signature: emissions improve but false turn-on worsens (or vice versa) → knob moved CM loop closure location.
Practical linkage: any application bucket must pass the same Kelvin Vgs measurement rule and partition constraints defined in H2-9.
Figure 10 — Application playbook mini-blocks. Identify the isolation boundary, map the noise path, and validate the first gate before expanding the design.
