Make the page boundary unambiguous

This page focuses on timing integrity in half-bridge / full-bridge drivers—preventing cross-conduction by hardware interlock, programmable deadtime, and matched delay, with testable acceptance criteria.

What “HB/FB driver timing integrity” really means

• Interlock defines the “never both ON” rule under all input combinations (including glitches).
• Deadtime provides margin against propagation delay drift, channel skew, and edge jitter.
• Matched delay keeps leg-to-leg and channel-to-channel switching aligned for repeatable losses, EMI, and control behavior.
• Validation must confirm the absence of harmful overlap at the device conduction level, not only at logic outputs.

Deliverables of this page: (1) a timing budget template, (2) a selection checklist for interlock/deadtime/matching, and (3) a measurement-driven acceptance method suitable for bench + production.

Forbidden sideways expansion (link-out only)

• Switch-technology gate voltages & SC energy policies (SiC/GaN/IGBT/LV MOSFET) → link to the corresponding “By Switch Technology” subpages.
• Bootstrap / charge-pump mechanism and sizing → link to “High-Side Gate Driver (Bootstrap/Charge Pump)”.
• Protection mechanism tutorials (DESAT/UVLO/Miller clamp internals) → link to “Protection & Control” subpages.
• Isolation standards deep dive → link to “Isolation & Integration” subpages.

Within this page, those topics may appear only as: why it matters here + what to verify + link-out.

Cross-conduction risk metrics (template)

Use a consistent definition to avoid lab-to-lab disputes.

• Overlap time ≤ X ns (define as “effective conduction overlap,” not just HO/LO overlap).
• VBUS droop ≤ Y V (define load condition + time window).
• Hotspot rise ≤ N °C (define duration + cooling boundary).
• Overlap current spike ≤ Z A (optional but recommended for bridge bring-up).

These placeholders become the page-wide “pass criteria” language reused in later chapters and FAQs.

Gate Driver Solar-System Map (HB/FB highlighted)

Create a traceable model from PWM inputs to device conduction

A half-/full-bridge driver must be understood as a multi-domain signal path: Input domain → Logic domain → Output domain → Power device conduction. This chapter defines the nodes that later timing budgets and acceptance tests will attach to.

What each domain is responsible for

• Input domain (PWM_H / PWM_L): thresholds, noise immunity, minimum pulse width, and input mode assumptions.
• Logic domain: interlock truth table, deadtime generation, and priority arbitration (EN/SHDN/FAULT/UVLO).
• Output domain (HO/LO): peak drive current, rise/fall asymmetry, gate-network interaction, and discharge behavior under faults.
• Power domain (HS/LS device + SW node): effective conduction timing, dv/dt coupling, and cross-conduction consequences.

A “clean” HO/LO waveform does not guarantee safe operation if the device-level conduction overlap is not verified.

Three patterns and where timing failures hide

• Independent HS/LS channels + interlock: most robust; interlock must dominate under any invalid input combination.
• Complementary input mode: relies on “never both high” assumptions; vulnerable to MCU reset glitches and edge corruption.
• External deadtime vs internal deadtime: mixed implementations can create double-deadtime or deadtime cancellation if definitions differ.

Selection should prioritize predictable behavior under corner inputs, not only typical-mode performance.

Define “who wins” when safety signals assert

For bridge stages, safe behavior must be deterministic. The following semantics should be stated and validated:

• Disable dominance: EN/SHDN/FAULT must override PWM and force HO/LO into a defined OFF state.
• Symmetric shutdown: avoid leg imbalances where one device stays ON while the other turns OFF (can amplify overshoot and ringing).
• Fault-to-OFF timing: specify and test propagation from fault detection to effective gate discharge.

What to measure (and what it proves)

• Inputs: PWM edge integrity, glitch width, minimum pulse width acceptance, and threshold margin.
• Logic outputs: HO/LO edge timing, deadtime insertion, channel skew (timing only).
• Device-level evidence: VGS + IDS (double-pulse or controlled switching) to confirm no harmful overlap.
• System evidence: VBUS droop, current spikes, hotspot rise, and EMI impact during timing sweeps.

Use the same definition of “overlap” across bench and production to prevent “looks OK on scope” false conclusions.

Data-oriented placeholders for later chapters

• Input thresholds / noise margin: VIH/VIL = X/Y (placeholder).
• Minimum accepted pulse width: ≥ X ns (placeholder).
• Disable reaction time: tDISABLE ≤ X ns (placeholder).
• Output timing skew: ΔtPD ≤ Y ns (placeholder; deep budget in later chapter).

Bridge Driver Block Diagram (domains + priorities)

Turn “shoot-through risk” into a measurable timing margin

Cross-conduction risk is best managed as a worst-case timing margin. Deadtime is not a single number; it is the remaining “no-overlap window” after subtracting propagation-delay mismatch and drift.

Four timing terms (single page-wide measurement language)

• tPD(H), tPD(L): propagation delay from PWM input threshold crossing to HO/LO timing reference (use a consistent edge reference definition).
• ΔtPD: channel-to-channel mismatch (skew) between HS and LS paths under the same conditions (worst-case across corners).
• tDT: configured deadtime (internal or external insertion; definition must be consistent with the chosen insertion point).
• tJ: jitter and drift margin (cycle-to-cycle variation plus temperature/supply-induced timing movement budgeted as worst-case).

The timing reference definition must remain unchanged across bench validation and production screening to avoid “deadtime margin” disputes.

Effective deadtime is the true safety margin

The bridge is safe only if the remaining no-overlap window stays positive after subtracting worst-case mismatch and drift.

• ΔtPD_wc: maximum HS/LS skew across temperature, supply, and load conditions.
• tJ_wc: jitter/drift allowance defined as a worst-case margin (not an average).
• tMEAS: measurement-definition margin (optional but recommended) to cover reference-point and instrumentation differences.

Why timing changes with temperature, supply, and load

• Temperature: internal drive strength and logic path delay shift, moving tPD(H/L) and skew endpoints.
• Supply variation: input threshold behavior and output stage slew change, modifying the measured edge reference timing.
• Capacitive load (gate network): heavier effective load slows HO/LO transitions, increasing apparent delay and asymmetry.

Even when logic-level HO/LO appears non-overlapping, device-level conduction overlap may still occur if edge timing is evaluated without the correct drift and skew margins.

Write the timing budget as a corner-based checklist

• Step 1: define corner set (Tmin/Tmax, Vmin/Vmax, typical/max gate load).
• Step 2: measure or obtain tPD(H) and tPD(L) per corner using the same edge reference definition.
• Step 3: compute ΔtPD per corner and select ΔtPD_wc (largest magnitude).
• Step 4: allocate tJ_wc and optional tMEAS as explicit margins.
• Step 5: select tDT such that Effective Deadtime ≥ Xmargin (placeholder) for all corners.

Data placeholders (page-wide language):

• Worst-case skew budget: ΔtPD,max ≤ X ns.
• Deadtime margin rule: tDT ≥ (ΔtPD_wc + tJ_wc + Xmargin).

What each measurement proves (avoid false “scope looks OK” conclusions)

• HO/LO timing proves deadtime insertion at the driver output level.
• VGS + IDS evidence proves whether harmful conduction overlap exists at the device level.
• Corner coverage proves the margin survives temperature/supply/load drift.

Acceptance should be written in terms of measurable evidence: “Effective Deadtime stays positive under specified corners” and “no overlap current spike beyond threshold.”

HO/LO Timing Diagram (deadtime, delay, skew, overlap window)

Define a hardware safety contract: “never both ON” under any input condition

Interlock is a bridge-level safeguard that must remain correct even when PWM inputs become invalid (both asserted, glitching, or briefly non-complementary during controller reset). The goal is deterministic behavior: unsafe combinations are blocked, and safety signals dominate.

Compact truth table (rules format for mobile-safe layout)

• Rule 1: PWM_H=0, PWM_L=0 → HO=0, LO=0 (both OFF).
• Rule 2: PWM_H=1, PWM_L=0 → HO allowed, LO blocked.
• Rule 3: PWM_H=0, PWM_L=1 → LO allowed, HO blocked.
• Rule 4: PWM_H=1, PWM_L=1 → both blocked (or a defined “force-OFF priority” behavior).

The exact meaning of “blocked” must be explicit: forced OFF output state with a defined discharge behavior.

Where bridges fail even when normal PWM looks correct

• Non-complementary window: controller reset/boot can briefly violate complementary assumptions.
• Edge glitches: short pulses may be filtered by minimum pulse / debounce behavior (good), or may be partially passed (bad).
• External deadtime + internal interlock: definition mismatch can cause double-deadtime (loss) or deadtime cancellation (risk).

Interlock must remain valid in these cases because shoot-through consequences are immediate at the bus level.

Safety dominance: FAULT / UVLO / DISABLE override PWM

• Dominance: when asserted, safety signals must force HO/LO to a defined OFF state.
• Symmetry: avoid leg imbalance where one switch remains ON while the other turns OFF.
• Timing: define and verify “safety assertion → effective gate OFF” propagation.

Mechanism details (UVLO/DESAT internals) are link-out topics; this page defines behavior and acceptance only.

Write interlock requirements as measurable test conditions

• Interlock reaction time ≤ X ns (input enters forbidden state → HO/LO effectively OFF at the chosen gate reference threshold).
• Glitch reject width ≥ Y ns (pulses shorter than Y ns do not create effective HO/LO conduction under the chosen definition).
• Forced-OFF dominance: safety signals override PWM regardless of its state (validated with injected fault patterns).

Minimal test loop to prevent field failures

• Inject invalid inputs: PWM_H=1 & PWM_L=1, reset-time non-complementary windows, and controlled glitch widths.
• Observe outputs: HO/LO timing plus a device-level sanity check (at least VGS evidence) for “effective OFF.”
• Record limits: reaction time and reject width become production screening limits and documentation hooks.

Interlock Priority & State Flow (inputs → interlock → outputs; safety dominates)

Treat deadtime as an engineered margin, not a fixed number

Programmable deadtime must remain valid across temperature, supply, and load corners. The objective is to select a generation method, calibrate with measurable signals, and reserve enough guardband so the effective deadtime stays positive.

Three deadtime insertion locations (bridge context only)

• Controller-generated (MCU/FPGA): highly flexible; requires robust handling of reset/glitch windows and must be backed by hardware interlock behavior.
• Driver-internal programmable deadtime: consistent definition near the outputs; tuning is quantized by step size and subject to drift.
• Hybrid (coarse external + fine internal): enables system-level control with device-level correction; must avoid double-deadtime or definition mismatch.

Selection is based on where timing is guaranteed and how the insertion definition is verified, not only on nominal features.

Deadtime too small vs too large (observable consequences)

The practical target is the smallest deadtime that still preserves a positive effective deadtime margin at all corners.

Deadtime sweep as a closed-loop engineering procedure

• Sweep input: tDT from A ns to B ns with step size = step (placeholder).
• Record risk signals: overlap current spike, bus droop, abnormal fault triggers.
• Record loss signals: switching loss trend, thermal rise trend, efficiency trend.
• Record compliance signals: EMI spectrum trend under repeatable conditions.
• Choose setpoint: the smallest tDT that clears risk limits with an added drift guardband.

The sweep output should be saved as a tuning artifact: “chosen tDT + measured margins + corner conditions.”

Keep effective deadtime positive after drift

Deadtime must cover delay mismatch and jitter under worst-case drift. Use a guardband rule aligned with the timing model:

Drift discussion remains at the behavior level; mechanism deep dives are link-out topics.

Make deadtime programmable features verifiable

• Step size ≤ X ns: verify by configured setting versus measured HO/LO timing reference delta (fixed definition).
• Accuracy/drift ±Y ns over temp: verify at Tmin/Tmax with a fixed reference point and consistent load condition.
• Corner pass: effective deadtime remains positive with documented guardband under defined corners.

These metrics convert programmable deadtime from “feature checkboxes” into production-grade requirements.

Deadtime Tuning Closed Loop (set → measure → adjust → accept)

Make delay matching verifiable and application-relevant

Channel-to-channel skew and cycle-to-cycle jitter directly shift effective switching instants. Bridge systems require repeatable symmetry: mismatched timing alters loss distribution, EMI signatures, and system consistency.

Bridges amplify timing asymmetry

• 3-phase stacks: phase-to-phase timing offsets increase current ripple and torque ripple, and shift thermal stress distribution.
• LLC / resonant bridges: symmetry loss modifies ZVS/ZCS window behavior and often worsens EMI signatures.
• Multi-bridge systems: skew accumulates across legs and channels, creating inconsistent switching edges across the system.

This section stays at timing consequences only; control-law deep dives are link-out topics.

Separate skew from jitter, and separate path segments

• ΔtCH (channel-to-channel): HS vs LS timing mismatch; and leg-to-leg mismatch within multi-channel drivers.
• ΔtPATH (path skew): segment contributions from controller → (isolation optional) → driver logic → output stage → gate network.
• tJ (cycle-to-cycle jitter): repeatability metric; define RMS/peak consistently for budget and acceptance.

Datasheet comparisons must use identical definitions; otherwise skew/jitter numbers are not comparable.

Measurement methods that produce defensible skew numbers

• Same-phase stimulus: drive HS and LS paths (or multiple legs) with the same input edge to isolate channel delay mismatch.
• Fixed reference point: measure time to a consistent edge reference (same threshold definition) to avoid slope-dependent artifacts.
• Multi-leg comparison: compare A/B/C legs under the same load and probe method to capture symmetry.
• Jitter capture: record cycle-to-cycle variation and report RMS/peak using the same time window and sampling method.

Probe technique and load symmetry strongly influence measured timing; verification should use a repeatable fixture.

Prove matching holds across temperature and supply drift

• Tmin / Tmax: confirm skew does not expand beyond requirement under temperature drift.
• Vmin / Vmax: confirm output stage and logic timing sensitivity does not break matching.
• Gate load variation: confirm timing reference definition remains stable under slope changes.

Write skew/jitter as application-bucket requirements

• Skew: Δt ≤ X ns (placeholder; choose X by application bucket such as high-sensitivity resonant bridges vs general inverters).
• Jitter: RMS ≤ Y ns and Peak ≤ Y’ ns (placeholders; must align with the timing budget).
• Path budget: ΔtTOTAL = ΣΔti across segments; each segment must be measurable or bounded.

Requirements should be budget-driven and verifiable, not only based on nominal datasheet values.

Skew Budget Chain (segment contributions add up)

Control dv/dt, EMI, and false turn-on through the gate network

In bridge systems, “stronger drive” is not always safer. Gate drive strength and slew shaping must be tuned so the switching node remains controllable while interlock safety is preserved at the device level.

Peak drive current vs Qg (engineering estimate)

A first-pass sizing rule links peak driver capability to the desired edge time:

Smaller target(tr) increases dv/dt and typically raises EMI and false turn-on sensitivity in bridges.

Split Rg(on/off) improves bridge safety and repeatability

• Rg,on: shapes turn-on dv/dt and reduces EMI excitation at the switching node.
• Rg,off: shapes turn-off behavior to reduce false turn-on risk and limit VGS rebound.
• Symmetry rule: maintain consistent gate network intent across upper and lower devices to avoid leg-to-leg imbalance.

Gate shaping must be validated by device-level evidence (VGS behavior and absence of overlap current signatures).

When two-level turn-on/off helps in bridges (usage + acceptance)

• Use case signals: strong SW node ringing, EMI failures, or repeated false turn-on sensitivity under high dv/dt.
• Bridge effect goal: keep the critical transition short, then soften the edge to reduce ringing and EMI.
• Acceptance: dv/dt and ringing meet targets without introducing excessive thermal rise or efficiency loss.

Mechanism deep dives for two-level drive remain link-out topics; this section focuses on bridge applicability and verification.

Lock measurement definitions to prevent bench-to-field disputes

• dv/dt limit: dv/dt ≤ X kV/µs using a fixed definition (e.g., 20–80% slope) and fixed operating corner (placeholders).
• Ringing limit: VGS ringing pk-pk ≤ Y V measured with Kelvin-source reference (placeholder).
• Overshoot/undershoot (optional placeholders): VGS overshoot ≤ A V, VGS undershoot ≥ −B V.
• False turn-on evidence: VGS does not cross the turn-on threshold during the off interval, and no abnormal overlap-current signature is observed (placeholders).

Common failure patterns and the first check

• EMI worsens after “stronger driver”: first check gate loop inductance and whether Rg,on is too small for the layout.
• Interlock looks correct but shoot-through still occurs: first check VGS rebound and false turn-on evidence using Kelvin reference.
• Upper/lower devices run at different temperatures: first check asymmetric gate networks and non-mirrored gate return paths.
• Only one leg is noisy: first check that leg’s gate loop area and local return integrity.

Gate Loop + Split Rg + Kelvin Source (bridge layout concept)

Select HS bias by bridge operating constraints, not by habit

High-side bias choices must be driven by bridge behavior: duty range, refresh availability, stop-and-hold requirements, and dv/dt stress. This section defines the constraints and acceptance templates without diving into component-level calculations.

Three operating states that stress HS bias

• High duty / near-DC on-time: limited refresh opportunities for bootstrap-style biasing.
• Low frequency / stop-and-hold behavior: requires HS bias to remain valid without frequent switching activity.
• Regeneration / reverse power behavior: alters expected switching patterns and can break refresh assumptions.

The correct bias method is the one that maintains a predictable UVLO and output state through these conditions.

Bootstrap vs charge pump vs isolated bias (fit boundaries)

• Bootstrap: best when refresh is guaranteed; constrained by duty, frequency, and stop-and-hold requirements.
• Charge pump (CP): improves low-frequency and high-duty behavior; limited by capability and ripple boundaries.
• Isolated bias: supports long HS on-time and high dv/dt systems; requires noise management and adds cost/complexity.

Component-level sizing and recovery mechanisms remain link-out topics; this section stays at the bridge constraint level.

Typical failures and the first check

• Works at speed, fails on stop-and-hold: first check whether the refresh requirement is met.
• High duty triggers random HS dropouts: first check HS UVLO thresholds and hysteresis versus the bias droop profile.
• Regen behavior causes non-repeatable faults: first check bias validity during mode transitions and the UVLO state timeline.

Write HS bias requirements in measurable terms

• HS UVLO behavior: VON/VOFF = X/Y V with defined output state when VOFF is crossed (placeholder).
• Refresh requirement: minimum switching activity over Y ms to keep HS bias valid (placeholder).
• Hold droop (optional placeholder): HS bias droop during hold ≤ A V.
• Ripple coupling (optional placeholder): bias ripple coupling into gate/control ≤ B (unit placeholder).

Minimum operating scenarios to validate HS bias choices

• High duty: near-DC HS on-time behavior with verified UVLO stability.
• Low frequency / stop-and-hold: verify bias hold margin and recovery behavior.
• Regen / reverse power: verify bias validity across transitions and confirm predictable fault handling.

Each scenario should produce a recorded UVLO timeline and bias waveform evidence for acceptance.

HS Bias Decision (bridge constraints → recommended method)

Shut down safely and consistently to prevent secondary disasters

In bridge systems, fault handling must guarantee a predictable safe state. The most dangerous outcome is an inconsistent shutdown where one device is forced off while the complementary device briefly re-enables due to ringing, bounce, or timing ambiguity.

Classify faults by bridge-required output behavior (not by mechanism)

• UVLO: outputs must be forced to a safe state and only recover under defined VON/VOFF behavior.
• OC/SC: shutdown must minimize destructive energy while controlling overshoot and ringing risk.
• OT: recovery must avoid thermal oscillation and repeated stress events.
• DESAT (named only): treated as a fast short-circuit trigger; blanking/filter tutorials are link-out topics.

This section defines required bridge behaviors and acceptance windows without expanding detection circuitry details.

Hard turn-off vs soft turn-off (bridge consequences)

Strategy selection is driven by the worst-case balance between short-circuit energy and overshoot/ringing risk.

Latch vs auto-retry (why inverter/traction choices differ)

• Latch: preferred when repeated retries can accumulate damage or when manual inspection and logging are required.
• Auto-retry: preferred when faults are plausibly transient and system availability is critical; requires bounded retry rules (placeholders).
• Bridge risk focus: avoid rapid on/off oscillation that creates thermal and electrical stress cycling.

Define timing requirements end-to-end (requirements, not implementation)

• Path definition: Detect → Logic/Priority → (Isolation optional) → HO/LO force-safe.
• Timing: fault propagation time ≤ X µs and safe turn-off window ≤ Y µs (placeholders).
• Verification: apply a repeatable fault stimulus and measure to a fixed HO/LO safe-state reference point.

Write shutdown as sign-off clauses

• Propagation: tPROP ≤ X µs (placeholder).
• Shutdown window: tSAFE ≤ Y µs (placeholder).
• No retrigger evidence: during shutdown, HO/LO remain forced-safe and no spurious re-enable evidence is observed (placeholder).
• Bus protection coupling: post-shutdown overshoot is controlled by external clamp/absorber within a defined limit (placeholder; external only).

Fault Propagation & Safe Shutdown Path (detect → logic → outputs → power → bus clamp)

Prevent parasitics from breaking timing, interlock safety, and false turn-on margins

Bridge layouts can invalidate timing assumptions. Parasitic inductance and return-path coupling can create gate bounce and ground bounce, shifting effective thresholds and enabling spurious edges even when logic interlock is correct.

Minimize the loops that inject SW node stress into logic and gates

• Gate loop: controls VGS rebound and false turn-on sensitivity.
• Power loop: sets di/dt overshoot sources and ground-bounce severity.
• Switch-node (SW) coupling loop: defines dv/dt electric-field injection into nearby traces and reference nets.

Each loop must be treated as a first-order safety and repeatability constraint, not a cosmetic routing detail.

Kelvin source/emitter is a bridge-critical requirement

• Reference integrity: keeps the driver’s VGS reference away from power return voltage spikes.
• Turn-off robustness: reduces the chance that VGS is lifted during high dv/dt and high di/dt events.
• Measurement consistency: enables repeatable acceptance measurements tied to a stable reference point.

Enforce leg-to-leg and HS/LS consistency

• Geometry symmetry: match gate loop length and return topology between complementary devices.
• Network symmetry: place and connect Rg,on/off and other gate elements consistently across legs.
• Thermal symmetry: avoid systematic temperature deltas that drift timing and switching behavior.

Bridge-only rules (no full grounding theory)

• SW keep-out: treat SW node as a high dv/dt zone; avoid routing sensitive signals and references through its coupling region.
• Driver reference: prevent power returns from crossing the driver logic reference domain.
• Isolation boundary (if present): keep cross-domain signaling away from SW node and enforce controlled return behavior.

Turn layout into reviewable acceptance items

• Gate loop inductance: target Lg ≤ X nH (placeholder), supported by geometry review and correlation evidence.
• HO/LO loop area: target Area ≤ Y mm² (placeholder), verified by annotated layout screenshots.
• Optional placeholders: SW keep-out distance ≥ A mm, gate-trace match within B mm.

These items enable consistent design reviews and prevent subjective “layout looks fine” conclusions.

Partition & Return Keep-Out Map (power / driver / control)

A gated, repeatable validation pipeline with sign-off evidence

Bring-up must convert timing, interlock, bias, fault, and layout assumptions into measurable evidence. Each gate produces a defined artifact set (tables, scope screenshots, logs, configuration snapshots) to prevent bench-to-field ambiguity.

Lock budgets, policies, and operating coverage before power-up

• Timing budget sheet: tDT, tPD(H/L), ΔtPD, tJ, Effective deadtime with worst-case margin placeholders.
• Fault policy sheet: force-safe state, tPROP, tSAFE, latch vs auto-retry rules (bridge semantics only).
• HS bias coverage matrix: duty/frequency/stop-hold/regen conditions mapped to HS bias feasibility (bootstrap/charge pump/isolated).
• Evidence folder: the three sheets above plus a single-page sign-off checklist.

Find the overlap boundary and the loss-optimal region with repeatable waveforms

• Pulse validation: double-pulse or half-bridge pulse test to capture switching transitions and current signatures.
• Deadtime sweep: sweep tDT to identify (1) shoot-through boundary and (2) loss-optimal region (placeholders).
• Corner repeats: repeat across temperature and bus voltage corners to expose drift and mismatch (placeholders).
• Required captures: HO, LO, VGS_H, VGS_L (Kelvin reference), SW node, ID/current spike window.

Tune dv/dt and ringing without eroding effective deadtime margin

• dv/dt target: set an edge-rate target and confirm the safety margin remains positive after tuning (placeholders).
• Split Rg(on/off): shape turn-on vs turn-off independently for EMI and false turn-on robustness.
• Return-path check: verify SW node keep-out discipline and driver reference integrity (bridge-only rules).
• Evidence package: pre/post comparison of dv/dt, gate ringing, SW overshoot, and EMI scan delta (placeholders).

Fault injection + consistency sampling for manufacturing readiness

• Fault injection set: EN disable, UVLO crossing simulation, short-circuit protection trigger (evidence only; mechanism is out-of-scope).
• Consistency sampling: spot-check deadtime, skew, and disable response time across units and temperature windows (placeholders).
• Traceability: archive configuration snapshots, logs, and “golden” scope screenshots for audit and service workflows.

Copy/paste sign-off clauses (placeholders)

• Overlap: No overlap current spike > X A in the defined commutation window.
• Overshoot: Switch-node overshoot < Y V under worst-case bus voltage and layout condition.
• Skew: Channel skew < N ns across temperature range and supply corners.
• Fault timing: tPROP ≤ X µs and tSAFE ≤ Y µs for the injected fault set.
• Ringing: Gate ringing pk-pk ≤ Z V with the production gate network.

Concrete part numbers for repeatable bench setups (reference only)

The following part numbers are commonly used as reference drivers for bring-up and comparison. Final selection must follow the timing/interlock/fault requirements defined in this page.

• Bootstrap HB driver (reference): Infineon (IR) IRS21867
• Classic HO/LO driver (reference): Infineon (IR) IR2110
• Non-isolated HS/LS MOSFET driver: TI UCC27714
• Non-isolated half-bridge driver: onsemi NCP5106
• Isolated dual-channel gate driver: TI UCC21520, TI UCC21530
• Isolated driver (iCoupler class): Analog Devices ADuM3223
• Isolated driver: Silicon Labs Si8233
• Isolated driver: onsemi NCP51530

Validation Pipeline (Design → Bench → EMI → Production) and evidence outputs

Application notes constrained to bridge-driver timing, interlock, and safe shutdown

This section maps each application to bridge-driver-critical constraints only: deadtime margin, channel skew, and fault reaction. Control theory and topology tutorials are intentionally out-of-scope.

FOC · LLC · Inverters (three cards, each with 3 must-meet placeholders)

Concrete part numbers mapped to bridge-critical needs (reference only)

The lists below provide concrete part numbers often used as reference points for each application class. Final selection must follow the page metrics (deadtime, skew, fault reaction, dv/dt robustness) rather than brand preference.

Application Mapping (FOC / LLC / Inverter → Deadtime / Skew / Fault reaction)

These FAQs close only on field troubleshooting and sign-off disputes for half-/full-bridge drivers. Each answer follows a fixed, measurable 4-line format and does not introduce new knowledge domains.