Definition: the “floating reference” driver

A high-side gate driver is a driver whose output reference is not system ground. Instead, the driver “rides” on the high-side device source/emitter, which follows the switch node (SW). The controlled quantity is therefore VGS = VG − VS, while VS can jump rapidly during switching.

Practical implication: the problem is not “PWM to gate voltage,” but “stable gate voltage and timing in a moving reference frame.”

High-side vs low-side: what changes (engineering view)

• Reference node: Low-side output is ground-referenced; high-side output is referenced to the SW node.
• Bias supply: High-side needs a floating bias (bootstrap or charge pump) that remains valid while VS is moving.
• Command transport: Input control must cross a shifting common-mode via level shifting and robust timing/interlock logic.
• Noise mechanism: SW dv/dt can couple into the gate loop and control path, causing false turn-on unless properly mitigated.

When high-side driving is required (trigger checklist)

• Half-bridge / full-bridge / 3-phase: the upper device source is the switching midpoint → reference is floating by definition.
• High-side power switch (load switch / hot-side stage): the controlled device sits between the supply rail and the load → gate drive must float with the source.
• High-side synchronous rectification: the SR device reference is not ground under operating conditions → floating gate control is required.

Core constraint set (this page’s routing map)

• Floating bias availability: can the design guarantee sufficient bias during the entire HS on-time? (Bootstrap refresh vs charge-pump continuity—expanded in H2-2 and later chapters.)
• dv/dt immunity path: SW dv/dt → parasitic coupling → gate voltage disturbance → false turn-on risk. (Mechanism and mitigations are covered later; here only the constraint is defined.)
• Level-shift + interlock correctness: command transport and shoot-through prevention must remain deterministic under switching noise.
• Duty/refresh limit: bootstrap drivers require regular opportunities to recharge; “near-100% duty” is an architectural red flag.

The single most important divider: refresh availability

The architectural question is not “which driver is stronger,” but: Can the system guarantee regular opportunities to replenish high-side bias? If the answer is “no” (near-100% duty, long HS on-time, very low switching activity, or extended high-side hold), then a pure bootstrap approach becomes structurally fragile regardless of capacitor size.

Compact map (what changes, what does not)

• Bootstrap bias is opportunistic: bias is replenished mainly when SW is pulled low (or LS is on), so the design inherits a refresh constraint.
• Charge-pump bias is more continuous: bias can exist without requiring SW-low windows, but it is bounded by pump capability and may introduce bias ripple/noise that must be managed.
• What does not change: both architectures still require robust level shifting, deterministic interlock/deadtime, and dv/dt-immune gate loops.

Failure-mode fingerprints (fast diagnosis + selection hints)

• Bootstrap signature: VBS droop grows with on-time; behavior worsens at low switching frequency or long HS hold; UVLO may chatter or release late.
• Charge-pump signature: bias remains present but sags under heavy demand or shows ripple sensitivity; thermal rise may correlate with pump activity or regulation losses.
• System signature: if switching patterns include extended “no-refresh” windows, architecture choice dominates more than component tweaks.

Decision rule (minimal, actionable)

• If SW-low refresh windows are guaranteed (regular LS conduction / midpoint low intervals) → bootstrap is usually the simplest and most BOM-efficient bias path.
• If refresh cannot be guaranteed (near-100% duty, long HS on-time, low activity, or HS hold at startup) → charge pump (or another continuous bias method) becomes the safer architecture choice.
• If startup requires immediate HS control before normal switching begins → precharge strategy and UVLO behavior become first-order constraints (covered in later sections).

Next chapters (not expanded here) will turn this map into engineering gates: bootstrap charge budget, UVLO/startup behavior, timing/interlock, and dv/dt immunity validation.

Unify the vocabulary: the floating bias is VBS

In a bootstrap high-side driver, the high-side “supply” is not ground-referenced. The useful quantity is the driver’s floating bias: VBS (high-side bias rail relative to the switching node). A convenient identity for analysis is: VBS = VBOOT − VSW, where VSW is the switch node.

Engineering consequence: any internal gate-drive logic gates (e.g., UVLO) effectively depend on VBS staying above a minimum during high-side on-time.

Two-phase operation: bootstrap is a “recharge-then-spend” system

• Phase A (Recharge): when VSW is low enough, the bootstrap diode conducts and Cboot is replenished. This happens during low-side conduction or any interval that pulls the switch node close to the return.
• Phase B (Spend): when the high-side switch turns on, the driver island rises with VSW, and Cboot supplies energy to the driver and gate output. During this interval, VBS typically droops.

Charge-conservation model: what consumes bootstrap charge

During a high-side on-time interval (Ton), the bootstrap capacitor must supply an effective charge sum:

• Gate-related demand (Qg_total): the effective gate charge the driver must deliver under operating conditions (including any internal/aux load tied to VBS).
• Driver bias current (IQBS × Ton): high-side driver quiescent + operating bias draw while the island is active.
• Leakage budget (Ileak_total × Ton): bootstrap diode reverse leakage, capacitor leakage, switch-related leakage paths, and any bias-sense paths.
• Transient loss terms: voltage loss through diode drop and instantaneous droop caused by Cboot ESR/ESL during fast current edges.

Why duty-cycle and low-frequency limits exist (the “refresh constraint”)

Bootstrap reliability is not determined by capacitor size alone. It is determined by whether the system can provide a refresh window that is frequent enough and deep enough (VSW sufficiently low) to restore the charge spent during Ton.

• Near-100% duty or long HS hold: refresh windows disappear → Cboot only discharges → VBS trends downward over time.
• Low switching activity / low frequency: the time between refresh events increases → IQBS and leakage dominate → droop grows even if Qg looks “reasonable.”
• Insufficient SW-low depth: if VSW cannot be pulled close enough to return, the diode may not conduct effectively → recharge becomes incomplete.

Practical prioritization: which term usually dominates

• High frequency / high switching: gate-related demand (Qg_total) becomes dominant.
• Low frequency / long on-time: bias current and leakage (IQBS, Ileak_total) become dominant.
• Noisy edges / large current spikes: ESR/ESL transient dips become visible (may appear as “random” issues unless the phase model is applied).

Sizing rule (first-pass, conservative)

A practical bootstrap sizing starting point is: Cboot ≥ (Qg_total + IQBS·Ton + Ileak_total·Ton) / ΔV

• Qg_total: effective gate-related charge demand under operating conditions (use worst-case when uncertain).
• IQBS: high-side driver bias current from the driver datasheet (floating bias domain).
• Ileak_total: sum of diode reverse leakage, capacitor leakage, and any bias-domain leakage paths (temperature-sensitive).
• Ton: maximum continuous high-side on-time that must be supported without refresh.

Define ΔV using bias margin (not guesswork)

ΔV should represent the allowed bias droop before the driver’s bias gate is threatened. A robust way to define it is to build a margin chain:

• Start bias: VBS_start ≈ VDD − Vdiode − Vloss_charge (diode drop and any recharge-path losses determine the top-of-charge level).
• Minimum required bias: VBS_min_req = VBS_UVLO_off + Margin (margin covers noise, temperature drift, measurement uncertainty, and transient dips).
• Available droop: ΔV = VBS_start − VBS_min_req

Bootstrap diode selection: optimize for the recharge problem

• Forward drop (Vf): reduces VBS_start, directly shrinking ΔV.
• Reverse leakage (Ir): grows at temperature; it belongs in Ileak_total, especially for low-frequency or long-hold cases.
• Reverse recovery (trr): can worsen recharge current spikes and coupling; treat it as a recharge-path quality metric (details of dv/dt immunity are handled later).
• Voltage rating: must cover the bootstrap node stress and transients with margin.

Cboot choice: capacitance is necessary, ESR/ESL explains the spikes

• Capacitance value: set by the sizing equation with margin for tolerance and aging.
• ESR/ESL: sets instantaneous dips and recharge pulse shape; high ESR/ESL increases peak losses and may create apparent “random” instability.
• Temperature behavior: effective capacitance changes with dielectric and temperature; treat it as a worst-case C when sizing.

Optional current limiting (Rlim): trade recharge spikes for recharge speed

The bootstrap recharge event is often a current pulse. Adding a small series resistor can reduce peak current and EMI, but it also slows recharge and can violate refresh requirements when the available SW-low window is short.

• No Rlim: faster recharge, larger peak current spike.
• With Rlim: smaller spike, slower recharge; must not consume the refresh window budget.
• Placement: typically in the recharge path (VDD→Dboot→Cboot); the exact location is chosen to shape pulse without harming bias start level.

Selection trigger: bias availability dominates when refresh is not guaranteed

• Near-100% duty / long HS hold: bootstrap loses its recharge window → bias droop accumulates.
• Low switching activity / burst / idle: refresh becomes sporadic → leakage and bias draw dominate between refresh events.
• Startup constraints: if HS action is needed before stable switching begins, continuous bias ramps are often more deterministic (startup gates are handled in H2-6).

Two boundaries define a charge pump: average current and ripple

A charge pump provides a more continuous high-side bias, but it is constrained by: average bias current capability and bias ripple amplitude.

• Average current boundary: the pump must supply the required average bias draw: driver bias (IQBS) + leakage + any bias-domain overhead. If Iavg_available < Iavg_required, the bias rail sags even without “missing refresh.”
• Ripple boundary: pumping is a switched charge transfer process; ripple is natural. Ripple reduces effective margin because the relevant safety condition is VBS_min, not VBS average.

Regulation (if present): what improves and what it costs

• What improves: regulation reduces ripple and makes bias thresholds cleaner and more repeatable.
• What it costs: dropout headroom and power loss. If pump capability is tight, regulation can exit its control region and bias will sag.
• Practical rule: regulated bias behaves “more DC-like,” while unregulated bias trades higher ripple for lower loss and potentially higher usable average headroom.

UVLO must be treated as two gates, not one number

• UVLO_ON: the bias level above which the driver is allowed to enter a controllable region.
• UVLO_OFF: the bias level below which the driver must force a safe-off state.
• Hysteresis: prevents chatter when bias ramps or ripples near the threshold.

Startup strategies (architecture-agnostic)

• Force a refresh opportunity (bootstrap-friendly): create SW-low intervals early so Cboot reaches a stable bias before enabling HS action.
• Wait for bias ready (pump-friendly): allow the pump/reg to ramp VBS above UVLO_ON, then enable switching.
• Hard gate the first pulse: HS gate permission must be conditional on VBS_ready (threshold + settling time), not only on PWM enable.

The most dangerous failure: partial drive and linear-region heating

If the first high-side pulse is allowed when VBS is insufficient, the effective gate drive can be too low. The high-side device may enter a linear region with high dissipation: insufficient gate voltage → higher on-resistance / higher VDS → I×V loss spikes → rapid heating and protection events.

Pass/Fail placeholders (objective bring-up gates)

• Bias margin: VBS_margin ≥ X V (relative to UVLO gates; define margins separately for ON and OFF).
• Startup time: t_start ≤ Y ms (power-on to READY state).
• No UVLO chatter: threshold crossings within the startup window must be below an allowed count/time (placeholder).
• Thermal sanity: no abnormal heating during the first pulse sequence (placeholder limit).

Deadtime must be defined at the output: tDT_eff

Deadtime is only meaningful at the outputs. A practical decomposition is:

• tDT_cmd: deadtime inserted by the PWM source (controller logic).
• tDT_drv: deadtime or blanking enforced inside the driver (hardware-level).
• tDT_eff: the effective non-overlap seen at HS_out and LS_out after propagation delays, skew, jitter, and drift.

Propagation delay and matching define the non-overlap budget

The timing budget must treat turn-on and turn-off as separate paths. Use placeholders to budget worst-case skew and drift:

• tPD_HS_on / tPD_HS_off and tPD_LS_on / tPD_LS_off are not identical.
• skew is the worst-case difference between HS and LS paths (evaluate on/off separately).
• jitter + PVT drift adds uncertainty (temperature, VDD, process, load).

Hardware interlock must override inputs (last-line protection)

• Hardware interlock: prevents HS and LS from being on simultaneously even if both inputs assert.
• Software logic: can be defeated by glitches, reset boundaries, or unexpected input overlap.
• Verification implication: include a deliberate overlap test case at inputs and confirm outputs never overlap.

Level-shift robustness: prevent false turn-on from noise-coupled triggers

In high-side drivers, the reference rides on the switching node. Noise coupling can create false internal transitions unless robustness features exist:

• Input deglitch / minimum pulse filtering: rejects narrow spikes.
• Blanking windows: blocks transitions during sensitive level-shift intervals.
• UVLO gate priority: if bias is not ready, HS output remains blocked (startup logic is covered in H2-6).
• Fault override priority: /EN or /FLT forces safe state regardless of input.

Pass/Fail placeholders (timing & overlap)

• Effective deadtime: tDT_eff(min) ≥ X ns (across PVT).
• Skew limit: skew(max) ≤ Y ns (evaluate on/off separately).
• No overlap: HS_out and LS_out never overlap under worst-case input overlap patterns (N cycles / window).
• Glitch immunity: under specified dv/dt conditions (placeholder), no false output pulses beyond the allowed width/count.

Root-cause view: false turn-on is a VGS problem

High-side immunity must be evaluated in the device’s local reference frame. The relevant quantity is VGS (gate relative to source), not gate relative to system ground. Under fast SW dv/dt, several mechanisms can momentarily raise VGS.

Three coupling paths (high-side critical)

• Path-1: Miller injection (Cgd). SW dv/dt drives current through Cgd into the gate node, pushing VGS upward during turn-off.
• Path-2: Gate loop impedance (Rg_off + Lg). The injected current creates a transient across the gate loop impedance, shaping a VGS spike.
• Path-3: Source reference bounce (common source inductance). Source/return movement shifts the local reference, effectively increasing measured VGS at the device.

Using CMTI / dv/dt specs (selection and verification gates)

• Define expected dv/dt: dv/dt_expected = ΔV / tr (placeholder).
• Select margin: ensure CMTI_spec ≥ M × dv/dt_expected (placeholder margin M).
• Verify behavior: under worst-case dv/dt, no false output pulses and VGS spikes remain below the allowed limit.

Countermeasure map (what each knob blocks)

• Active Miller clamp: provides a low-impedance gate-to-source clamp during turn-off, suppressing Path-1/2 by steering injected current away from raising VGS.
• Strong turn-off (Rg_off, split Rg): lowers effective gate impedance during turn-off, reducing Path-2 spike amplitude.
• Negative VGOFF (placeholder): increases turn-off margin so residual spikes are less likely to cross the threshold.
• Kelvin source reference: reduces Path-3 reference movement by separating sensing/driver return from power source inductance.
• Gate loop minimization (principle only): reduce loop impedance to limit spike formation (routing details handled later).

Pass/Fail placeholders (false turn-on immunity)

• VGS spike: VGS_spike(max) ≤ (Vth_min − X V) (placeholder margin).
• No false pulses: under dv/dt_expected, HS_out shows no unintended pulses beyond allowed width/count.
• No shoot-through spike: measured overlap current impulse ≤ N A (placeholder).
• CMTI margin: CMTI_spec ≥ M × dv/dt_expected (placeholder).

Peak source/sink current sets edge time (rule-level sizing)

Gate edge speed is limited by how fast the output stage can move effective gate charge in the targeted edge window. Use a rule form to back into the required peak capability:

• Faster edges can reduce switching loss but increase dv/dt-driven stress and EMI.
• High-side constraint: the output stage sits on a floating island (VBS). Bias droop and UVLO gating can reduce effective drive amplitude even if peak current is nominally high.

Split Rg_on / Rg_off: why it is frequently used on the high side

Split resistors separate the “turn-on edge” from the “turn-off edge,” enabling asymmetric control of dv/dt and false turn-on margin:

• Strong turn-off (lower Rg_off): improves gate discharge authority, reducing susceptibility to dv/dt-induced VGS rise during off intervals.
• Controlled turn-on (higher Rg_on): limits dv/dt and ringing, improving EMI headroom when loss targets permit.
• High-side emphasis: the switching node’s fast transitions make the off-state gate margin more fragile; split control prioritizes a robust off edge.

Slew and drive-strength knobs (map knobs to measurable metrics)

• Drive strength steps: tune effective output impedance to hit a target edge window.
• Slew-rate selects: cap dv/dt for EMI or false turn-on margin, at the cost of higher switching loss.
• Turn-off assist features: improve off-state margin by reducing VGS spikes during SW dv/dt events.

Two-level edges (overview only)

Two-level turn-on/off applies a “fast–then-gentle” profile: a short fast segment reduces linear-region time, while a slower segment limits ringing and dv/dt peaks. Detailed implementations are handled in dedicated pages.

Pass/Fail placeholders (output-stage tuning)

• Edge target window: tr/tf within X…Y ns (placeholder).
• dv/dt limit: dv/dt ≤ Z kV/µs (placeholder).
• VGS spike: VGS_spike(max) ≤ (Vth_min − N V) (placeholder margin).
• Ringing/overshoot: overshoot or ringing Vpp ≤ target limit (placeholder).

Loop-1: Bootstrap loop must be the shortest local power ring

The bootstrap loop is a pulsed local supply path. Its parasitic inductance converts charge pulses into bias ripple and noise injection. The loop to minimize is: VDD → Dboot → Cboot → HS driver (VB/VBS) → return.

• Place Cboot next to VB/VBS pins: reduce loop length and inductance.
• Place Dboot next to Cboot: keep the charge pulse local and predictable.
• Keep return local: avoid long detours and cross-partition returns that pick up SW noise.

Loop-2: Gate loop must close tightly to the device source (Kelvin preferred)

• Minimize gate loop area: driver out → Rg → gate → source return.
• Kelvin source reference: separate driver return from power source inductance to reduce reference bounce.
• Avoid SW proximity: do not route the gate loop across high dv/dt regions.

Loop-3: Reference and input paths must avoid SW dv/dt injection

The switching node is a strong noise radiator and injector. Keep sensitive input, enable, and fault paths out of the SW keep-out region. Robust timing (H2-7) cannot compensate for severe injection into the level-shift and input logic paths.

Common layout pitfalls (symptom → root cause)

• UVLO chatter / first-pulse failure: Cboot too far or loop too large → VBS ripple rises.
• Random false pulses: SW region injects into input/EN/FLT or level-shift path.
• False turn-on sensitivity increases: shared return / non-Kelvin source → reference bounce grows.
• Ringing and EMI spikes: oversized gate loop area and uncontrolled return path.

Pass/Fail placeholders (placement and loop closure)

• Cboot proximity: Cboot-to-driver (VB/VBS) distance ≤ X mm (placeholder).
• Bootstrap loop closure: no cross-partition detours; local return to driver reference (checklist gate).
• Gate loop: gate trace and return must remain tightly coupled; loop length ≤ Y mm (placeholder).
• SW keep-out: sensitive input/EN/FLT traces do not enter SW dv/dt keep-out zone (rule placeholder).