Negative VGOFF & Miller: Prevent False Turn-On in SiC/GaN
Negative VGOFF is a controllable “off-margin” knob: hold the gate at −2…−5 V so Miller dv/dt injection cannot lift VGS into the threshold window. The right answer is budget + evidence—choose the minimum −V that keeps VGS_peak below threshold and VGS_min inside abs-max under worst dv/dt, sequencing, and measurement conditions.
H2-1 · What Negative VGOFF Solves (Scope & Non-Goals)
Negative VGOFF pulls VGS below 0 V during turn-off (typically −2…−5 V) to increase turn-off margin against dv/dt + Miller induced gate bumps and reduce false turn-on.
Solves: A repeatable way to decide whether negative turn-off bias is needed, choose a safe level, and verify that false turn-on is suppressed without overstressing the gate.
Scope boundary: Focuses only on the risk loop (dv/dt → Miller injection → VGS bump → threshold crossing) and the negative turn-off knob. Driver/isolator system design is not covered here.
Non-goals (do not replace): Negative VGOFF is not a substitute for a clean gate loop, active clamp, or staged (two-level) wave-shaping. Those are separate knobs with different ownership.
Applies when:
- High dv/dt switching pushes larger Miller-injection current into the gate loop.
- Tight threshold margin (low Vth or hot Vth shift) makes small VGS bumps risky.
- Constraint-driven parasitics (parallel devices, unavoidable loop inductance, high power density) prevent relying on layout alone.
Defer or avoid when:
- Measured gate bump remains far below threshold across corners and an active clamp already holds the gate low.
- Negative rail generation and sequencing add unacceptable startup/fault complexity for the target platform.
- Gate stress margin is already tight; negative bias would push VGS(min) closer to the absolute negative limit.
H2-2 · The Miller False Turn-On Mechanism (What Actually Moves VGS)
False turn-on is not “mystery switching.” It is a measurable chain: dv/dt creates Miller-injection current, which converts into a VGS bump through gate-loop impedance and common-source inductance.
Step 1 — Capacitive injection: The switching node dv/dt drives current through Cgd into the gate network. The risk scales with dv/dt and effective Cgd.
Engineering handle: Ig ≈ Cgd × (dVDS/dt) (first-order budgeting).
Step 2 — Current becomes a voltage bump: The injected current flows through gate-loop impedance (driver pull-down path, Rg, and parasitics), producing a bump on VGS.
Engineering handle: ΔVGS ≈ Ig × |Zg(ω)| (fast edges emphasize parasitic L at high frequency).
Step 3 — Common-source inductance (CSI): Source-path inductance lifts the source reference during high di/dt, effectively increasing VGS even when the gate node looks “quiet.”
Engineering handle: ΔVGS,CSI ≈ Ls × (di/dt) (Kelvin source reduces this term by stabilizing the reference).
Why SiC/GaN are more sensitive:
- Higher dv/dt → higher Ig injection for the same Cgd.
- Tighter threshold margin (including temperature Vth shift) → smaller bumps can cross the effective turn-on boundary.
- Faster edge spectra → parasitic inductance contributes more, increasing |Zg(ω)| and CSI impact.
Budget anchor for the rest of this page: false turn-on risk rises when VGS,peak approaches the effective threshold window.
Practical anchor: VGS,peak ≈ VGOFF + ΔVGS(Miller) + ΔVGS(CSI) + ringing_margin. Negative VGOFF increases turn-off headroom by pushing VGOFF below 0 V.
H2-3 · Do You Need −VGOFF? (Decision Tree Before You Add Complexity)
Negative VGOFF is a margin knob, not a universal fix. The correct sequence is: confirm evidence, quantify margin, then choose the lowest-complexity knob that closes the risk.
Layer A — Evidence gate: Add complexity only after repeatable evidence exists (VGS bump aligned with opposite dv/dt, abnormal current spike, or shoot-through symptom in controlled switching tests).
Layer B — Margin gate: If the worst-case VGS,peak stays far below the effective threshold window (including temperature and process shift), negative bias can be deferred. If the margin collapses at corners, negative bias becomes a primary candidate.
Layer C — Knob ownership: −VGOFF expands turn-off headroom; Miller clamp holds the gate low against injection; two-level turn-off reshapes edges for EMI/ringing control. Use links for implementation details to avoid duplicated design content.
Defer −VGOFF (start with simpler knobs) when:
- dv/dt is moderate and VGS bump remains comfortably below the effective threshold window across operating corners.
- An existing Miller clamp already prevents gate lift and the measured margin is stable with temperature.
- Gate loop conditions are already controlled (clear reference return, no ambiguous source reference), so additional margin is not the limiting factor.
Consider −VGOFF (or a combination) when:
- High dv/dt hard-switching creates large Miller-injection currents that exceed what pull-down impedance can absorb.
- Parallel devices or unavoidable parasitics reduce the worst-case threshold margin (Vth spread + local impedance mismatch).
- EMI/ringing knobs (slower edges, larger Rg) are already constrained by loss/thermal targets, and margin is still insufficient.
Three metrics that must be measured before deciding:
- dv/dt at VDS or the switching node under worst-case conditions (threshold placeholder: X kV/µs).
- VGS,peak during the opposite switch transition at the victim device (placeholder: Y V).
- Margin to the effective threshold window including temperature and process shift (placeholder: N V).
H2-4 · Gate-Voltage Budgeting (How to Pick −2…−5 V Without Exceeding Limits)
Selecting −VGOFF is a balance between turn-off margin and negative gate stress. A correct budget uses worst-case injection and worst-case ringing to keep VGS within a safe window.
Budget object #1 — Turn-off margin: ensure worst-case VGS,peak stays below the effective threshold window with margin.
Anchor: VGS,peak ≈ VGOFF + ΔVGS(Miller) + ΔVGS(CSI) + ringing_margin.
Budget object #2 — Negative stress: ensure VGS,min (including undershoot spikes) does not approach the device negative absolute limit.
Key risk: stronger pull-down + higher parasitics can increase negative undershoot even if the nominal −VGOFF is modest.
Budget object #3 — Robust operation: include startup/UVLO/fault sequencing so the gate never stays in an undefined region when rails move.
This chapter defines the budget item; sequencing details belong to the dedicated startup/UVLO section later in the page.
Key contributors (what shifts the budget corners):
- Vth drift across temperature and process shifts the effective threshold window.
- Pull-down strength (driver sink capability and output impedance) changes how injection current converts into ΔVGS.
- Gate-loop parasitics (Rg + inductive content) determine ringing and negative undershoot severity.
Risk–benefit ladder (use the budget, not guesswork):
- −1 V: small margin gain, low complexity; may be insufficient for high dv/dt corners.
- −2 V: common starting point; meaningful margin gain with manageable stress if undershoot is controlled.
- −3 V: stronger robustness for high dv/dt / parallel devices; watch negative spikes and sequencing.
- −5 V: maximum margin; highest stress and sequencing risk; requires disciplined verification and protection.
Budget template — Item 1 (Injection): ΔVGS(Miller)
Symbol: ΔVGS(Miller) · How to obtain: measure dv/dt and gate bump during opposite transition · Pass criteria: ΔVGS(Miller) ≤ X V
Budget template — Item 2 (CSI): ΔVGS(CSI)
Symbol: ΔVGS(CSI) · How to obtain: correlate di/dt with source reference movement · Pass criteria: ΔVGS(CSI) ≤ Y V
Budget template — Item 3 (Ringing): VGS undershoot
Symbol: VGS,min · How to obtain: capture turn-off transient with correct reference · Pass criteria: VGS,min ≥ (AbsNeg + N V)
Budget template — Item 4 (Threshold window): Vth corner
Symbol: Vth,eff · How to obtain: use worst-case datasheet + temperature shift · Pass criteria: Margin to Vth window ≥ M V
Budget template — Item 5 (Chosen level): VGOFF
Symbol: VGOFF · How to choose: pick the least negative level that closes margin while keeping VGS,min safe · Pass criteria: VGOFF = −(1/2/3/5) V justified by the above items
Scope note: This section defines the −VGOFF budget only. Clamp strength, two-level timing details, and layout geometry belong to their dedicated pages to avoid duplicated design rules.
H2-5 · How to Generate the Negative Rail (Bias Options & Trade-offs)
The negative rail is not only “a voltage.” Its noise, transient droop, and sequencing behavior directly determine whether −VGOFF remains a reliable margin under hard switching.
Scope boundary: This section compares negative-rail sourcing options and the engineering trade-offs. Integrated isolated-bias implementations belong to the dedicated pages to avoid duplicated design details.
Bias options (four common sources):
Option A — External negative supply: stable rail, predictable behavior; higher BOM/area and system-level routing.
Primary checks: ripple level, transient droop during turn-off events, and reference integrity.
Option B — Isolated bias (isolated DC-DC): strong domain separation; noise and coupling paths must be managed under high dv/dt.
Primary checks: common-mode injection sensitivity and rail stability across switching corners.
Option C — Local charge pump: low BOM and compact; output impedance and ripple can dominate under dynamic load.
Primary checks: ripple at the switching spectrum and droop during fast gate discharge.
Option D — Auxiliary winding: efficient reuse of magnetics; startup and load-dependent drift must be budgeted.
Primary checks: rail availability at cold start / light load and recovery after transients.
Trade-off dimensions (use measurable language):
- Noise: VNEG ripple level (placeholder: X mVpp / VRMS) and whether it aligns with sensitive windows.
- Transient output impedance: droop during turn-off events (placeholder: ΔVNEG ≤ Y mV) and recovery time (placeholder: ≤ N µs).
- Startup & sequencing: rail-ready time and UVLO crossing window (placeholders: Tready, ΔT).
- Cost/area: BOM count, routing complexity, and mechanical constraints (qualitative tiering only).
- Reliability: predictable failure modes (open/short/drift) and temperature sensitivity (placeholder: ΔVNEG/ΔT).
Most common pitfalls (symptom → first check):
- −VGOFF looks correct on paper, but margin collapses under switching: check ΔVNEG droop at the exact turn-off instant (transient output impedance).
- Protection chatter or false trips increase after adding −V: check VNEG ripple coupling into the gate reference/threshold sensing path.
- Cold start or light load causes intermittent behavior: check rail-ready timing and whether PWM/enable can occur before the negative rail is valid.
H2-6 · Negative Turn-Off Dynamics (Ring-Down, Undershoot, and Gate Stress)
Adding −VGOFF can increase negative undershoot and make measurements harder. The risk comes from stronger pull-down interacting with loop parasitics and reference ambiguity.
Phenomenon: the gate waveform shows a negative platform (−VGOFF) followed by a deeper negative spike and ring-down. The spike can approach the negative absolute limit and increase oxide stress.
Root causes (minimum set): true undershoot from Lloop × di/dt during fast discharge, reference shift from Kelvin vs power source ambiguity, and measurement artifacts from the probe loop.
Fix knobs (names only): split Rg(on/off), series ferrite, limit sink strength, Kelvin reference discipline, active Miller clamp, two-level turn-off.
Pass criteria (placeholders): VGS,min ≥ VGS(abs neg) + X V, ring settles within N ns (or amplitude ≤ Y V), and captured spikes are repeatable across measurement setups (≤ M delta).
H2-7 · Active Miller Clamp + −VGOFF (Division of Labor, Not Duplication)
Clamp and −VGOFF address the same dv/dt injection chain from different points. Clamp suppresses gate lift; −VGOFF increases turn-off headroom against threshold drift.
Clamp (what it closes): keeps the gate tightly referenced to the source during high dv/dt events, reducing the amplitude and duration of Cgd-driven VGS lift.
Owner: Active Miller Clamp (internal structure and clamp current are defined there).
−VGOFF (what it closes): shifts the turn-off baseline downward to enlarge margin to the effective threshold window, improving robustness across temperature, process, and device spread.
Owner: this page (budget and negative-stress limits are defined in the earlier sections).
Shared boundary: neither clamp nor −VGOFF replaces loop control. If the source reference is ambiguous, “gate lift” and “undershoot” can both worsen.
When clamp-only is often sufficient:
- Gate lift is clearly correlated with dv/dt events, and adding clamp reduces VGS,peak to a stable, repeatable level (placeholder: ≤ X V).
- Worst-case margin to the effective threshold window remains comfortable after clamp (placeholder: ≥ N V), including temperature and device spread.
- Negative undershoot risk is already close to the limit, so adding −V would tighten the negative-stress budget unnecessarily.
When −VGOFF becomes necessary (with or without clamp):
- Clamp reduces gate lift but the corner-case margin remains insufficient due to Vth drift/spread (placeholder: < N V).
- Parallel devices or unavoidable parasitics create a narrow threshold window where baseline headroom dominates the decision.
- The requirement is “no false turn-on across all corners,” and injection suppression alone cannot guarantee margin.
Combination strategy (no tuning details): apply clamp to suppress injection first, then apply −VGOFF only as negative as needed by the budget. Verification must include both VGS,peak (false turn-on risk) and VGS,min (negative stress margin) with placeholders X/Y/N.
H2-8 · Two-Level Turn-Off + −VGOFF (Taming EMI Without Losing Robustness)
Two-level turn-off separates “fast safety” from “gentle EMI control.” −VGOFF provides the final hold margin so robustness is preserved when dv/dt is intentionally reduced.
Stage-1 (fast pull-down): quickly moves VGS away from the sensitive region, shrinking the false turn-on window. Owner: Two-Level Turn-On/Off
Stage-2 (gentle slope): controls dv/dt and ring excitation to improve EMI without forcing extreme Rg or excessive loss. Owner: Two-Level Turn-On/Off
Hold at −V: anchors the final off-state at a lower baseline to increase headroom against threshold drift/spread and noisy environments. Owner: this page
How to avoid making −V an “extra ringing exciter” (strategy names only):
- Limit sink strength (avoid over-driving the discharge path into parasitic resonance).
- Split Rg(off) (shape the discharge impedance without changing the on-edge).
- Ring-aware hold transition (avoid landing the hold baseline at the instant of peak oscillation).
- Kelvin reference discipline (keep “hold at −V” referenced to the true source).
Joint acceptance (placeholders): EMI target via dv/dt or radiated margin (X), robustness via VGS,peak and threshold margin (Y/N), and stress via VGS,min negative margin (M). Detailed tuning parameters (t1/t2 and current shaping) belong to the Two-Level page.
H2-9 · Startup, UVLO, and Fault Sequencing with a Negative Rail
Negative-rail systems most often fail during transitions: power-up, power-down, brownout, and fault. The goal is to prevent any “gate-undefined window” where the switch can enter half-conduction.
Failure modes to prevent (transition focused):
- −V arrives late (or never valid): the gate baseline can be undefined while PWM/EN becomes active → half-conduction risk.
- −V collapses faster during power-down: margin disappears first, but PWM/logic can remain active → false turn-on becomes easier.
- UVLO boundary chatter: insufficient hysteresis causes repeated enable/disable toggles → stress and unpredictable behavior.
Rail-ready rule (enable permission): PWM/EN release is allowed only when both rails are valid and stable: VPOS ≥ VPOS_ON (X) for TPOS_STABLE (N), and VNEG ≤ VNEG_ON (Y) for TNEG_STABLE (N). If either condition fails, the output must remain in an OFF-safe state.
UVLO (negative-rail relevant requirements): define paired ON/OFF thresholds, include sufficient hysteresis, and specify a default OFF-safe state under undervoltage. Do not rely on software to enforce this behavior.
/DIS and /FLT safe path (auditable OFF-safe state): define what “OFF” means during UVLO/fault and verify it in hardware. Level 1: force VGS ≤ 0V (no float). Level 2: force VGS ≤ −VREADY when the negative rail is valid. Fault-to-safe timing must be bounded (placeholder: T_OFF_SAFE ≤ N).
Acceptance placeholders (review-ready): No-PWM-before-rails (Y/N), UVLO-safe-state (Level-1/2), Fault-to-off-time (N), Brownout behavior shows no gate-undefined window (Y/N).
H2-10 · Validation & Measurement Playbook (Prove No False Turn-On)
“No false turn-on” must be proven with repeatable evidence: gate waveform limits, absence of shoot-through signatures, and no gate-stress violations. This playbook is designed for review and acceptance disputes.
Three proof targets (evidence-based):
- Gate lift limit: VGS,peak stays below the effective threshold window (placeholder: VGS,peak ≤ Vth_effective − X).
- No shoot-through signature: no abnormal overlap indicators (placeholder: ΔIbus ≤ Y, no abnormal VDS coincidence).
- No stress violation: VGS,min remains within negative margin (placeholder: VGS,min ≥ AbsNeg + N).
Recommended coverage (corner-focused): double-pulse test, maximum dv/dt condition, temperature corners, and worst-layout corner. Record the exact stimulus (VBUS, load current, switching edge strength) for reproducibility.
Measurement discipline (avoid false spikes): avoid long ground leads, prioritize differential sensing, and measure VGS at the true gate-to-source reference point (Kelvin discipline). Measurement settings must be recorded (bandwidth, sample rate, filters) to resolve disputes.
Pass/Fail template (placeholders): Gate lift (X), shoot-through evidence (Y), negative stress margin (N), and repeatability across measurement setups (Δ ≤ M).
H2-11 · Engineering Checklist (Design → Bring-up → Production)
This chapter converts the negative turn-off strategy into three audit-friendly gates. Each item is written as a recordable checkpoint so review, bring-up, and production acceptance use the same criteria.
Design gate before PCB release
- Gate-voltage budget is complete: VGS_peak, VGS_min, margin ≥ X V (worst corner).
- Negative stress stays inside limits: VGS_min ≥ AbsNeg + N V (include ringing allowance).
- Negative rail capability is quantified: VNEG droop ≤ X V during max sink events.
- UVLO + sequencing policy is explicit: rail-ready conditions + default OFF-safe state.
- Division of labor is fixed: −V hold / Miller clamp / two-level turn-off roles do not overlap.
- Layout constraints are stated: Kelvin reference, minimal loop, return-path rules (no cross-split).
Example BOM (negative rail) — verify latest datasheets:
TPS63710(TI) — inverting converter for a small −V rail.LTC3260(Analog Devices) — charge-pump based dual-polarity supply.R05P05D(RECOM) — isolated DC/DC module with ± outputs.
Bring-up gate lab proof
- Waveform evidence pack: VGS, VDS, current proxy + probe setup recorded.
- Worst dv/dt condition is exercised: max VBUS / strongest drive / worst layout corner.
- No false turn-on signature: shoot-through evidence = 0 (define metric Y).
- Negative spike is bounded: VGS_min ≥ AbsNeg + N V (measured at Kelvin reference).
- Temperature corners are covered: cold/hot margins tracked (Δ margin ≥ X V).
- Sequence fault injection: late/early −V, brownout, disable path → OFF-safe state (Y/N).
Example BOM (driver candidates) — shortlist by specs:
UCC21750/UCC21732(TI)ADuM4135(Analog Devices)1ED3122MC12H/1EDI20I12MF(Infineon)ACPL-337J(Broadcom)
Production gate repeatability
- Sampling plan is defined: VNEG, VGS_peak, VGS_min, and key timing items (N samples/lot).
- Fault injection is standardized: /DIS open/short, UVLO trigger, −V drop → OFF-safe (Y/N).
- Measurement fixture is frozen: bandwidth, ground method, Kelvin point definition.
- Documentation acceptance text: the same thresholds appear in EMC/safety/FA docs (X/Y/N).
- Regression triggers are listed: device lot change / layout change / rail change → minimum re-test set.
Example BOM (consistency aids):
- Gate resistor footprints for split tuning + optional bead footprint.
- Dedicated Kelvin-sense test pads at the driver reference point.
- Rail monitor points for +V and −V (probe repeatability).
Figure (Gate checklist board) — quick scan of the three gates and the evidence required.
H2-12 · Applications & IC Selection (Placed at the End, Before FAQ)
This chapter stays strictly within negative VGOFF + Miller-risk closure: application playbooks define when −V is worth the complexity, and selection lists only the fields that matter for this topic.
A) 3-Phase inverter / half-bridge (SiC/GaN)
- Risk shape: dv/dt-driven gate lift + tight VTH margin.
- Preferred combo: Miller clamp handles injected current; −V provides off-margin hold; two-level turn-off manages EMI if needed.
- Acceptance focus: VGS_peak < (VTH_min − X), VGS_min ≥ AbsNeg + N, no shoot-through evidence (Y).
Example part numbers (drivers):
UCC21750,UCC21732(TI)1ED3122MC12H,1EDI20I12MF(Infineon)
B) Totem-pole PFC / LLC
- Risk shape: EMI constraints force edge-shaping; margin can be consumed by slow transitions + coupling.
- Decision rule: clamp first for injected-current control; add −V when corner margin is still insufficient.
- Acceptance focus: EMI target (X) met while VGS_peak and VGS_min margins remain stable across temperature.
Example part numbers (drivers):
ADuM4135(Analog Devices)ACPL-337J(Broadcom)
C) Paralleled switches (VTH spread)
- Risk shape: the “weakest” device (lowest VTH corner) defines false turn-on vulnerability.
- Preferred combo: −V provides uniform off-margin across devices; clamp prevents dv/dt injection from becoming VGS lift.
- Acceptance focus: corner-based margin uses worst-VTH device; production sampling includes VGS metrics (N/lot).
Example part numbers (drivers):
UCC21750(TI)1EDI20I12MF(Infineon)
Key specs & shortlisting fields for −VGOFF topic-specific
1) Negative drive capability
- Why: defines off-margin hold and how much droop occurs during strong sink events.
- Check: supported VEE range, peak sink current, output impedance (X/Y/N).
Example part numbers:
UCC21732(TI)1ED3122MC12H(Infineon)
2) Active Miller clamp availability
- Why: provides a low-impedance path for injected Miller current when dv/dt is highest.
- Check: clamp mode entry condition + clamp strength class (X/Y/N).
Example part numbers:
ADuM4135(Analog Devices)1EDI20I12MF(Infineon)
3) UVLO & rail-valid / default OFF-safe behavior
- Why: negative-rail systems fail most often during ramp-up/down and brownout.
- Check: enable/disable defaults, UVLO thresholds + hysteresis, fault-to-off state (X/Y/N).
Example part numbers:
UCC21750(TI)1ED3122MC12H(Infineon)
4) Delay / skew (bridge safety)
- Why: not the root cause of Miller false turn-on, but still critical for shoot-through margin.
- Check: propagation delay stability and channel-to-channel matching (X/Y/N).
Example part numbers:
UCC21732(TI)ACPL-337J(Broadcom)
Negative rail generation — example BOM options (pick by noise/impedance/startup needs):
TPS63710(TI) — inverting converter for −V rails.LTC3260(Analog Devices) — charge-pump based dual-polarity rails.R05P05D(RECOM) — isolated DC/DC module with ± outputs.
Note: Part numbers are examples for shortlisting; final selection must follow the latest datasheet limits and safety requirements.
Figure (Application × knobs matrix) — which knob is typically needed, and why (one-line).
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H2-13 · FAQs (Fixed 4-Line Answers, No Diagram)
These FAQs close common field-debug and acceptance disputes for negative VGOFF and Miller-induced false turn-on.
Each answer is strictly four lines and uses measurable placeholders (X/Y/N) for review-ready pass/fail criteria.
FAQAdded −3 V but false turn-on still happens—Cgd injection or CSI (Ls) dominating?
Likely cause: The dominant path is common-source inductance (L_s) / reference bounce, or clamp is not actually clamping the injected current from Cgd.
Quick check: Measure VGS at the true Kelvin source reference and log VGS_peak timing versus dv/dt (worst corner).
Fix: Enforce Kelvin referencing / minimize shared source inductance; ensure clamp return path is local; adjust −V_hold only after the reference path is controlled.
Pass criteria: VGS_peak ≤ VTH_effective − X V; no shoot-through signature (ΔIbus ≤ Y); repeatability across probe methods (Δ ≤ M).
FAQVgs shows −8 V spikes at turn-off—real stress or probe artifact?
Likely cause: Either true gate-loop ring-down (high L·di/dt) or measurement loop pickup from long ground leads / wrong reference.
Quick check: Re-measure using a differential method (or shortest ground spring) and the Kelvin source reference; compare spike change (ΔV_spike).
Fix: If artifact: fix probing and bandwidth logging; if real: reduce gate-loop inductance, tame sink edge (two-level / split Rg_off), and limit −V + undershoot sum.
Pass criteria: VGS_min ≥ AbsNeg + N V (including worst-case ringing); probe-change sensitivity ΔV_spike ≤ M V for the accepted method.
FAQNegative bias improved shoot-through but EMI got worse—edge too hard or ringing moved bands?
Likely cause: Stronger sink + deeper −V increased gate-loop excitation; ringing energy shifted into a radiated/ conducted sensitive band.
Quick check: Correlate EMI peak frequency with VGS ring frequency and switching node dv/dt under the same load condition.
Fix: Keep −V_hold for margin but shape the sink edge (two-level turn-off / split Rg_off / clamp usage discipline) to reduce excitation.
Pass criteria: EMI target met (X); VGS_peak ≤ VTH_effective − X V; VGS_min ≥ AbsNeg + N V; efficiency impact within Y.
FAQWorks at room temp, fails hot—Vth shift reduced margin or UVLO sequencing?
Likely cause: VTH shift and leakage reduce the effective off-margin, or undervoltage sequencing creates a gate-undefined window at temperature corners.
Quick check: Repeat the worst dv/dt test hot and log VGS_peak, VGS_min, and rail-valid timing (+V/−V/EN/PWM).
Fix: Increase margin via clamp + −V_hold only if the reference path is correct; tighten UVLO thresholds/hysteresis and enforce “PWM after rails-ready”.
Pass criteria: Hot-corner: VGS_peak ≤ VTH_effective(hot) − X; no PWM before rails-ready (Y/N); T_off_safe ≤ N.
FAQClamp enabled but Vgs still bumps—clamp pin placement/return path wrong?
Likely cause: Clamp is not referenced to the true source (non-Kelvin return), or clamp current path is inductive so injected current still lifts VGS.
Quick check: Verify clamp engagement timing and measure V(G−S_Kelvin) directly; compare bump magnitude with clamp on/off (same dv/dt).
Fix: Route clamp and driver return to the Kelvin source; reduce shared source inductance; keep −V_hold as margin rather than as a substitute for a bad return.
Pass criteria: Clamp-on reduces VGS_peak by ≥ X V; VGS_peak ≤ VTH_effective − X; no shoot-through evidence (Y/N).
FAQTwo-level turn-off reduces ringing but false turn-on returns—Stage-2 too weak or hold level wrong?
Likely cause: Stage-2 leaves the gate in a vulnerable impedance state, or the final −V_hold level is not reached quickly enough after the critical dv/dt event.
Quick check: Log VGS across Stage-1/Stage-2/hold and align it with switching-node dv/dt to see where the bump occurs.
Fix: Ensure Stage-1 establishes control, Stage-2 shapes dv/dt, and the final state clamps/holds at −V_hold; avoid leaving the gate floating or high-Z.
Pass criteria: During dv/dt window: VGS_peak ≤ VTH_effective − X; post-turn-off: reaches −V_hold within N; no overlap signature (Y).
FAQBootstrap HS with −V rail sometimes latches off—UVLO thresholds or charge balance issue?
Likely cause: UVLO boundary condition is triggered by rail droop or timing; the negative rail changes the effective supply window or startup order.
Quick check: Capture +V, −V, VBS (or local bias), /EN, and output state during the latch event; confirm which UVLO threshold is crossed.
Fix: Enforce rails-ready gating; add margin to bias droop (Zout/decoupling/sequence), and ensure OFF-safe default is defined when either rail is invalid.
Pass criteria: No UVLO chatter (Y/N); Vbias_min ≥ UVLO_OFF + N; outputs remain OFF-safe whenever rails are not valid (Y/N).
FAQParallel devices: one dies first after adding −V—mismatch, gate loop symmetry, or local undershoot?
Likely cause: Gate loop asymmetry creates unequal VGS_min undershoot or unequal effective off-margin; device-to-device VTH spread amplifies the weakest corner.
Quick check: Measure each device’s V(G−S_Kelvin) and compare VGS_min and bump timing under the same dv/dt event.
Fix: Enforce per-device symmetry (return path, Kelvin, gate resistance), limit worst-case undershoot, and use −V_hold as shared margin after symmetry is achieved.
Pass criteria: Device-to-device: |VGS_min(i) − VGS_min(j)| ≤ X; all meet VGS_min ≥ AbsNeg + N; no single-device overstress (Y/N).
FAQDriver reports fault during dv/dt bursts—CMTI limit or /FLT path coupling?
Likely cause: dv/dt induced common-mode transient triggers a false fault, or the /FLT path is coupled (return/reference not robust).
Quick check: Correlate fault timing with dv/dt burst; log Vcm behavior and /FLT waveform integrity at the receiver reference.
Fix: Strengthen fault path referencing and filtering within allowed limits; verify OFF-safe behavior drives to −V_hold (or at least ≤ 0 V) during faults.
Pass criteria: No false faults under worst dv/dt (Y/N); if fault occurs, T_off_safe ≤ N and VGS ≤ 0 V (or ≤ −V_hold) guaranteed (Y/N).
FAQGate oxide failures increase after switching to −5 V—abs max violated by undershoot?
Likely cause: The sum of −V_hold and ringing undershoot pushes VGS_min beyond negative absolute maximum at worst conditions.
Quick check: Measure VGS_min at Kelvin source under max dv/dt and strongest sink; confirm the worst undershoot event.
Fix: Reduce undershoot excitation (layout, sink shaping, two-level), or reduce −V_hold to restore margin; treat “−V deeper” as last resort.
Pass criteria: Worst-case: VGS_min ≥ AbsNeg + N; lifetime risk indicator does not regress (Y/N); stress margin recorded as X V.
FAQShoot-through only at certain bus voltage—dv/dt changes moved Miller bump into threshold window?
Likely cause: The dv/dt-dependent bump timing overlaps the vulnerable window where VGS crosses VTH_effective due to reference bounce or insufficient clamp.
Quick check: Sweep bus voltage and record dv/dt, VGS_peak, and overlap indicators (ΔIbus); locate the voltage where the bump aligns with the window.
Fix: Use clamp to suppress injected current and keep −V_hold for margin; reduce reference inductance so dv/dt does not translate into VGS lift.
Pass criteria: Across VBUS range: VGS_peak ≤ VTH_effective − X; ΔIbus ≤ Y; no event-dependent window crossing (Y/N).
FAQMeasured Vgs looks safe, but current spike indicates conduction—where to probe and what to log?
Likely cause: VGS was measured at a non-Kelvin reference, missing the effective gate-to-source voltage during dv/dt events; current spike is the real evidence.
Quick check: Re-probe V(G−S_Kelvin) and log ΔIbus/VDS simultaneously with time alignment to the dv/dt edge.
Fix: Standardize measurement reference and logging; then apply the minimal knob that addresses the proven path (clamp for injection, −V_hold for margin, two-level for excitation control).
Pass criteria: Kelvin-referenced VGS_peak ≤ VTH_effective − X; overlap evidence ΔIbus ≤ Y; repeated runs consistent (Y/N).
X = required margin, Y = allowed overlap indicator, N = required negative-stress margin, M = allowed measurement variation.
Replace with project-specific numbers during design review and acceptance.
