PFC + HB/FB/LLC Gate Driver Guide (Main Bridge + SR)
H2-01 · Definition & Scope
What this page is about
This page focuses on main-bridge gate drivers (HB/FB driving the LLC or hard-switched bridge) and synchronous-rectifier (SR) drivers in a PFC + HB/FB/LLC power chain, with the explicit goal of achieving and preserving ZVS/ZCS behavior through timing budget, gate-loop control, bias integrity, and fault-safe shutdown.
Primary value
Engineering-usable rules: what to size, what to verify, and what must pass (with thresholds X/Y/N placeholders).
Outcome
Higher efficiency, controlled EMI, and consistent protection behavior across load/line/temperature.
Typical system boundary
- Front end: PFC stage (boost or bridgeless family) providing a regulated or semi-regulated DC bus.
- DC/DC stage: HB or FB driving an LLC resonant tank (or a bridge feeding a transformer stage).
- Secondary: Transformer + SR stage (MOSFET synchronous rectification) for efficiency and thermal headroom.
Rule The discussion stays on the driver-controlled path: gate loop, timing, bias, fault path, and verification gates.
Main-bridge driver vs SR driver (responsibility split)
Main-bridge driver
Enforces interlock and deadtime, manages dv/dt and Miller behavior, maintains high-side bias headroom, and
preserves ZVS by not consuming the timing window (tPD/skew + gate transition).
SR driver
Decides when to conduct and when to release under changing current polarity and diode conduction;
prevents reverse energy flow and reduces loss without creating hard commutation events.
Shared requirement
Predictable timing + safe fault deactivation. Any ambiguous state must resolve to safe off within X µs.
What changes when targeting ZVS/ZCS
- Deadtime becomes a window budget: ZVS can be lost if driver delay, skew, and gate transition consume the available commutation window.
- Gate voltage strategy matters: insufficient VGS headroom causes partial conduction; excessive edge speed creates EMI and false turn-on risk.
- dv/dt stress is real: Miller coupling can trigger unintended turn-on; clamp and gate-loop inductance dominate the outcome.
- Bias integrity is not optional: high-side undervoltage or refresh gaps can collapse drive strength and break soft-switching behavior.
- Fault handling must be “hard”: shutdown must propagate across domains with deterministic timing and no “soft” ambiguity.
Scope Guard (hard boundary to prevent overlap)
This page covers
Main-bridge + SR driver selection and bring-up under ZVS/ZCS goals:
timing budget, gate-loop control knobs, bias choices, and fault-safe shutdown/acceptance.
This page does NOT cover
Control-loop theory, compensator design, magnetics design, resonant-tank derivations, or topology tutorials.
Those belong to dedicated power-control/topology pages.
If a deep dive is needed
Link out only (no expansion here): High-Side Driver (bootstrap/charge pump details), Half/Full-Bridge Driver (interlock/deadtime internals),
Protection & Control (DESAT/UVLO tuning), Isolation & Integration (reinforced isolation and integrated bias).
Acceptance anchors (placeholders to be enforced later)
- ZVS/ZCS success rate: ≥ X% across Y line/load points (define the test window).
- Shoot-through / cross-conduction: 0 events over N startups and thermal cycles.
- Fault-to-safe-off: ≤ X µs from detection to safe gate state (main and SR domains).
- High-side bias headroom: ≥ X V worst case (min line, max load, high temp).
H2-02 · System Partition & “Where Driver Matters”
Driver impact chain (only what changes switching behavior and outcomes)
A driver decision is not local; it propagates through a deterministic chain:
- Gate charge management (peak source/sink + Rg strategy) → sets gate transition speed and current slew.
- dv/dt & di/dt (gate loop inductance + Miller coupling) → defines false turn-on risk and switching loss.
- EMI vs loss trade (slew control / two-level / clamp) → controls radiated/conducted margin and thermal headroom.
- Temperature rise (loss distribution + symmetry) → drives drift and mismatch that erodes ZVS/ZCS stability.
- Reliability (fault response and energy control) → prevents runaway short-circuit energy and repetitive stress damage.
Key mindset The page stays on variables that can be tuned, measured, and accepted.
Four domains to keep separate (hard partition rule)
Power loop
High current, high dv/dt. Contains bridge devices, DC-link caps, primary commutation paths. Goal: minimum loop area and controlled return.
Gate loop
Driver output → Rg → gate → Kelvin source return. Goal: low inductance, predictable edge shaping, minimal coupling into sense/control.
Sense loop
Current/voltage feedback and protection sensing. Goal: clean reference and consistent thresholds; never share noisy returns with power commutation.
Isolation barrier
Defines common-mode current paths and fault transfer rules. Goal: high CMTI robustness and deterministic safe-disable across domains.
Return-path guardrails (what must never happen)
- No cross-domain return: do not let power-commutation return current share a path with sense reference.
- Kelvin source is mandatory: gate return must reference the device source sense point, not the power ground.
- Barrier-aware fault path: fault and disable signals must remain valid under fast dv/dt; avoid “soft-only” shutdown paths.
- Driver bias decoupling: local decoupling must close on the correct return to avoid injecting commutation noise into driver logic.
Practical check: if a measurement point can move by more than X mV during switching, it is not a stable reference for thresholds.
Measurement anchors (placeholders to be enforced later)
- Gate loop quality: ringing ≤ X Vpp at the gate (defined probe method), overshoot within device limit.
- Timing budget: channel skew ≤ X ns; effective deadtime error within the ZVS window reserve.
- Common-mode robustness: required CMTI ≥ X kV/µs with no false toggles / latch-up events.
- EMI margin: ≥ X dB margin in the defined band under worst-case edge settings.
Non-goals for this section (to prevent topic drift)
- No control-loop derivations, compensator math, or magnetics sizing methods.
- No PCB layout tutorial; only enforceable partition rules and acceptance checks.
- No standards deep dive; only measurable robustness requirements and pass criteria placeholders.
H2-03 · ZVS/ZCS Windows & Deadtime Economics
Why this section matters
ZVS/ZCS success is often decided by time budget, not topology. The available commutation window is consumed by propagation delay, channel skew, deadtime error, and gate transition time. The goal is to preserve a stable ZVS reserve across line/load/temperature.
How the ZVS window is created (engineering view)
- Available energy (load current + resonant energy) must move the switch node before the next turn-on edge.
- Required charge (device output capacitance + parasitics) must be charged/discharged within the allowed interval.
- Practical implication: when available energy shrinks (light load), the window tightens and timing tolerance collapses.
Rule Treat ZVS as a budget: window available minus window consumed must stay positive.
Window killers (driver-centric)
Propagation delay (tPD)
Adds fixed latency and temperature drift; consumes margin if not budgeted against the window reserve.
Inter-channel skew (Δt)
Mismatch between HS/LS (or phase-to-phase) compresses effective deadtime and can trigger overlap or hard switching.
Deadtime too short
Overlap risk, hard commutation, and cross-conduction events; reliability and protection margin degrade.
Deadtime too long
Body-diode / reverse-conduction time increases; losses rise and EMI signatures can worsen; ZVS becomes fragile at light load.
Miller false turn-on
dv/dt-induced gate lift creates unintended conduction during off-state, breaking ZVS and causing hidden heating.
Deadtime economics (cost of being wrong)
- Too short → cross-conduction / hard turn-on → current spikes, thermal stress, fault triggers.
- Too long → diode conduction / reverse recovery time → efficiency loss, extra ringing/EMI, higher temperature.
- Optimal point is a controlled interval that preserves ZVS reserve while maintaining zero overlap events.
Acceptance anchors (placeholders)
- ZVS success rate: ≥ X% across the defined Y line/load window.
- Cross-conduction events: = 0 over N startups and thermal cycles.
- Timing reserve: ZVS window reserve ≥ X ns after subtracting tPD, skew, and gate transition time.
H2-04 · Main-Bridge Driver Requirements
What a main-bridge driver must guarantee (common requirements)
- High peak source/sink with low effective output impedance to shape gate transitions as intended.
- dv/dt robustness to prevent false turn-on under fast switching-node slews.
- Hardware interlock and deadtime control to enforce zero overlap and stable ZVS reserve.
- UVLO behavior that prevents half-conduction (clean on/off thresholds and deterministic state on brownout).
- Fault-safe disable path that forces safe gate states with bounded delay (X µs placeholder).
Selection focus Features are evaluated by their impact on loss, EMI, and reliability under ZVS/ZCS goals.
HB/FB vs LLC (priority differences)
HB / FB priority
Interlock and matching dominate. Tight propagation matching and stable deadtime enforce zero overlap events under load transients and temperature drift.
LLC priority
ZVS window preservation dominates. Timing stability during frequency sweep and light-load conditions matters more than peak edge speed.
Shared acceptance
Cross-conduction events = 0; ZVS success rate ≥ X% across the defined Y window; driver behavior must not shift the budget beyond reserve.
Drive strength sizing (engineering sizing handle)
- Peak current class is sized by gate charge and target transition time: choose the Ipk tier that supports the intended tr/tf under the real gate loop.
- Edge shaping knobs (split Rg, clamp, two-level) must exist if EMI margin and false turn-on risk are tight.
- Temperature and tolerance matter: the selected driver must hold timing and output strength over the full operating range.
Practical anchor: specify the target tr/tf and then validate gate waveform overshoot/ringing within X Vpp under worst-case dv/dt.
The 3 must-ask questions (inputs that lock the requirement set)
Deadtime budget
Allowed deadtime error ≤ X ns; skew and tPD drift must fit within the ZVS reserve.
tr/tf + EMI constraint
Target transitions that meet EMI margin ≥ X dB while keeping loss and temperature within limits.
High-side bias strategy
Bootstrap vs isolated bias must be chosen based on frequency sweep, light-load refresh, and headroom requirement ≥ X V.
Cross-link only (no expansion here)
- Bootstrap sizing details → High-Side Gate Driver page.
- Interlock/deadtime internals → Half-Bridge / Full-Bridge Driver page.
- Protection tuning (DESAT/blanking/clamp) → Protection & Control page.
- Reinforced isolation and integrated bias → Isolation & Integration pages.
H2-05 · High-Side Biasing for Main Bridge
Goal: bias that does not steal ZVS reserve
High-side bias selection is finalized by application stability, not by formulas. A stable high-side supply prevents UVLO oscillation, preserves deadtime/ZVS reserve, and avoids “half-drive” behavior during line/load/temperature corners.
Bootstrap go / no-go criteria (application checks)
Refresh guaranteed?
Switching pattern must provide consistent refresh opportunities across all operating modes (startup, brownout recovery, steady-state).
Duty / on-time margin?
High-side on-time and off-time must both support charge and hold-up; avoid conditions where the supply droops during extended intervals.
Frequency behavior stable?
If frequency sweeps or burst/skip modes occur, refresh cadence must remain valid under the worst case.
UVLO recovery clean?
UVLO must not chatter; recovery must be deterministic and must not create partial conduction events.
Boundary Component sizing and detailed bootstrap equations belong to the High-Side Driver subpage.
LLC traps (why refresh can fail in real builds)
- Light-load / burst: refresh becomes intermittent; VHB may droop periodically and trigger UVLO instability.
- Fast frequency transitions: cadence changes; a previously safe refresh assumption can break at the sweep extremes.
- Startup and brownout edges: uncontrolled intervals can appear; bias droop during these windows causes timing drift and loss of ZVS reserve.
Isolated bias tradeoffs (why it helps, what it demands)
Benefits
Stable headroom independent of refresh, better behavior under sweep/burst, and clearer control of UVLO boundaries.
Primary risk
Common-mode current paths must be managed; uncontrolled return paths can inject noise into control and sensing domains.
Integration focus
Define return paths, place decoupling at the driver pins, and maintain strict partition rules across the barrier.
Acceptance anchors (placeholders)
- VHB headroom: ≥ X V across line/load/temperature corners (including sweep and light-load modes).
- No UVLO chatter: startup and brownout recovery repeated N times without oscillation or partial conduction.
- Stable behavior: high-side bias does not introduce timing drift that collapses ZVS reserve.
H2-06 · Synchronous Rectifier Drivers
Role: efficiency lever and rework hotspot
SR drives efficiency and thermal headroom in the secondary stage, but it is sensitive to detection windows and noise. This section focuses on criteria, timing windows, protection hooks, and acceptance for stable production behavior.
Two operating modes (application view)
Self-driven SR
Simpler and fast response, but detection is more exposed to parasitics and noise; mistiming risk increases under ringing and load steps.
Controlled SR
Stronger controllability and coordination with main bridge timing, but requires explicit minimum on/off constraints and validated sync relationship.
Selection anchor
Decide by noise environment, allowed sync error budget, and the acceptance requirements for reverse energy and spikes.
Conduction criteria: define windows, not slogans
- Turn-on window: permit conduction only when secondary current direction and device voltage condition indicate forward power transfer.
- Turn-off window: force off before reverse energy dominates or before mis-sync spikes appear.
- Margins: windows must include noise and temperature margin to avoid chatter and heat concentration.
Rule SR must be “windowed” with a clear pass/fail definition across line/load transients.
Mis-detect cost (what goes wrong and how it shows up)
False turn-on
Backfeed and heating risk; can excite spikes and trigger upstream protection responses.
False turn-off
Efficiency drop and larger ripple/spike signatures; thermal distribution shifts and EMI margin can degrade.
First checks
Reverse-current event count (placeholder), Vds/Vf window violations, and hotspot repeatability across N cycles.
Protection hooks and acceptance (placeholders)
- Overcurrent / overtemperature: SR transitions to a defined safe state; no unstable oscillation during faults.
- Reverse-current limiting: reverse energy events remain bounded (≤ X) under the defined Y window.
- Production acceptance: efficiency ≥ X% (Y point) and temperature rise ≤ Z°C with no persistent backfeed behavior.
H2-07 · Protection Integration (Application View)
Goal: protection as a closed-loop exit path
This section connects protection into a single application-level closure for PFC + HB/FB/LLC with SR: detect → report → arbitrate → disable → confirm safe state. It avoids parameter encyclopedias and focuses on system-safe retreat with measurable acceptance.
Risk map (what must be handled in this chain)
Main bridge risks
Cross-conduction overlap, overcurrent/short events, overtemperature, and loss-of-ZVS leading to rapid loss and thermal escalation.
SR risks
Backfeed/reverse energy, secondary short, and mistimed sync causing current spikes and unstable behavior.
Key requirement
All faults must converge to a deterministic safe gate state with bounded delay across domains.
Fault behavior classes (decide the exit strategy)
- Fast faults (µs-class): overlap/short/critical overcurrent → hard disable path dominates; energy must be bounded.
- Soft faults (ms-class): overtemperature, overload, ZVS degradation → controlled power reduction or stop, then safe off.
- SR-specific hazards: prevent reverse energy and mis-sync spikes during both normal operation and shutdown transitions.
Rule A fast fault must never depend on soft control loops to reach a safe gate state.
Fault-chain wiring (what connects to what)
Report path
/FLT (main and SR domains) → controller arbitration. Use fail-safe signaling behavior across domains.
Disable path
/EN (or equivalent) must force gate outputs to safe state even under dv/dt stress and brownout conditions.
Soft shutdown
Used only after the hard-disable path is guaranteed; controls energy and avoids secondary disturbances.
Latch vs auto-retry
Selection is based on energy risk and repeatability: high-energy faults favor latch; bounded-energy faults may allow controlled retry.
Acceptance anchors (placeholders)
- Fault-to-safe-off: ≤ X µs from detection/report to verified safe gate state (main and SR).
- Repeatability: N repeated fault events without damage; energy remains controlled (placeholder Y).
- No reverse energy runaway: SR behavior prevents backfeed during shutdown and retry cycles.
H2-08 · Timing, Matching & EMI Control Knobs
Goal: from “works” to production-ready
This section consolidates driver-related knobs into an executable set that controls the trade between EMI, loss, and ZVS reserve. It standardizes what to tune and what to verify for repeatable builds.
Timing knobs (main bridge): ZVS reserve is a budget
- Deadtime sets the commutation interval; too short risks overlap, too long increases diode conduction time.
- Propagation delay (tPD) and drift consume reserve; drift must be bounded across temperature and bias.
- Skew (Δt) compresses effective deadtime and creates asymmetry between arms or phases.
Acceptance Allowed deadtime error + drift + skew ≤ X ns (placeholder) within the defined ZVS reserve.
Timing knobs (SR): sync error creates spikes
- Early turn-on can cause current spikes and recovery stress.
- Late turn-off can allow reverse energy and destabilize the output stage.
- Window misalignment converts “efficient rectification” into hidden heating and EMI growth.
EMI control knobs (driver-related only)
Rg_on
Controls turn-on dv/dt; reduces EMI but may increase switching loss.
Rg_off
Controls turn-off ringing and false turn-on risk; impacts overshoot and tail behavior.
2-level
Fast primary + gentle secondary edges to balance loss vs EMI margin.
Clamp
Suppresses Miller-induced gate lift during high dv/dt events.
Ferrite / series
Damping tool to reduce ringing; validate that waveforms remain within loss and timing budgets.
Production acceptance pack (placeholders)
- EMI margin: ≥ X dB in the defined Y band.
- Efficiency: ≥ X% at the defined Y operating point, with temperature rise ≤ Z°C.
- ZVS success: ≥ X% across the defined line/load window; no hidden heating from false turn-on.
H2-09 · Key Specs You Must Lock (for this application)
Scope: application-only spec subset
This section locks only the specification subset that directly governs ZVS reserve, false turn-on risk, EMI margin, thermal stability, and qualification constraints in PFC + HB/FB/LLC with SR. General “selection encyclopedia” coverage belongs to the Key Specs & Selection hub page.
Peak I vs Qg
UVLO on/off
tPD
Skew
CMTI
-Voff / clamp
Pkg / temp / creepage
Peak source/sink current vs Qg (reverse from tr/tf)
Why it matters
Too weak: tr/tf stretches, switching loss rises, ZVS reserve collapses. Too strong: dv/dt increases, EMI and false turn-on risk rise.
What to lock
Define target tr/tf window (placeholders) from loss/EMI goals, then verify the driver can move the effective Qg in that window with margin.
How to verify
Gate waveforms meet tr/tf limits (X/Y), efficiency ≥ X% (Y point), and temperature rise ≤ Z°C (placeholders).
UVLO (independent on/off thresholds preferred)
Why it matters
UVLO chatter can create partial drive states, break deadtime/ZVS budgeting, and trigger unstable restart behavior.
What to lock
Independent on/off thresholds with adequate hysteresis; deterministic recovery under startup and brownout transitions.
How to verify
No UVLO oscillation across N starts and brownout recoveries; high-side bias headroom remains ≥ X V (placeholders).
Propagation delay + channel matching (ns-class budgets)
Why it matters
Deadtime and ZVS windows are consumed by tPD and skew; drift in corners can erase margin and create overlap risk.
What to lock
tPD (including drift) and inter-channel skew budgets aligned to the deadtime/ZVS reserve (placeholders).
How to verify
Measure tPD and skew across temperature and supply corners; ZVS success ≥ X% in the defined Y window (placeholders).
CMTI / dv/dt immunity (high-side and isolation stress)
Why it matters
High dv/dt can induce false turn-on, spurious faults, or input misinterpretation; failures are often intermittent and hard to debug.
What to lock
CMTI rating and input robustness consistent with target switching speed and layout constraints.
How to verify
Under expected dv/dt stress, false-trigger events = 0 and fault paths behave deterministically (placeholders).
Negative Voff / clamp / two-level + package/creepage/temp
Why it matters
SiC/GaN sensitivity to Miller injection can require -Voff and clamp features. Package, creepage, and temperature are production and safety gates.
What to lock
Feature set needed for the switch technology and dv/dt; package thermal path and safety spacing aligned to compliance targets.
How to verify
False turn-on = 0 (placeholder), thermal margin holds across corners, and safety spacing assumptions match the certification plan.
H2-10 · Design Checklist (Design → Bring-up → Production)
How to use: gate-based workflow
This checklist is organized as a production workflow with gates. Do not tune efficiency or EMI until timing and protection gates are stable. Each gate has a measurable exit criterion (placeholders).
Timing
Protection
ZVS validate
EMI tune
Production gates
Design: gate loop and partition
- Kelvin source: route driver return to Kelvin-source reference; avoid shared power return segments.
- Loop area: minimize gate loop area and keep high di/dt nodes away from sensing and barrier boundaries.
- Partition returns: do not allow return currents to cross power/control/sense partitions.
Design: initial Rg strategy (stable first, then faster)
- Initialize conservative: prioritize stable turn-off and false turn-on immunity before reducing switching loss.
- Split Rg_on/off: separate knobs for dv/dt and ringing control; validate waveforms before tightening.
- Two-level only when needed: use two-level edges when EMI margin is tight but loss must be preserved.
Design: high-side bias + UVLO validation points
- Bias headroom: validate VHB headroom ≥ X V across line/load/temperature and sweep/burst corners.
- UVLO behavior: confirm no UVLO chatter and deterministic recovery under brownout events (N cycles).
- Corner modes: explicitly test the modes that break refresh assumptions (light-load and transitions).
Design: protection strategy (latch vs retry) and energy bounds
- Strategy decision: high-energy faults favor latch; bounded-energy faults may allow controlled retry.
- Fault-to-safe-off: define and verify fault propagation to safe gate state ≤ X µs (placeholder).
- Repeatability: repeat N fault injections without damage; confirm energy remains controlled.
Bring-up: verify timing and protection before efficiency
- Timing gate: interlock, deadtime, tPD and skew measured vs budgets.
- Protection gate: /FLT → /EN → safe-off is deterministic under noise and dv/dt.
- ZVS/ZCS gate: define waveform criteria for “true ZVS” and validate across the target window.
- SR gate: calibrate turn-on/turn-off windows; confirm reverse-energy events ≤ X.
- EMI/efficiency tuning: only after gates 1–4 pass; tune knobs with margin tracking.
Production: measurable items + documentation pack
- ATE-friendly metrics: tPD/skew bins, UVLO thresholds, fault path behavior, and isolation sampling strategy (placeholders).
- Process gates: golden waveforms, acceptance thresholds, and change-control records.
- Documents: EMC evidence, safety spacing assumptions, and fault-safe explanation for audits.
H2-11 · Applications & IC Selection
Deliverable: deployment playbooks + a selection decision tree
Inputs
Vin / Pout / fs, target ZVS window, switch tech (SiC/GaN/LV MOSFET), dv/dt noise level, isolation class,
EMI margin target, protection policy (latch vs retry), production constraints (temp/creepage/package).
Outputs
Main-bridge driver class (A/B/C) + SR class (SR-1/2/3) + bias strategy (bootstrap vs isolated bias),
plus a minimum feature set (deadtime control, clamp, skew budget, fault path).
Boundary
This section selects combinations and validates decision gates. It does not repeat detailed theory or parameter encyclopedias.
Main driver A/B/C
SR-1/2/3
Bootstrap / Isolated bias
Knobs
Protection paths
Production gates
Typical configuration templates (PFC + LLC main bridge + SR)
Template A — Non-isolated main bridge (bootstrap), MOSFET-centric
- Main bridge: half-bridge driver (bootstrap) → MOSFET HB/FB or LLC primary.
- SR stage: adaptive SR controller or controlled SR controller based on noise and window stability.
- Best for: moderate dv/dt, stable refresh, cost/volume priority.
Bootstrap
Deadtime discipline
Rg split optional
Template B — Isolated main bridge for high dv/dt (SiC/GaN-leaning)
- Main bridge: isolated gate driver(s) with strong dv/dt robustness and tight skew budgeting.
- Bias: isolated bias supply recommended when refresh stability is not guaranteed (sweep/burst/transients).
- SR stage: controlled SR with stricter windowing when secondary noise is high.
High CMTI
Low skew
Fault path
Template C — Protection-tight main bridge + production-ready SR
- Main bridge: isolated driver class with protection hooks (fast safe-off, clamp features).
- SR stage: SR controller class chosen by reverse-energy bound and window repeatability targets.
- Best for: tight reliability targets and repeatable production gates.
Clamp / -Voff option
Deterministic safe-off
Qualification focus
Note: The decision tree below selects driver classes and SR classes, then validates acceptance anchors (placeholders X/Y/Z).
SR selection branch (self-driven vs controlled vs SR controller)
SR-1: Adaptive SR controller
Prioritizes efficiency with adaptive timing, but still requires window stability checks under ringing/noise.
SR-2: Controlled SR controller
Stronger controllability and window discipline; preferred when secondary noise and reverse events must be tightly bounded.
SR-3: SR controller with stronger protection posture
Selected when reverse-energy and fault behavior must be deterministic across production variation and test corners.
Acceptance anchors (placeholders)
- Reverse-energy / backfeed events: ≤ X in the defined Y window.
- Window stability: no chatter/oscillation across N cycles and temperature corners.
- Thermal outcome: temperature rise ≤ Z°C at Y point.
Isolation & bias choice (bootstrap vs isolated bias)
Bootstrap preferred when
Refresh is guaranteed across all modes (startup, sweep/burst, brownout recovery) and UVLO behavior is clean.
Isolated bias preferred when
Refresh stability is not guaranteed or dv/dt noise is high; bias headroom must be stable across corners.
Production hook
Bias choice must be validated by headroom and “no UVLO chatter” gates across N cycles (placeholders).
Bias supply part number examples (secondary bias options)
TI UCC14240 / UCC14241
Isolated bias supply family suitable for building stable high-side driver rails (validate power and noise budgets).
Analog Devices ADuM6000 / ADuM5000 (isoPower)
Isolated power options for low-to-moderate bias rails; verify output power and switching noise coupling.
Murata MGJ2 series (isolated DC-DC module)
Module option for isolated bias; verify EMI filtering and common-mode return control.
Knobs mapping (targets → required features)
Efficiency target tight
Lock tr/tf and ZVS reserve first; then tune gate speed with split Rg_on/off and controlled slew where available.
EMI margin tight
Prefer controllable edge shaping (split Rg, two-level turn-on/off where required), plus clamp support for false turn-on immunity.
Reliability / protection strict
Prioritize deterministic fault propagation to safe-off and repeatable behavior under fault injection (placeholders).
Production constraints strict
Prioritize package thermal path, temperature rating, creepage/clearance compatibility, and measurable ATE gates.
Candidate device buckets (with specific part numbers)
Main-bridge driver buckets (A/B/C)
Driver Class A — Non-isolated HB drivers (bootstrap path)
Examples: TI UCC27714, TI UCC27211, Infineon IRS21867S. Use when refresh is guaranteed and dv/dt noise is manageable.
Driver Class B — Isolated drivers (tight skew budgeting)
Examples: TI UCC21520, Analog Devices ADuM4121, Silicon Labs Si823H1. Use when high dv/dt or domain separation requires isolation and robust input behavior.
Driver Class C — Isolated drivers with stronger protection posture
Examples: TI UCC21750, Analog Devices ADuM4135. Use when false turn-on immunity, fast safe-off behavior, and protection integration are strict gating items.
PFC (boost / totem-pole stage) low-side driver examples: TI UCC27524A, Infineon 1EDN7550. Validate gate charge and dv/dt/EMI constraints for the PFC switch stage.
SR buckets (SR-1/2/3) with part numbers
SR-1 — Adaptive SR controllers
Examples: TI UCC24612, Infineon IR11688S, NXP TEA1795. Select when efficiency is primary and window stability is achievable.
SR-2 — Controlled SR controllers (tighter window discipline)
Examples: onsemi NCP4306, MPS MP6924A, TI UCC24610. Select when reverse-energy bounds and noise-robust timing windows are strict.
SR-3 — Production-tight SR posture (deterministic behavior focus)
Examples: TI UCC24636 (family option), plus SR-2 parts when configured with stricter disable/fault handling. Select when qualification gates emphasize repeatability under transient and fault injection.
Selection note: SR choice must be validated against reverse-energy events ≤ X and window stability across N cycles (placeholders).
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H2-12 · FAQs
Format rule: every answer is fixed 4 lines (Likely cause / Quick check / Fix / Pass criteria). Data placeholders use X/Y/N with units (%, ns, V, µs, dB, °C) so acceptance can be copied into test plans.
ZVS disappears at light load and EMI gets worse — check deadtime or high-side refresh first?
Likely cause: Light-load ZVS window shrinks and is consumed by deadtime/tPD; or high-side bias headroom droops (refresh instability) causing weak/slow gate edges.
Quick check: Capture VDS+VGS in the same cycle at light load; log VHB/VDD for droop or ripple during sweep/burst and load steps.
Fix: Stabilize high-side bias headroom first (refresh/bias path), then retune deadtime to the minimum safe value that still fits worst-case tPD/skew.
Pass criteria: ZVS success ≥ X% over Y (Vin/load/temp window), EMI margin ≥ X dB over Y (band), repeatability: N startups with no regression.
LLC sweep shows occasional shoot-through — suspect tPD/skew drift or Miller false turn-on?
Likely cause: Worst-corner tPD or inter-channel skew reduces effective deadtime; dv/dt coupling drives Miller-induced false turn-on during the off interval.
Quick check: Measure HS/LS timing overlap margin (Δt) across sweep endpoints and temperature; probe VGS during turn-off for spikes above threshold (VTH + X V).
Fix: Re-budget deadtime for worst-case tPD/skew, then strengthen clamp / reduce dv/dt (Rg_off or two-level strategy) without breaking loss targets.
Pass criteria: Cross-conduction events = 0 over sweep Y, Δt margin ≥ X ns at corners, verified across N thermal cycles.
SR runs hot but efficiency looks “normal” — wrong SR window or wrong reverse-current criterion?
Likely cause: SR turn-on/turn-off window misalignment causes reverse conduction or late turn-off loss; current-direction / VDS criterion threshold is mis-set under noise/ringing.
Quick check: Correlate secondary current direction with SR VDS/VF around transitions; capture SR gate timing during load steps and burst/light-load modes.
Fix: Tighten SR window boundaries first (conservative), calibrate thresholds/min on/off, then reopen window gradually to recover efficiency.
Pass criteria: SR temperature rise ≤ Z°C at Y point, reverse/backfeed events ≤ X per Y minutes, stable across N cycles.
Main-bridge waveforms “look ZVS” but device temperature is high — what are pseudo-ZVS signs to check?
Likely cause: VDS crosses near zero due to ringing, not true zero-voltage turn-on; residual charge and diode recovery create hidden loss even when scope looks “clean”.
Quick check: Check turn-on timing relative to the true window (current direction + VDS settling), not a ringing zero-cross; compare hot vs cold switching energy proxy.
Fix: Shift deadtime/edge shaping so turn-on lands inside the true window; damp ringing with driver knobs (two-level / Rg split / clamp as applicable).
Pass criteria: At turn-on, VDS residual ≤ X V (settled), ZVS success ≥ X% over Y, junction proxy temperature rise ≤ Z°C across N cycles.
Increasing Rg_off passes EMI but efficiency drops — how to replace it with two-level or clamp?
Likely cause: Large Rg_off slows turn-off and increases switching loss; EMI improves because dv/dt decreases, but loss penalty becomes dominant.
Quick check: Compare dv/dt, di/dt, and turn-off transition time under two settings; correlate efficiency drop with longer turn-off interval and higher thermal rise.
Fix: Use two-level turn-off (fast then gentle) to keep EMI low while limiting loss; use clamp to prevent false turn-on without over-slowing edges.
Pass criteria: EMI margin ≥ X dB over Y band, efficiency ≥ X% at Y point, temperature rise ≤ Z°C, false turn-on events = 0 over N runs.
High-side UVLO does not trip but gates feel “soft” — bootstrap capacitor or diode is the prime suspect?
Likely cause: VHB headroom droops dynamically without crossing UVLO; bootstrap recharge is insufficient under sweep/burst/light-load; diode recovery/forward drop reduces effective refresh.
Quick check: Capture VHB during worst transient (sweep endpoint, load step, burst); look for repetitive droop or slow recovery; compare against gate edge rate change.
Fix: Increase refresh robustness (bootstrap capacitance/charge path margin) and reduce refresh sensitivity; if mode coverage is incomplete, switch to isolated bias.
Pass criteria: VHB headroom ≥ X V across Y (line/load/temp), no soft-gate recurrence across N start/stop cycles, UVLO chatter = 0.
SR occasionally backfeeds and triggers protection — check sync relation or direction-detect threshold?
Likely cause: SR window is misaligned to the primary timing at corner conditions; direction/threshold logic mis-detects due to ringing/noise, causing early-on or late-off.
Quick check: Capture primary timing markers and secondary current direction at the backfeed moment; classify failure as early-on vs late-off vs threshold noise.
Fix: Tighten SR window and strengthen noise immunity first, then expand window carefully; enforce deterministic disable/fault linkage on abnormal detection.
Pass criteria: Backfeed events ≤ X per Y minutes, protection false trips = 0, stable across N load steps and temperature corners.
/FLT asserts but one abnormal gate pulse still occurs — which segment of the fault chain is not “hard”?
Likely cause: /FLT→/EN→driver-disable path has a propagation gap, polarity/pull-up mismatch, or cross-domain path is not hardware-prioritized to force safe-off immediately.
Quick check: Probe /FLT, /EN, and VGS simultaneously; locate whether the pulse sits inside the propagation window (tFAULT) or inside a control logic window.
Fix: Hard-wire disable priority (direct-to-driver where applicable), reduce propagation gap, and validate pulls/levels so disable is immediate and unconditional.
Pass criteria: fault-to-safe-off ≤ X µs, abnormal pulses after /FLT = 0 over N fault injections, recovery behavior consistent across N cycles.
ZVS success rate drops when hot — is deadtime budget consumed or driver output impedance drifting?
Likely cause: Temperature drift shifts effective tPD/skew and edge rates; ZVS window reserve shrinks and deadtime becomes insufficient or too long for the hot corner.
Quick check: Measure tPD/skew and tr/tf at cold vs hot; overlay ZVS failure points against these drifts under the same operating window.
Fix: Re-lock timing budgets for hot worst case; adjust drive strength/knobs to keep edges inside target while preserving EMI and false-turn-on margins.
Pass criteria: Hot-corner ZVS success ≥ X% over Y, efficiency ≥ X% at Y point, temperature rise ≤ Z°C, verified over N thermal cycles.
Passes EMI in one lab, fails after harness/grounding changes — which common-mode path to locate first?
Likely cause: Harness/grounding changes alter common-mode return and coupling paths; dv/dt-driven common-mode current increases, often linked to gate edge shaping and partition/return control.
Quick check: Under the failing setup, measure common-mode current/noise hot spots (current probe / near-field) and correlate with gate dv/dt and switch-node ringing.
Fix: Reduce sensitivity using driver knobs first (Rg split, two-level, clamp, slew control), then enforce controlled return paths (bonding/shield/partition rules).
Pass criteria: EMI margin ≥ X dB over Y band for both grounding setups, performance delta ≤ X (efficiency/thermal), stable across N repeats.
Production spot-check shows poor consistency (delay/UVLO drift) — which test definition must be unified first?
Likely cause: Inconsistent test conditions and definitions (supply, load, temperature, trigger point, sampling window, measurement threshold) inflate apparent drift.
Quick check: Re-test the same units under a single frozen setup and trigger/window definition; quantify how much variation is procedural vs intrinsic.
Fix: Freeze measurement definitions (trigger, threshold, window) and fixtures first, then define bins and sampling strategy for tPD and UVLO across batches.
Pass criteria: Under the unified definition, tPD spread ≤ X ns and UVLO spread ≤ X V over N lots; repeatability ≥ X% across N retests.
Short-circuit protection is too slow and devices sometimes die — tune blanking/soft turn-off first or external clamp first?
Likely cause: Blanking is too long or soft turn-off is too gentle, exceeding short-circuit energy; or external clamp/energy path is insufficient for the transient.
Quick check: Run controlled fault injection and measure fault-to-safe-off and energy proxy (peak current, duration, VDS overshoot) to locate detection vs energy-path limitation.
Fix: Tighten blanking and speed up safe turn-off within stability limits, then reinforce external clamp/energy path only if energy still exceeds the bound.
Pass criteria: fault-to-safe-off ≤ X µs, peak fault current ≤ X A for Y duration, and N repeated faults cause no damage or parameter shift beyond X%.
