Temperature sets lifetime limits, package sets the thermal escape path, and creepage/clearance sets safety acceptance. A gate driver is “ready” only when selection is closed by validation and documentation.

Temp = Ta / Tj / Tstg as separate constraints.

• Ta (Ambient): the external boundary condition; it does not guarantee silicon survival.
• Tj (Junction): the reliability driver; design decisions must track Tj margin under worst case.
• Tstg (Storage): a handling limit; it must not be mistaken as operational reliability.
• Key rule: “Functional at hot” is not the same as “reliable for life at hot.”

Package = thermal impedance under stated conditions (not a universal constant).

• θJA: board- and airflow-dependent; only valid with its test setup.
• θJC / ψJT: better for comparisons across packages when used with consistent assumptions.
• Thermal path: die → leadframe/EP → copper spreading → ambient.

Creepage / Clearance = safety geometry that must hold on the PCB, not only in the package.

• Clearance: shortest distance through air.
• Creepage: shortest distance along an insulating surface.
• Key rule: package values are the ceiling; the PCB layout is the real measurement.

Temperature fields (budget & evidence):

Thermal/package fields (path & implementation):

Creepage/safety fields (acceptance & traceability):

Next chapters will convert these fields into: temperature budgeting, package selection, and creepage rules.

This page focuses on thermal and safety acceptability. Topics below are referenced only as outcomes or constraints, and are expanded in their dedicated pages to prevent cross-over.

• Protection waveforms: DESAT, Miller clamp, two-level switching (expanded elsewhere).
• Timing/CMTI mechanisms: delay matching, dv/dt immunity (expanded elsewhere).
• EMI deep dive: return-path / radiation tuning (expanded elsewhere).

The loop highlights that temperature, package thermal path, and creepage/clearance must converge into a single evidence-backed decision.

Field failures cluster around combined stresses: higher ambient temperature, weaker thermal escape paths, and compromised safety geometry from PCB details, contamination, humidity, or process drift. The goal here is rapid classification: temperature-driven, thermal-path-driven, or spacing-driven.

Symptom: works at room temperature, fails in enclosure or hot soak.

Mechanism (page scope): insufficient Tj margin due to underestimated Ta or hidden self-heating.

Fast check: log Ta + board temperature, then estimate Tj using a consistent method (case proxy or thermal model).

Next on this page: H2-3 (temperature ratings) and H2-4 (derating & lifetime budget).

Symptom: calculations look fine, but IR camera shows hotspots or unexpected local heating.

Mechanism (page scope): θJA assumptions do not match the real board, airflow, copper, or neighbor heat sources.

Fast check: compare the actual PCB heat-spreading (EP, copper area, thermal vias) against the thermal test condition used for θJA.

Next on this page: H2-6 (package selection) and H2-9 (PCB guardrails).

Symptom: package creepage looks large, yet safety review or lab measurement still rejects spacing.

Mechanism (page scope): the effective PCB creepage path is reduced by copper pours, solder mask openings, residues, humidity, or layout details that “steal distance.”

Fast check: measure the true shortest path on the PCB (along surface for creepage, through air for clearance), including keepout, mask, slots, and contamination assumptions.

Next on this page: H2-7 (definitions) and H2-10 (validation & acceptance).

• “Hot-only trips / drift” → verify Ta assumption + estimate Tj margin → go H2-3/H2-4.
• “θJA says OK, but hotspot appears” → validate EP/copper/airflow assumptions → go H2-6/H2-9.
• “Creepage passes on paper, fails in lab” → measure effective PCB path + document keepout/mask/slot → go H2-7/H2-10.
• “Passes at room, fails after humidity” → suspect surface tracking from residue/humidity → go H2-10 (evidence & acceptance).
• “Same design, different factory outcome” → treat as process/evidence drift (cleanliness, coating, mask) → go H2-10 + checklist later.

This chapter only classifies failures within Temp/Package/Spacing. Detailed protection, timing, and EMI mechanisms are intentionally kept in their dedicated pages.

A field failure is rarely “random”; it is a traceable chain that can be tested and documented.

Ambient temperature (Ta) is a boundary condition; junction temperature (Tj) governs reliability. Storage temperature (Tstg) is a handling limit and cannot be used as a lifetime guarantee.

• Ta (Ambient): the external environment that drives the thermal headroom; it is not silicon temperature.
• Tboard (Board): a practical proxy near the device; used to represent enclosure and copper heating effects.
• Tc (Case): a measurement anchor (when a defined Tc point exists); useful for consistent estimation.
• Tj (Junction): the reliability variable; decisions must track Tj,est against a target with margin.
• Tstg (Storage): non-operational; indicates survival during storage/transport, not lifetime during switching.

The rest of this page uses a single approach: translate the worst-case environment into Tj,est and compare it to Tj,target.

Industrial/automotive grades primarily define a qualified operating envelope (temperature range and validation coverage). Reliability acceptance still depends on junction temperature margin under the true worst case.

• Target junction: Tj,target = 125°C (industrial) or 150°C (high-temp program).
• Thermal headroom: ΔT_budget = (Tj,target − Ta,worst).
• Acceptance (placeholder): Pass if Tj,est ≤ (Tj,target − Margin[X°C]).
• Evidence type: specify the evidence pack category (e.g., long-run stress coverage) rather than assuming “hot operation” implies lifetime.

Margin X is a project knob. It is selected by risk (sealed enclosure, lifetime target, production variation) and is validated later.

The diagram separates what can be directly measured from what must be estimated, so temperature discussions stay consistent across reviews and labs.

Derating is not a vague safety factor. It is a controlled method to ensure Tj margin under worst-case environment, assembly variation, and lifetime targets.

• High Ta,worst: limited airflow, dense thermal neighborhood, elevated enclosure temperature.
• Sealed enclosure: strong coupling between board heating and ambient rise.
• Automotive / high reliability programs: tighter acceptance on temperature drift and long-run stability.
• Lifetime target: explicit years/hours requirement that must be backed by a stable Tj envelope.
• Production variation: board copper, assembly, coating, and heatsinking deviations that affect thermal impedance.

A trigger implies that “typical conditions” are not representative. The budget must be built from worst-case assumptions and validated.

1. Step 1 — Estimate power loss (P)

   Use supply, quiescent draw, and switching activity level to get P_est. Avoid assuming “Iq-only” or “activity-only.”

2. Step 2 — Choose a thermal model

   Pick Rth_used based on what matches reality: conditioned θJA or proxy-based ψJT/θJC.

3. Step 3 — Estimate junction and margin

   Compute Tj,est = Ta,worst + P_est × Rth_used, then compare to Tj,target with a defined margin.

• Pass criteria (placeholder): Tj,est ≤ (Tj,target − Margin[X°C]).
• If fail: reduce P (activity/frequency), reduce Rth (package/thermal path), or reduce Ta,worst (system airflow/heatsinking).
• Evidence to attach: worst-case environment record, measurement point definition, and model assumption statement.

Later chapters will expand package selection and verification details. This chapter anchors the temperature decision as a budget and an acceptance rule.

Inputs define the worst-case environment, power loss is estimated, a thermal model is selected, and the junction estimate drives a margin decision.

This section identifies the dominant heat contributors inside a gate driver and ties them to the package thermal escape path. It intentionally avoids drive-sizing decisions (peak current selection, detailed Qg-based slew tuning, or gate resistor design).

The exact split varies by topology and integration level. The purpose is not to compute exact values here, but to keep the thermal model auditable.

Use a minimal decomposition for review and traceability: P_total ≈ Iq·VDD + (Qg·Vg·f)·A + P_overlap + P_bias (P_bias only if integrated).

After identifying dominant heat blocks, the next step is to ensure the package + PCB can export that heat without violating Tj,target margin.

• Localized heat: output stages and internal bias blocks concentrate heat near the die and leadframe region.
• Escape bottleneck: the dominant temperature rise is often controlled by die-to-board coupling, not only the heat magnitude.
• Package leverage: exposed-pad and thermally efficient leadframes increase the probability that the PCB can carry heat away.

When the same electrical conditions produce very different temperature rise across builds, the bottleneck is usually the thermal path implementation.

Heat is generated inside functional blocks, then flows through the package and PCB copper before reaching ambient.

Package selection must be performed as a comparable rule set rather than a list of names. The correct thermal metric depends on whether the goal is prediction under a defined condition or comparison across packages.

• θJA: predictive only when the board and airflow condition matches the real system; otherwise it becomes misleading.
• θJC: more stable for comparing internal-to-case conduction across package candidates.
• ψJT: useful as a proxy path from a measured surface/case temperature back to junction for validation consistency.

• Exposed pad (EP): enables a low-impedance path into PCB copper when properly soldered and referenced.
• Copper spreading: determines whether the board behaves like the θJA condition used in datasheets.
• Thermal via field: connects top copper to inner planes and back copper for heat transport.

If identical electrical conditions yield widely different temperature rise across builds, assembly and copper implementation are typical bottlenecks.

Isolation packages increase creepage/clearance capability and simplify safety evidence, but their thermal path can be less efficient than exposed-pad packages due to geometry and internal conduction length.

Spacing definitions and PCB-effective creepage/clearance are expanded in the creepage chapter; this section establishes package-level trade-offs and selection fields.

The map illustrates typical package positioning: high thermal performance often competes with spacing capability, and decisions must close both constraints.

Clearance is the shortest distance through air between two conductive parts. Creepage is the shortest distance along an insulating surface between the same two conductive parts.

These factors influence required or effective spacing. They are declared as review qualifiers (no standard tables in this section).

• Clearance: define the air shortest path between Node A and Node B; declare Altitude = ___.
• Creepage: define the surface shortest path between Node A and Node B; declare qualifiers Pollution = ___, CTI = ___, Coating/Slot = Y/N.
• Geometry rule: use the true shortest path, not a visually convenient route; record the exact start/end features (pad edge, lead edge, via ring).
• Scope rule: package nominal spacing does not automatically equal PCB-effective spacing; record both if applicable.

These statements are designed to be copied into review notes and lab communication to remove ambiguity.

• Mixing paths: quoting creepage while discussing clearance (or the reverse).
• Package-only assumption: using package creepage/clearance as the final system spacing without PCB verification.
• Ignoring altitude: discussing clearance without declaring the altitude boundary condition.
• Non-minimum routing: measuring a convenient line instead of the true shortest path around edges and openings.

The left panel shows the two shortest paths for the same conductor pair. The right panel shows how a slot can lengthen creepage.

Isolation-related spacing decisions require consistent interpretation of datasheet fields and evidence. This section keeps basic/reinforced as labels and focuses on mapping: datasheet → system requirement → certificate/report evidence.

These fields are reviewed together, but they cannot replace one another in requirement statements.

• Step 1: extract system requirements: working condition, surge environment, isolation label (basic/reinforced).
• Step 2: map to datasheet fields: spacing (pkg), working voltage field, surge, and hi-pot test condition.
• Step 3: require evidence: certificate/report must cover the same package variant and a production-consistent flow.
• Step 4: produce a conclusion: accepted only when evidence matches the selected variant and stated boundary conditions.

• Variant match: the certified package/isolation structure must match the chosen ordering option.
• Flow consistency: the evidence must align with the production-intended process and revision control.
• Condition match: reported test conditions must not contradict declared system boundary qualifiers (altitude, coating, assembly context).

Evidence is not a checkbox; it is the linkage between the chosen part variant and the lab acceptance criteria.

The diagram prevents mixed interpretation by forcing a structured mapping from datasheet numbers to system needs and evidence.

Package creepage/clearance values do not automatically become system spacing. The board can silently shorten the true minimum path. This section provides practical guardrails to preserve spacing on the PCB without drifting into EMI or signal topics.

The safest approach is to define a keepout boundary that blocks copper, vias, silkscreen, and test points as a single controlled rule set.

• Boundary invasion: a small copper island, test point, or silkscreen crosses into the keepout boundary.
• Via ring surprise: stitching vias become the nearest feature and shorten clearance/creepage unintentionally.
• Mask opening pull-in: solder mask openings expose copper edges closer than expected.
• Slot without guardrails: a slot is added but keepout does not protect the slot edges, allowing a short surface path.
• Package-only assumption: using package spacing as final evidence without measuring PCB-effective geometry.
• Coating claimed, not controlled: coating is used as a justification but process records and consistency are missing.

The keepout boundary must control copper, vias, silkscreen, and test points together. Slots can extend surface paths only when the edges are protected.

Acceptance should be based on declared worst-case conditions and recorded evidence. This section defines what to test, where to measure, what to record, and how to state pass/fail criteria using threshold placeholders.

If isolation is part of the chosen driver package, acceptance should reference evidence types and variant coverage.

Each cell contains a single short action keyword to keep validation executable and audit-friendly.