Speed-grade summary (focus on what tightens)

Engineering interpretation: when moving from Sm → Fm → Fm+, the allowed t_r(max) shrinks rapidly, so the same wiring, connectors, and ESD components that were “fine at 100 kHz” can become the dominant failure driver at higher grades.

What actually changes (board-level)

• Rise-time is the first-order constraint: t_r(max) tightening compresses the allowable R_p·C_b product.
• Pull-up “window” becomes narrow: stronger pull-ups help t_r but increase low-level current and can stress VOL/IOL margins.
• Protection and interconnect are amplified: ESD capacitance, connectors, cable stubs, and poor return paths consume the t_r budget.
• Tool illusions appear: some analyzers decode with internal thresholds and filtering even when analog edges violate the mode limit.
• Hs-mode is not “Fm+ but faster”: treat it as a separate regime with special timing and validation requirements.

Timing glossary (minimum set for edge compliance)

Gate rule: t_r(30–70%) is measured against the speed-grade limit. The limit is a pass/fail boundary, not a recommendation.

Measurement checklist (repeatable, tool-agnostic)

1. Pick nodes: capture at the controller pin neighborhood and at the farthest device pin neighborhood; use the worst node for acceptance.
2. Probe discipline: minimize ground inductance (short ground spring or coax); avoid adding large probe capacitance that slows edges.
3. Bandwidth & sampling: ensure the instrument does not “shape” the edge; confirm the same edge with consistent settings.
4. Thresholds: set measurement levels at 0.3·VDD and 0.7·VDD for t_r; avoid default 50% unless explicitly justified.
5. Worst-case capture: measure under maximum loading (devices connected, longest route) and include voltage/temperature corners if relevant.

Core engineering formulas (30–70% window)

Where the constant comes from (keep the definition consistent)

• RC charge curve: V(t) follows an exponential toward VDD.
• Using 0.3·VDD and 0.7·VDD thresholds, the time difference between those crossings equals 0.8473·R·C.
• Changing the threshold window (e.g., 10–90%) changes the constant; do not mix definitions across measurements and calculations.

What breaks the simple RC assumption (and how to spot it)

• Active pull-ups / rise-time accelerators: the edge becomes piecewise (a visible “knee”); t_r no longer scales linearly with R_p.
• Current-source or special Hs mechanisms: the rise is driven by controlled current rather than passive R_p.
• Distributed RC (long routes/cables): far-node edges show extra tailing; the bus is not a single lumped C_b.
• Reflections/ringing: multiple crossings at 0.3/0.7 thresholds produce unstable t_r readings.
• Protection capacitance dominates: ESD/clamps add large C; computed R_p(max) collapses unexpectedly.
• Probe loading: changing probe type/grounding changes t_r materially; measurement is altering the circuit.

Next-step handoff (no expansion): use R_p(max) from this chapter together with low-level sink limits (VOL/IOL) to form the feasible pull-up window, then validate t_r at the worst node.

Step 1–5 workflow (inputs → window → verification)

1. Lock the mode gate: select Sm/Fm/Fm+ and take t_r(max) as the pass/fail boundary.
2. Acquire C_b: estimate or measure worst-segment bus capacitance (devices + routing + connector + protection + probe).
3. Compute the ceiling: R_p(max) = t_r(max) / (0.8473 · C_b) (30–70% definition).
4. Compute the floor: R_p(min) = (VDD − VOL(max)) / IOL(min) using the weakest sink device on the bus.
5. Choose & verify: pick R_p within the feasible window, then measure t_r(30–70%) at the worst node to confirm t_r ≤ t_r(max).

Margin rules (avoid “knife-edge” designs)

• Resistor tolerance: account for 1%/5% variation and parallel pull-ups (intentional or internal).
• VDD corners: higher VDD increases low-level current (and power) for a given R_p.
• Temperature: VOL/IOL capability and leakage shift across temperature; guard with the weakest corner.
• Protection & connectors: ESD arrays and connectors add C; a footprint-equivalent swap can move C_b materially.
• Future attachments: treat C_b as a budget; each added device/branch consumes margin.
• Measurement loading: probe capacitance and grounding can change the observed t_r; validate with consistent method.

Quick reference: R_p(max) scale vs C_b (30–70% definition)

Interpretation: as C_b rises into the hundreds of pF, R_p(max) collapses into the low-kΩ or sub-kΩ range for Fm/Fm+. This often eliminates the feasible window once VOL/IOL constraints and power are applied.

Low-level power check (why “strong pull-up” can hurt)

• Instantaneous low-level current: I_LOW ≈ (VDD − VOL)/R_p.
• Average current: I_AVG ≈ D_LOW · I_LOW, where D_LOW depends on SCL duty and SDA traffic.
• Average dissipation: P ≈ VDD · I_AVG. Consider the worst case when multiple devices pull low frequently (ACK-heavy traffic).

C_b budget template (add one line per contributor)

Treat C_b as a controlled budget. Each added device/branch consumes margin and reduces R_p(max), potentially forcing a speed downgrade.

Measure and back-calculate C_b (same 30–70% definition)

• Probe loading: probe capacitance and ground inductance can change the edge; use consistent probing.
• Non-passive pull-ups: active pull-ups or internal pull-ups change the effective R_p and invalidate the back-calc.
• Ringing/reflections: multiple threshold crossings make t_r unstable; read t_r on clean exponential segments.
• Distributed RC: different nodes show different t_r; acceptance should use the worst node.

Note: tighter speed grades shrink t_r(max) and therefore shrink the allowable C_b and R_p(max) window. Hs-mode typically requires much tighter per-line capacitance budgets than Sm/Fm/Fm+.

Card A · Series-R: placement rules and why it works

• Place near the edge aggressor: put series-R close to the node that launches the fast transition into a long trace/connector. This limits ringing and reduces EMI by lowering dI/dt at the launch point.
• Know what it costs: series-R plus downstream capacitance forms an extra RC. The bus can look “less noisy” while the downstream t_r becomes slower and violates the speed-grade limit.
• Measure at the worst receiver node: verifying only near the controller can miss the slowest edge at the far device pin (after the series-R and connector stack).
• Keep it minimal and validate: start from the smallest value that damps ringing, then step up only if needed, re-checking t_r(30–70%) each time.

Card B · ESD arrays: the capacitance redline (why footprint swaps break 400 kHz)

Treat ESD capacitance as a first-class C_b budget line item. Any added shunt capacitance shrinks the pull-up ceiling: R_p(max) = t_r(max) / (0.8473 · C_b). When C_b rises, the feasible window can disappear even if VOL/IOL are unchanged.

• Prefer low-C ESD parts on SDA/SCL, especially near connectors and test headers.
• Verify A/B by measurement: same board, same node, same 30–70% definition; compare t_r before/after ESD swap.
• Budget for variants: connector/cable and ESD vendor changes can move effective C_b enough to force a speed downgrade.

Card C · “Looks clean but fails”: common misdiagnoses and first checks

• First check: measure t_r(30–70%) at the worst receiver node and compare to the mode’s t_r(max).
• If a “knee/step” appears: suspect distributed RC, stub loading, or a series-R placed between the pull-up and the dominant capacitance.
• If ringing crosses thresholds multiple times: focus on return-path continuity and connector transitions; “filtering harder” can worsen threshold dwell and timing margins.
• Fix direction: reduce effective C_b (low-C ESD, shorter stubs, fewer branches), re-position/adjust series-R, or downgrade the mode.

Card A · Hs-mode SCL vs SDA (mechanism → consequence → verification point)

• Mechanism: SDA typically remains dominated by the open-drain + pull-up network, while SCLH can be assisted by a current-source pull-up.
• Consequence: an apparently fast SCL edge does not guarantee SDA compliance; SDA often becomes the limiting edge when C_b rises.
• Verification: measure SCL and SDA separately and include “worst transition moments” (e.g., the first rise immediately after an ACK/release sequence).

Card B · When not to force Hs-mode (why stepping back to Fm+ is often better)

• High C_b reality: connectors, ESD, test headers, and branches make small-C budgets hard to sustain.
• Distributed loading: many devices and long stubs create node-to-node rise-time spread and harder worst-case verification.
• Always-on probing/fixtures: production or debug access can permanently add capacitance.
• Power constraints: stronger pull-up assistance can increase low-level current or complicate power budgeting.
• Margin management: if assembly or vendor variants shift C_b, a stable Fm+ design can outperform a fragile Hs-mode attempt.

Decision anchor: if the board-level C_b budget cannot be tightly controlled, prioritize Fm+ margin and repeatable compliance over Hs-mode headline speed.

Card A · Bring-up verification steps (baseline → load-up → corners → external links)

1. Step 0 — lock the measurement definition: use t_r(30–70%) with thresholds tied to the current VDD (0.3VDD / 0.7VDD). Set the scope trigger/measurement thresholds accordingly.
2. Step 1 — no-external baseline: disconnect optional connectors/cables/fixtures. Measure at MCU pin and at the farthest device pin to establish intrinsic margin.
3. Step 2 — progressive loading: add devices/branches one at a time. After each change, re-measure t_r at the worst node and record margin to identify the dominant C_b contributor.
4. Step 3 — worst-case corners: re-run the same measurements at lowest VDD, lowest temperature, and maximum loading (fully populated bus, worst connector/cable stack).
5. Step 4 — external links: validate both sides of the connector (board-side and cable-side). Treat connector + cable + protection as part of the C_b budget, not “outside noise.”

Card B · “Protocol bug” vs “edge physics bug” (fast triage)

• Triage 1 — pass the edge first: if worst-node t_r exceeds the speed-grade limit, treat it as a physical-layer compliance failure (C_b/R_p/protection) before any software discussion.
• Triage 2 — avoid measurement illusions: logic analyzers can “decode” through thresholding and digital filtering. Always cross-check with a scope using 30–70% thresholds at the correct node.
• Triage 3 — then evaluate retries/timeouts: only after rise-time compliance and measurement consistency are proven, treat remaining failures as higher-layer handling (retries, timeouts, recovery policy).

Pass criteria template (accept/reject)

For production reports, extend the table with measured values and margins, and keep the measurement setup identical across builds.

Card A · Failure → Root cause → Fix (quick look-up)

Table usage: start with the symptom row, confirm the root cause by measurement at the worst node, apply the fix, then re-run H2-9 acceptance.

Card B · “Compute first, then change” priority order

Materials note

Part numbers below are concrete examples for BOM speed-up. Always verify package, value, voltage rating, tolerance, ESD capacitance, and availability before locking a design.

Card A · Selection logic (speed vs cost vs robustness)

• Short on-board bus, few devices, light protection: Fm or Fm+ is usually feasible if the worst-node t_r margin is proven.
• Large C_b, heavy protection, many connectors/cables: prioritize lowering C_b, segmenting the bus, or stepping down the mode.
• Max throughput targets: consider Hs only if C_b is tightly controlled and SCL/SDA are verified separately under corner conditions.

Card B · What “faster” costs (and why it breaks after adding protection)

• Edge cost: smaller t_r(max) pushes R_p(max) down; the window narrows and becomes sensitive to C_b drift.
• Protection cost: ESD capacitance consumes C_b budget; “low C” parts are often required for Fm+ and beyond.
• Power cost: smaller R_p increases low-level current; compute real traffic duty impact before locking values.
• Validation cost: acceptance must be proven at the worst node and worst corner; “analyzer decode” is not acceptance.

1) “100 kHz is fine, but 400 kHz shows more CRC/NAK”

Likely cause: Worst-node rise time exceeds the Fast-mode limit, typically after C_b grew (more devices/ESD/connector) or R_p is too large.

Quick check: Measure t_r(30–70%) at the farthest device pin (not only MCU). Compare “baseline (no external cable)” vs “full load” and record Δt_r.

Fix: Reduce C_b (lower-C ESD/connector, shorten stubs, reduce fanout) or reduce R_p within the computed window; if the window does not exist, step down to Sm or segment the bus.

Pass criteria: At worst node, t_r(30–70%) ≤ 300 ns (Fm), with margin ≥ 20% of the limit (≤ 240 ns) under max load and low VDD.

2) “Logic analyzer decodes, but the oscilloscope says t_r is out of spec — which one to trust?”

Likely cause: Decoder success is not compliance. The analyzer’s threshold, digital filtering, or sampling hides slow edges and ringing; compliance uses 30–70% thresholds tied to VDD.

Quick check: On the scope, set thresholds to 0.3·VDD and 0.7·VDD, measure t_r at the worst node, then repeat with the same probe/setup to verify repeatability (do not change bandwidth/probe type mid-test).

Fix: Use the scope result as acceptance. Bring t_r into spec by adjusting R_p/C_b. Use the analyzer only to correlate retries/NAKs with measured margin.

Pass criteria: Worst-node t_r(30–70%) meets mode limit (1000/300/120 ns for Sm/Fm/Fm+). Measurement repeatability: two runs differ by ≤ X ns (fixture/probe dependent).

3) “After switching to a low-capacitance ESD part, 400 kHz suddenly becomes stable — what was eating t_r?”

Likely cause: The previous ESD array added enough capacitance to push C_b beyond the budget, shrinking R_p(max) and violating the rise-time limit at the worst node.

Quick check: Keep R_p unchanged and measure worst-node t_r before/after the ESD swap; back-calculate ΔC_b using C_b ≈ t_r / (0.8473·R_p).

Fix: Treat “ESD capacitance” as a hard constraint at higher modes: choose low-C parts and minimize extra pads/stubs. If protection must be heavier, step down the mode or segment the bus.

Pass criteria: After protection is finalized, worst-node t_r(30–70%) still meets the selected mode limit with ≥ 20% margin in the max-load configuration.

4) “Making R_p smaller makes it less stable — is it VOL or ringing?”

Likely cause: Two opposite failure modes: (a) R_p too small violates sink capability (VOL rises), or (b) edges become too steep and ringing causes multiple threshold crossings.

Quick check: On the scope at worst node: (1) measure VOL during a long low (compare against device VOL spec), (2) inspect if the signal crosses 0.3·VDD / 0.7·VDD more than once within a bit.

Fix: If VOL is high, increase R_p until within sink limits (recompute R_p(min)). If ringing dominates, add small series-R (e.g., 22–47 Ω near driver) while re-checking that t_r still meets the limit.

Pass criteria: (a) VOL at worst sink load ≤ device VOL limit and stable, and (b) worst-node t_r(30–70%) meets mode limit; no repeated threshold crossings near 0.3/0.7·VDD during valid bits.

5) “Same R_p, but changing the harness/connector breaks it — C_b or reflections?”

Likely cause: The new harness adds capacitance and/or changes impedance, pushing t_r over the limit and increasing ringing near thresholds.

Quick check: Measure worst-node t_r and compare against the limit. Then look for overshoot/undershoot and multiple threshold crossings around 0.3/0.7·VDD when the harness is attached.

Fix: If t_r is the limiter, reduce C_b or increase pull-up strength within sink limits. If reflections dominate, reduce stubs, improve return path, and add modest series-R near the driver while verifying t_r.

Pass criteria: With the harness/connector installed, worst-node t_r(30–70%) meets the mode limit and margin ≥ 20%; waveform shows no repeated crossings of 0.3/0.7·VDD during valid edges.

6) “Mixing Fm+ parts with Sm-only parts — can 1 MHz work?”

Likely cause: The slowest device sets the bus electrical limit. Even if most devices can handle Fm+, the legacy part may require slower edge/rate behavior and larger timing margins.

Quick check: Under the intended 1 MHz configuration, measure worst-node t_r and confirm it meets the Fm+ line; then repeat with the legacy device present vs removed (same bus) to see whether it changes the edge budget.

Fix: If the legacy device forces larger C_b or reduces margin, keep that segment at Fm/Sm or isolate it using a mux/buffer so the Fm+ segment can meet its rise-time budget independently.

Pass criteria: Fm+ segment acceptance: worst-node t_r(30–70%) ≤ 120 ns with ≥ 20% margin (≤ 96 ns), and the legacy segment meets its own selected mode limit.

7) “SCL looks slower than SDA — why?”

Likely cause: SCL often has higher effective C_b (more pins/branches, longer trace, different protection/connector path), so the same pull-up yields a larger RC rise time at the worst node.

Quick check: Using the same setup, measure t_r(30–70%) for SCL and SDA at the same worst node and back-calculate C_b for each line with C_b ≈ t_r / (0.8473·R_p).

Fix: Reduce SCL-specific capacitance (routing/stubs/protection), or use separate pull-ups per line (if architecture permits) to equalize rise-time margins without violating sink limits.

Pass criteria: Both lines meet the selected mode limit at worst node (Sm/Fm/Fm+: 1000/300/120 ns) with documented margin; C_b(SCL) and C_b(SDA) estimates are within expected budget.

8) “Back-calculating C_b from known R_p + measured t_r gives 2× the estimate — why?”

Likely cause: The estimate missed hidden capacitance (probe/fixture, connector, ESD, cable) or the waveform is not a pure RC (ringing/active pull-up/accelerator changes the edge shape).

Quick check: Repeat the measurement with a lower-capacitance probe or shorter ground lead; measure at two nodes (MCU vs far node). If C_b “grows” with distance, distributed capacitance/connector/cable is dominant.

Fix: Update the C_b budget table with the missing contributors and re-compute R_p(max). If active edge-shaping exists, accept that 0.8473·R·C is only an approximation and use measured t_r as the source of truth.

Pass criteria: After updating the budget, measured worst-node t_r(30–70%) meets the mode limit with ≥ 20% margin, and measurement setup is documented (probe type, bandwidth, thresholds).

9) “At lower temperature, 400 kHz gets worse — how to reserve t_r margin?”

Likely cause: Corner conditions shift edge behavior (device drive, leakage, and effective load). The design passes typical but fails at the worst electrical corner when the margin is too thin.

Quick check: Build a corner matrix: low VDD × low temp × max load. Measure worst-node t_r at each corner and compute margin = (limit − measured).

Fix: Tighten the design target (internal goal) to ≤ 0.8× of the spec limit at typical conditions, then re-check at corners; if still failing, reduce C_b, segment the bus, or step down the mode.

Pass criteria: For Fast-mode: worst-node t_r(30–70%) ≤ 300 ns at low VDD, low temp, and max load; margin ≥ 10% of limit (≤ 270 ns).

10) “How to quickly compute R_p bounds and land on an E24 value?”

Likely cause: Pull-up selection fails when only R_p(max) is considered (rise time) and R_p(min) is ignored (sink capability / VOL), leaving no safe window after tolerances and added capacitance.

Quick check: Determine mode t_r(max) and worst-case C_b. Compute R_p(max)=t_r(max)/(0.8473·C_b) and R_p(min) from the weakest IOL/VOL requirement; confirm R_p(min) < R_p(max).

Fix: Pick an E24 value near the middle of the window (geometric middle is preferred), then validate by measuring worst-node t_r and VOL at max load. If window is narrow, prioritize reducing C_b or segmenting.

Pass criteria: Selected E24 R_p yields (1) worst-node t_r(30–70%) ≤ mode limit (1000/300/120 ns) with documented margin, and (2) VOL meets sink capability at max load (per device spec).

Scope guard: This FAQ section intentionally does not discuss addressing, arbitration, or clock stretching. All checks and fixes are limited to mode choice, rise-time compliance, pull-up window, bus capacitance, and measurement/EMC pitfalls.