1. Open-drain power is often duty-cycle dominated. Compute P_pullup_avg ≈ (V²/R)·D_low; measure D_low over a fixed window (e.g., 60 s) with a logic analyzer.
2. Standby Iq is a frequent “cannot-sleep” root cause. Buffers/isolators/bridges can sit in listening states; confirm the actual Iq_state (active/idle/standby/shutdown), not just “bus idle.”
3. Reconcile system power by decomposition, not by datasheet copying. Use a single accounting model: Pull-up static + C·V² dynamic + Iq + regulator loss, then rank top contributors before changing hardware.

1. Log rails & baseline: record Vrails, total current, temperature, and whether the system is “idle” by workload definition.
2. Lock device states: verify each relevant IC is in the intended Iq_state (standby/shutdown vs listening).
3. Quantify traffic: measure D_low (SDA/SCL) and estimate f_toggle (SPI/UART edges) over a fixed window.
4. Run a first-pass decomposition: compute static vs dynamic vs Iq; identify the top contributor(s) before attempting any optimization.

Pass criteria (placeholder): idle current stays within X mA for Y minutes at the defined idle workload and temperature range.

Total power is the sum of rail contributions plus regulator losses. Use equivalent current to reconcile with measurements:

Practical order: first close the budget on each rail (currents), then add regulator efficiency terms. This prevents “η as a black box.”

• V_pullup, R_pullup (effective), and pull-up rail ownership.
• D_low_SDA, D_low_SCL measured over a fixed time window (e.g., 60 s).
• C_bus_equiv (estimated or measured) and the topology version used.
• f_toggle (effective toggle rate) derived from traffic/edge statistics.
• Iq_state per device (active / idle-listening / standby / shutdown) and wake source enabled.
• η_reg (or measured input/output power for each regulator stage).
• Environment: temperature, cable/connector configuration, defined “idle workload.”

Pass criteria (placeholder): the model estimate matches measured power within ±X% across Y operating states (idle / burst / sustained).

1. Measure rail currents in the defined state (idle/burst). Record window length and temperature.
2. Compute static pull-up using (V²/R)·D_low. If this term is already close to measured rail power, optimization must target duty/V/R first.
3. Estimate dynamic using α·C·V²·f and convert to I_dynamic_equiv. If the gap appears only at higher traffic, dynamic is likely the driver.
4. Add Iq_state per device. If measured current remains high at “bus idle,” the system is not in the intended low-power state.
5. Attribute the remaining difference to regulator loss / leakage / back-powering, then validate by isolating rails and toggling wake sources.

• In scope: static pull-up loss math, how to measure D_low, and how to reconcile pull-up rail current.
• Out of scope: rise-time compliance and detailed pull-up sizing constraints (link to the owner page: “Open-Drain & Pull-Up Network / Rise-Time Budget”).

During low level, the pull-up resistor conducts a DC current. Average loss scales linearly with the low-level duty fraction:

Interpretation: smaller R_pullup increases I_low linearly. If D_low is non-trivial, average loss rises quickly even when traffic “looks small.”

1. Define the workload state (idle / burst / periodic polling). “Bus idle” must match a system definition, not a guess.
2. Capture SCL/SDA with a logic analyzer over a fixed window (recommended: 60 s for baseline, and 10 s for quick checks).
3. Compute duty by counters: D_low = T_low / T_window for SDA and SCL separately.
4. Optional (power-focused) attribution: bucket by address or transaction type to find which device dominates low time (this improves optimization focus without expanding protocol theory).
5. Reconcile against pull-up rail current using I_pullup_avg. If reconciliation closes, the dominant knob is confirmed.

Pass criteria (placeholder): predicted pull-up rail current matches measurement within ±X% across Y workload states.

• Static pull-up loss depends on low time, not on “nominal bus speed” alone.
• For a fixed payload (bytes per second), increasing SCL frequency can reduce total low time and thus reduce the static term—while the dynamic term may rise.
• After static loss is minimized, systems often become dominated by dynamic switching or Iq states; the next chapter addresses switching power with the same accounting vocabulary.

Use this approximation to connect traffic to power. It is an accounting tool: it indicates which knob (C, V, activity) dominates.

Practical note: ringing and repeated threshold crossings can behave like extra toggles. This increases effective α even when payload is unchanged.

• I²C: open-drain + RC edges → both static pull-up loss and dynamic charging can be significant.
• SPI / UART: mostly push-pull → dynamic switching is often dominant during throughput; edge speed can also increase EMI and effective α via ringing.
• When “idle current is high,” dynamic is rarely the root cause; verify Iq_state, leakage, or back-powering first.

Trigger: dynamic term ranks as a top contributor under a defined workload (from the accounting model). Choose knobs with measurable outcomes:

• Reduce V (V² leverage): lower I/O rail or shift to a lower-voltage domain where compatible.
• Reduce C (topology leverage): shorten traces, segment buses, reduce fanout, or revise cabling topology.
• Reduce f_toggle / α (traffic leverage): batch transfers, avoid unnecessary polling, reduce spurious toggles.
• Edge control (robustness leverage): series-R / limited slew / driver strength control to reduce ringing-driven extra toggles.

Pass criteria (placeholder): P_dyn drops by X% with no degradation in error rate, EMI margin, or wake reliability under the same workload definition.

• In scope: Iq state taxonomy, wake latency, retention, fail-safe I/O behavior, and partial-power-down impacts on system current.
• Out of scope: protocol recovery details and timing waveforms (link to owner pages under “Error Handling & Recovery” and bus-specific timing pages).

Use a consistent field set so Iq behavior can be compared across bridges, isolators, buffers, and PHY blocks without ambiguity:

Pass criteria (placeholder): documented state targets must map to measured rail current within ±X% across Y workloads and temperatures.

• Always listening: device remains in idle_listening (receiver-on) due to configuration defaults or missing sleep command.
• Fail-safe leakage: isolator/level-shifter fail-safe structures create leakage paths or clamp currents when one side is off.
• External DC path: bias/termination networks create steady currents even when traffic is absent (especially across long cables).
• Back-powering: I/O pins drive current into an “off” rail through ESD/clamp structures without PPD or IO-highZ guarantees.

Quick check (placeholder): isolate one block at a time (bridge / isolator / buffer), then confirm which rail current collapses first; verify off-rail voltage is not being lifted by I/O back-powering.

Pass criteria (placeholder): each tier has a documented rail-current target and a verified wake sequence with bounded latency t_wake ≤ X.

• I²C: address/edge activity wake can require receiver-on monitoring; noise/glitch tolerance must be controlled to avoid false wakes (link to recovery owner page).
• SPI: CS assertion wake is often compatible with deep sleep when CS detection is maintained; floating CS can cause repeated wake events without proper biasing.
• UART: start-bit / break / idle detect wake typically requires always-on edge detection; noise can increase effective activity and prevent deep sleep.

Compare strategies using an energy-per-cycle view. A lower sleep Iq can be negated by long wake latency or repeated false wakes.

Pass criteria (placeholder): measured energy per cycle improves by X% under the defined workload without introducing lock-up or back-powering.

• In scope: topology-level levers that change V, C, Iq state, DC paths, and regulator loss.
• Not expanded here: buffer/switch implementation details, rise-time compliance math, and EMC/SI tactics (link to owner pages under buffers, pull-up network, and EMC).

Rail voltage directly scales both static and switching terms. When compatibility allows, lowering Vpullup is often the highest-leverage change.

Pass criteria (placeholder): selected Vpullup meets VIH/VIL compatibility and reduces the modeled (and measured) rail power by ≥ X%.

• Why it saves power: smaller effective Cbus reduces switching energy (C·V²) and relaxes the need for aggressive pull-ups.
• What it costs: buffers/switches add Iq, and the Iq state must be budgeted (active vs idle_listening vs standby).
• How to decide: compare ΔP_dyn from C↓ against ΔP_Iq from added blocks using the H2-2 accounting model.

Pass criteria (placeholder): segmentation reduces the top dynamic contributor without increasing idle power beyond X.

• Cables: protection networks and biasing can create steady DC paths; leakage often grows with temperature.
• Noise-driven power: common-mode events can trigger false wakes or keep receivers listening, raising effective idle Iq.
• Isolation accounting: isolated pull-ups, bias rails, and DC-DC efficiency loss must be counted as system power, not “interface power”.

Pass criteria (placeholder): system power is reconciled at the upstream boundary (battery / main input) and closes within ±X% after including isolated rails + DC-DC loss.

1. V: lower rails when compatibility allows (V² leverage).
2. C: reduce effective capacitance (shorten, fanout control, segmentation).
3. Activity: reduce unnecessary toggles and false wakes.
4. Iq: optimize device states and swap blocks only after V/C/activity are constrained.

• Boundary: measure at battery/main input for system truth; measure at rails for attribution.
• Workload: define states (idle / typical / worst) and keep them repeatable.
• Windows: use a short window to catch pulses and a long window for average (e.g., 10 ms + 60 s).

Pass criteria (placeholder): repeated runs under the same workload produce average power within ±X%.

• Shunt + scope: best for short pulses (wake spikes, burst transfers). Errors come from bandwidth, wiring, and amplifier saturation.
• Power analyzer: best for integrated averages and energy-per-cycle comparisons. Errors come from window and sampling configuration.
• PMIC telemetry: best for long-term logging and trend correlation. Errors come from slow sampling that hides fast pulses.

1. Split contributors: pull-up static + switching dynamic + device Iq + regulator loss.
2. Convert each term into an equivalent rail current contribution for comparison with measurements.
3. Close each rail first, then close the upstream input boundary last.
4. Only after a gap remains, hunt for leakage, back-powering, and measurement bandwidth/window artifacts.

Pass criteria (placeholder): rail-level sums close to upstream input power within ±X%.

• Hidden pulses: short current bursts raise average, but disappear with low bandwidth or slow sampling.
• Floating logic: undefined pins keep blocks partially on and increase leakage.
• Ghost powering: I/O back-feeds an “off” rail through clamps or protection structures.
• ESD/TVS leakage: temperature and voltage raise leakage, turning protection into a DC path.

Quick check (placeholder): increase measurement bandwidth, extend averaging window, and verify off-rail voltages are not lifted by I/O paths.

• In scope: power fields, measurement windows, and stage gates (static, dynamic, Iq, wake).
• Not expanded here: protocol root-cause and recovery details; use owner debug/recovery pages for fixes.

Record a repeatable “power packet” under defined workload and windows (short window for pulses + long window for averages).

Pass criteria (placeholders): idle current < X; standby/shutdown current < X; t_wake < Y; reconciliation gap < ±X%.

• Add controlled patterns: BIST/loopback patterns create repeatable activity for dynamic power comparison.
• Log “workload signature”: NAK/retry/throughput as labels that explain f_toggle and retransmission-driven energy.
• Track drift: temperature, rail tolerance, and cable conditions that change leakage and false wake behavior.

Pass criteria (placeholders): per-unit power under BIST stays within ±X%; false wake rate < Z/hour; off-rail voltage lift < X.

1. Write a budget: split power into static, dynamic, Iq, and regulator loss (placeholders per rail).
2. Rank contributors: compute and measure; force a Top-1/2/3 list to avoid ambiguity.
3. Select knobs: choose the smallest set of changes that moves the dominant term.
4. Verify & regress: keep workload and windows fixed; log the portable “power packet” fields.

Verification rule (placeholder): each knob change must improve the dominant term by ≥ X% without violating error-rate or wake constraints.

• In scope: power drivers per application + selection fields (Iq states, wake behavior, PPD/fail-safe, leakage).
• Not expanded here: protocol root-cause, recovery sequences, and detailed signal-integrity design (use owner pages).

Selection should map datasheet fields into the accounting model columns: Iq, Wake, Static/DC path, Dynamic, and Regulator loss.

tokens

Pull-up became smaller (more stable) but battery drains fast — compute D_low or C·V² first?

Likely cause: Pull-up DC loss dominates because D_low is not small, so reducing R increases static power linearly.

Quick check: Measure D_low(SCL/SDA) over a 60 s window and compute P_static ≈ (V²/R)·D_low, then compare against measured rail current.

Fix: Increase R within rise-time compliance or reduce hold-low time/transactions; if dynamic dominates, reduce V and/or effective C (segmentation).

Pass criteria: Pull-up rail average current drops by ≥ X% at the same workload, and D_low stays within ±X% over Y minutes.

I²C is almost idle — why is current still high? Check Iq state or leakage first?

Likely cause: A device stays in idle-listening/receiver-on (Iq tax) or an off-state DC path exists (leakage / back-power).

Quick check: Freeze bus traffic, then toggle suspected always-on blocks (buffers/isolators/bridges) and watch step changes on the relevant rail current.

Fix: Enforce a lower-power state (standby/shutdown), disable listening features when possible, and eliminate back-power via fail-safe/PPD-capable parts.

Pass criteria: Idle rail current ≤ X mA at T = {room/hot} with bus activity held constant and wake reliability maintained.

Higher bus speed reduced power — static dropped or measurement window issue?

Likely cause: Static pull-up energy per transferred byte fell (shorter low-time total), or the measurement missed short bursts due to bandwidth/window mismatch.

Quick check: Compare (a) D_low over the same workload and (b) rail current using both a short window (ms–s) and a long window (≥60 s).

Fix: Standardize measurement boundary and windows; if static truly dropped, keep speed but verify rise-time compliance and error rates.

Pass criteria: D_low decreases by ≥ X% and the long-window average current decreases by ≥ X% with unchanged traffic volume and stable error counters.

After sleep, the bus occasionally locks up — verify wake trigger or recovery flow first?

Likely cause: Wake sequence leaves a device in an undefined I/O state (held-low / partial power), causing static loss and protocol stalls.

Quick check: Log wake sources + timestamps and capture a post-wake window showing line levels, D_low, and whether rails reached valid levels before bus activity.

Fix: Enforce a deterministic wake order (rails → I/O enable → traffic) and add a timeout-based recovery action if bus-free does not occur.

Pass criteria: Over Y wake cycles, bus-free is achieved within X ms and no held-low event persists beyond X ms.

Isolation doubled power — DC-DC loss or isolator standby Iq?

Likely cause: System input power includes converter inefficiency and remote pull-up/bias currents, not just isolator Iq.

Quick check: Measure power at the system input and at the isolated rail; estimate loss as P_loss = P_in − ΣP_rails and compare against isolator state current.

Fix: Improve DC-DC operating point/efficiency and move pull-ups/bias to lower V where possible; ensure isolator enters standby/shutdown when idle.

Pass criteria: P_loss stays below X% of P_in at idle and isolated-rail current matches the model within ±X% over Y minutes.

Adding ESD/TVS increased standby current — leakage or back-power?

Likely cause: Temperature-dependent leakage creates a DC path, or an I/O path is back-powering an “off” rail.

Quick check: Compare standby current at room vs hot and check for off-rail voltage lift (non-zero voltage on a supposedly off domain).

Fix: Use lower-leakage protection for the rail level, add back-power prevention (fail-safe/PPD), and ensure no external bias holds the line into a clamp.

Pass criteria: I_idle(T_hot) − I_idle(T_room) ≤ X mA and off-rail lift ≤ X mV under the same wiring condition.

SPI high-throughput power spikes — check f_toggle first or edge ringing/overshoot?

Likely cause: Dynamic switching power dominates (α·C·V²·f_toggle), and excessive ringing can add extra toggles/energy loss.

Quick check: Correlate rail current with throughput and verify whether current scales with f_toggle; then spot-check SCLK edges for repeated crossings (ringing).

Fix: Reduce V and effective C where possible, limit edge rate (series R / drive strength), and avoid unnecessary toggling bursts via buffering/traffic shaping.

Pass criteria: At fixed payload, average current scales within ±X% of the f_toggle ratio and peak current stays below X mA.

UART sits idle but current does not drop — receiver-on or auto-baud listening?

Likely cause: The UART block or transceiver stays in a listening/receiver-on mode to detect start bits (Iq_idle dominates).

Quick check: Toggle receiver enable and compare step current; also log whether line noise triggers wake/interrupt events during “idle”.

Fix: Use a deeper sleep mode with a qualified wake detector (break/idle filter) and disable auto-baud/listening when not required.

Pass criteria: Idle current ≤ X mA with receiver disabled (or qualified wake enabled) and wake latency ≤ Y ms.

Long-line RS-485 bias resistors burn power — how to balance fail-safe bias vs consumption?

Likely cause: Continuous DC bias current dominates standby power because the bias network forms a permanent path across the supply/termination.

Quick check: Compute I_bias from the bias network values and confirm with measured current in true idle (no traffic, stable line state).

Fix: Increase bias resistance while meeting noise margin requirements, or use a transceiver with built-in fail-safe behavior to reduce external DC biasing.

Pass criteria: Standby power contribution from bias ≤ X mW and receiver false-detect rate ≤ Z/hour under the specified cable condition.

Standby current rises at higher temperature — suspect TVS leakage or I/O clamp first?

Likely cause: Temperature-dependent leakage (TVS/ESD structures or I/O clamps) creates a growing DC path at hot corners.

Quick check: Measure idle current at room vs hot while holding the exact same rail voltages and line states; look for off-rail lift or unexpected bias.

Fix: Replace or re-bias the leaky element (lower-leakage protection, better off-state isolation) and reduce rail voltage where feasible to cut leakage.

Pass criteria: ΔI_idle(T_hot − T_room) ≤ X mA with no off-rail lift beyond X mV.

Measured average current is 30% higher than datasheet — bandwidth/window or duty stats first?

Likely cause: Measurement boundary/window misses short pulses or compares different operating states; alternatively, an unaccounted DC path exists.

Quick check: Re-measure with a defined boundary and two windows (short + long), then reconcile using the model terms (static + dynamic + Iq + loss).

Fix: Standardize workload, sampling/bandwidth, and integration window; if a residual remains, isolate by turning off blocks to find the missing term.

Pass criteria: |P_meas − P_model| ≤ ±X% for Y minutes at fixed workload and temperature.

Turning off pull-ups saves power but lines float — how to add a weak keeper without leakage?

Likely cause: Floating lines create noise-triggered toggles or false wake, but a strong keeper introduces a DC path (static leakage).

Quick check: With pull-ups off, log wake/interrupt events and line state stability; measure any residual DC current on the keeper/bias path.

Fix: Use a qualified weak hold (high-value bias, controlled keeper, or stateful retention) that avoids back-power and stays high-Z in off domains.

Pass criteria: False wake rate ≤ Z/hour and added idle current ≤ X µA (or X mA) across temperature corners.