Voltage Compatibility: VIH/VIL, 5V Tolerance, and Drivers
← Back to: I²C / SPI / UART — Serial Peripheral Buses
“Voltage compatibility” is proven only when threshold margins, dynamic edges, and power-off/hot-plug states all stay safe—otherwise use translation, buffering, or isolation. This page provides a pass/fail workflow to catch back-powering, contention, and timing-window failures early.
Definition & Boundary: What “Voltage Compatible” Really Means
“Voltage compatible” is a measurable pass/fail check: logic thresholds have margin, real waveforms stay within limits, and fault or power-state conditions do not inject current or back-power rails.
A) One-line definition + scope
- Definition: Compatible = VIH/VIL margins are positive under datasheet conditions, dynamic crossing occurs inside the sampling window, and fault/power-state behavior does not violate abs max or cause back-powering.
- Included here: threshold margins, 5-V tolerance meaning (injection/back-power risk), open-drain vs push-pull contention, power-off/hot-plug compatibility, and measurement proof.
- Excluded (link out): specific level-shifter topologies and part lists (go to the dedicated Level Translation page), detailed ESD/surge component selection (Port Protection), and isolation delay/CMTI budgets (Isolation Strategy).
B) Three non-negotiable rules (pass/fail)
C) Common misconceptions (and why they fail)
- “Same VDD means compatible.” Thresholds are receiver-defined; VOH/VOL depend on output current and temperature.
- “5-V tolerant means a wider logic range.” It usually means a safe overvoltage path; it does not guarantee VIH/VIL compatibility or safe behavior when unpowered.
- “If the logic analyzer decodes it, it’s fine.” Analyzer thresholds and sampling can hide marginal crossings and ringing-induced double transitions.
- “Overshoot is OK if it’s brief.” Abs max violations can trigger clamp conduction, injection, or long-term fragility even without immediate functional failure.
Scope Guard: stop here and route to Level Translation when…
- NMH/NML is negative or too small for the noise and grounding environment.
- VIN can exceed VDD (including hot-plug) or peer devices can be unpowered while signals remain active.
- Push-pull contention is possible (shared lines, multiple drivers, unknown power-up defaults).
- Edge-rate, ringing, or overshoot cannot be kept within abs max and stable threshold crossing without additional conditioning.
Output classification from this page: OK / Needs Shifter / Unsafe.
The Numbers That Decide: VIH/VIL/VOH/VOL + Noise Margin
Threshold compatibility is not a guess. It is a margin calculation using worst-case receiver requirements and worst-case driver guarantees under the correct load and temperature conditions.
A) The core calculation (worst-case)
Receiver thresholds: VIH(min) (minimum input voltage recognized as logic-1), VIL(max) (maximum input voltage recognized as logic-0).
Driver output guarantees: VOH(min) (minimum output high), VOL(max) (maximum output low), specified at IOH/IOL conditions.
Positive NMH/NML means the static logic window is valid; larger margins increase immunity to noise, ground bounce, and threshold drift.
Interpretation rule: Use minimum driver VOH and maximum driver VOL (worst-case), and compare to the receiver’s minimum VIH and maximum VIL.
B) 7 datasheet pitfalls that break margin checks
- VOH/VOL depend on IOH/IOL. A “high” that looks perfect at light load can collapse under required sink/source current.
- CMOS vs TTL-like inputs differ. Some inputs use ratio thresholds vs VDD; others use fixed-ish thresholds.
- Speed grade and temperature grade matter. Worst-case corners may tighten VOH/VOL and shift VIH/VIL.
- Schmitt inputs change behavior. Hysteresis improves noise immunity but the trip points differ from plain CMOS.
- Abs max ≠ recommended operating. Passing functional tests while briefly violating abs max can still create clamp conduction or long-term fragility.
- Injection current may hide in abs max tables. A pin can “survive” VIN>VDD only if current stays below a specified limit.
- Power-off conditions are special. “5-V tolerant” may apply only when VDD=0 or only when VDD is present; the valid state must be verified.
C) Pass criteria template (copy/paste)
Likely cause (if failing): threshold margin is too small under real load/temperature, so dynamic crossing drifts into the sampling edge or noise flips states.
Quick check: read VIH(min)/VIL(max) of the receiver; read VOH(min)@IOH and VOL(max)@IOL of the driver; confirm the corner conditions match the system use case.
Fix direction (do not expand here): reduce required IOH/IOL, slow or condition edges, or route to Level Translation if margins cannot be guaranteed at corners.
Pass criteria: NMH ≥ X mV and NML ≥ X mV at the intended corner (X is project-specific).
Input Types Matter: CMOS vs TTL vs Schmitt vs “5V-Tolerant Input”
A “3.3-V interface” is not a single threshold. The input type defines how VIH/VIL behave, how ringing is interpreted, and which failure modes appear at speed, noise, and corner conditions.
A) Input type quick reference (meaning, best use, risk)
Best for: clean rails, short traces, controlled edges.
Risk: margin shrinks at corners; slow edges can miss the sampling window at higher speed.
Best for: mixed-voltage legacy logic, tolerant “high” recognition.
Risk: common-mode noise and ground bounce can create false highs; verify VIL(max) and noise environment.
Best for: slow edges, noisy environments, long traces/cables, debounce-like signals.
Risk: trip points and hysteresis can shift timing; verify propagation/latency impact and input leakage at corners.
Best for: mixed rails, hot-plug, signals that may be present while VDD is off.
Risk: tolerance is conditional (VDD state, mode, injection current limits). It does not automatically guarantee VIH/VIL compatibility.
Practical takeaway: Threshold math (H2-2) must use the correct input type. “5V tolerant” is primarily a fault/power-state attribute, not a different logic threshold.
B) How to identify the input type in a datasheet (fast)
- DC characteristics: VIH/VIL definitions and conditions.
- I/O description: Schmitt, hysteresis, fail-safe, Ioff language.
- Absolute max ratings: VIN range, clamp current (IIK/IOK), injection limits.
- Power sequencing notes: behavior when VDD=0 or brown-out.
- Schmitt / hysteresis: confirms dual trip points (VH+/VH−) or a hysteresis voltage.
- TTL-compatible: suggests lower VIH(min); still verify VIL(max) and noise margin.
- 5V tolerant / overvoltage tolerant: requires confirmation of VDD state and injection current limits.
- Fail-safe / Ioff: often indicates safe behavior with inputs active while the device is unpowered, but is pin- and mode-specific.
If a pin claims “5V tolerant” but there is no stated injection/clamp current limit or no stated behavior when VDD=0, treat the compatibility status as unknown until verified.
5-V Tolerance Deep Dive: Clamp, Injection Current, and Hidden Back-Powering
“5V-tolerant” is a fault/power-state claim. The real question is whether VIN>VDD creates clamp conduction or injection current that lifts rails, corrupts I/O states, or locks the bus.
A) Common mechanisms (classified by behavior, not by schematics)
Confirm: abs max VIN limits, clamp current (IIK/IOK), and explicit “VIN>VDD” handling language.
Confirm: “Ioff / fail-safe input” specs and the exact VDD state(s) where the claim holds.
Confirm: allowable overvoltage range, injection current limit, and whether the limit applies to transient or steady-state conditions.
Important boundary: The claim can be pin-specific and mode-specific. Always verify the valid VDD state (powered vs unpowered) and the permitted injection current.
B) Three red flags (treat as Unsafe until proven otherwise)
If the abs max table indicates VIN ≤ VDD + small margin and there is no stated injection/clamp current limit for VIN>VDD, overvoltage behavior is not controlled.
If “5V tolerant” is claimed but the valid power state is undefined, hot-plug and power-off drive can cause back-powering or partial power that breaks state machines.
Without an IIK/IOK (or injection current) limit, it is impossible to guarantee that a fault condition will not lift VDD rails or stress ESD structures.
C) Fast verification: prove (or disprove) back-powering risk
- Limit current first: apply VIN>VDD through a series resistor or a current-limited source to avoid uncontrolled stress.
- Measure rail lift: with the target device unpowered (VDD=0), monitor the VDD rail and nearby rails for unintended rise.
- Estimate injection current: measure current directly (probe) or infer from the series resistor voltage drop.
- Watch system symptoms: partial power, unexpected boot, stuck bus lines, or altered I/O defaults are direct evidence of back-power paths.
Pass criteria: no unintended rail rise beyond X, and injection/clamp current stays below X (project-specific X).
Open-Drain vs Push-Pull: What Changes Electrically and Why It Breaks Systems
Driver type decides who “owns” the high level, how edges form, and whether multiple devices can safely share a line. Many lockups and intermittent failures are contention or power-state problems, not protocol issues.
A) What each driver can do (and what it cannot)
- High level: created by the pull-up rail (VIH depends on pull-up voltage).
- Rising edge: RC-shaped (speed depends on Rpullup × Cbus).
- Sharing lines: inherently safe for multi-drop (one device pulls low at a time).
- Must add: pull-up network and edge control (series-R or segmenting when needed).
- Cannot assume: fast rise at high speed without RC budget.
- High level: driven by VOH under IOH (verify VOH(min) conditions).
- Edges: fast transitions (better timing margin, higher SI/EMI risk).
- Sharing lines: unsafe unless strict ownership is enforced (contention risk).
- Must add: contention avoidance rules, and SI damping/termination when needed.
- Cannot assume: safe behavior when a peer is unpowered (back-power/injection risk).
Engineering rule: If more than one device can drive the same line at the same time, treat push-pull as unsafe unless contention current is bounded and power-state behavior is validated.
B) Conflict scenarios that commonly break systems
Multiple devices can legally or accidentally drive the same node. Push-pull can create direct high-vs-low contention; open-drain is naturally wired-safe but becomes RC-limited at higher speed.
During insertion, VIN can appear before VDD (or vice versa). A push-pull driver can back-power an unpowered peer through clamp/injection paths (see H2-4 risk model).
A powered master driving a line into an unpowered device can lift rails, corrupt default I/O states, or lock bus state machines. Validate Ioff/fail-safe behavior and injection current limits.
Power-up defaults can create “instant contention” if both sides default to output-drive. The worst cases are intermittent (depends on timing) and can appear as random protocol errors.
C) Pass criteria template (contention, waveform, and power-state)
- Contention current: Icontention < X (project-specific X) for any overlap condition.
- Thermal impact: ΔT < X during repeated contention stress tests.
- Waveform bounds: overshoot/undershoot stays within abs max limits under worst-case edge rate and loading.
- Power-state safety: unpowered endpoints do not exhibit rail lift beyond X and do not force stuck-high/stuck-low lines.
Scope guard: specific damping, termination, and protection selections belong to the Port Protection / SI pages; this section defines the acceptance criteria and the failure signatures.
Timing Meets Voltage: Why “It Works at 100 kHz but Fails at 1 MHz”
Static VIH/VIL math is not enough at speed. Reliability depends on when the waveform crosses the threshold relative to the sampling window—and whether ringing creates multiple crossings.
A) Typical failure chain (dynamic threshold problem)
When the rising edge is RC-limited (or driver is weak), the signal may not reach VIH before the receiver samples. The same link can look stable at low rate and fail at higher rate because the sampling window shrinks.
A fast driver can create reflection and ringing. If the waveform crosses VIH/VIL more than once near the sampling instant, the receiver may interpret different values across cycles.
B) Quick checks (three measurements that settle most debates)
- Measure crossing time: how long it takes to reach VIH from the last stable low.
- Locate the sampling moment: identify when the receiver decides (sampling point/window).
- Align thresholds: verify instrument decode thresholds are not masking (or inventing) errors.
Instrument pitfall: A logic analyzer threshold can differ from the real receiver threshold. Use the receiver VIH/VIL as the reference, not the decoder default.
C) Fix routes (directional; detailed selections live on sibling pages)
Reduce effective RC (pull-up strategy, segmentation, buffering) so the threshold is crossed with margin before the sampling point.
Dampen the edge (series-R, return-path cleanup, termination approach) so the waveform crosses thresholds once and then stays stable.
Component-level protection, translator selection, and detailed termination values belong to the Port Protection / Level Translation / SI pages. This section defines the failure signatures and the measurement-first workflow.
Power Sequencing & Hot-Plug: The Real-World Compatibility Killer
Voltage compatibility must include power states. Many field failures come from partial-power paths: VIN arrives before VDD, ground disconnects first, or a rail drops while I/O keeps toggling.
A) Three dangerous sequences that cause hidden failures
External signals drive an unpowered pin. Clamp/injection paths can lift the local rail (ghost powering), alter default I/O states, and lock state machines.
The reference shifts or floats. Return paths become uncontrolled, producing ground bounce and unexpected current loops that can violate abs max even when steady-state levels look correct.
One rail drops while I/O keeps toggling. “Powered” logic may drive into “unpowered” pads, creating rail lift, contention, or stuck-high/stuck-low lines.
B) Principles to minimize risk (directional only)
- Order matters: prefer “ground first” and “power before signal” where hot-plug exists.
- Limit current first: ensure any VIN>VDD event is current-bounded (series resistance / controlled source in validation).
- Avoid driving unpowered peers: confirm Ioff/fail-safe behavior or add isolation/translation boundaries.
- Design for recoverability: a bad insertion should not leave a bus permanently stuck.
- Treat partial power as a normal mode: verify “brown-out + active I/O” behavior explicitly.
- Use abs max as a gate: overshoot and injection must stay within specified limits in worst-case insertion waveforms.
Scope guard: Detailed protection component selection lives on the Port Protection pages. This section defines sequencing risks and verification workflow.
C) Field troubleshooting: measure rail lift and clamp/injection current
- Rail-lift check: with the endpoint unpowered, drive a known input level through a current limit and observe VDD rise (if any).
- Clamp/injection check: measure input current (or series-R drop) when VIN>VDD to detect clamp conduction.
- Symptom correlation: confirm whether rail lift coincides with stuck lines, unexpected boot, or thermal rise.
- Pass criteria template: VDD lift < X, injection < X, and the interface recovers without persistent stuck states (project-specific X).
Bus-Specific Rules: I²C vs SPI vs UART Voltage Compatibility Checklist
The same “voltage compatible” claim means different checks across buses. Use these per-bus lists to catch the most common field failures without turning this page into a protocol tutorial.
I²C (open-drain + pull-up rail defines VIH)
- Confirm pull-up rail: SDA/SCL pull to a voltage that meets VIH(min) for every node.
- Check unpowered tolerance consistency: any node that clamps VIN>VDD can back-power the bus.
- Verify injection limits: abs max and clamp current specs exist for VIN>VDD cases.
- Validate edge budget: RC rise still crosses VIH early enough at target speed.
- Watch stuck-line signatures: partial-power endpoints can hold SDA/SCL in illegal states.
- Hot-plug assumption: if cabling/modules exist, run the rail-lift check (H2-7 workflow).
SPI (push-pull + edge integrity + MISO tri-state)
- Use VOH/VOL under load: verify VOH(min)@IOH and VOL(max)@IOL against receiver VIH/VIL.
- Identify input type: CMOS/TTL/Schmitt affects real thresholds and noise sensitivity.
- Check overshoot/ringing: fast edges can create multiple crossings and abs max violations.
- Validate MISO high-Z: unselected slaves must tri-state; unpowered slaves must not clamp.
- Confirm power-state mixing: CS/SCLK/MOSI into an unpowered slave must not rail-lift.
- Ground reference sanity: board-to-board ground offset can shift effective logic levels.
UART (async sampling + noise + ground offset; PHY boundary matters)
- Threshold vs noise margin: ensure VIH/VIL margins remain under ground bounce and EMI.
- Dynamic crossing stability: avoid late crossing and multi-crossing near sampling points.
- Ground offset awareness: long cables can shift reference and distort “effective” levels.
- Unpowered endpoint behavior: check clamp/injection to prevent rail lift or stuck levels.
- PHY migration rule: if RS-232/RS-485 is used, compatibility moves to the transceiver specs (link to UART PHY page).
- Transient tolerance: verify abs max and clamp current behavior for port events.
Measurement & Debug: How to Prove Compatibility (Not Guess)
Compatibility is proven by a repeatable evidence chain: waveform integrity → threshold-aware decode → injection/rail-lift checks → correlation to error counters and state-machine behavior.
A) Measurement checklist (waveform • current • state)
- Abs max crossings: overshoot/undershoot during steady-state and insertion/power transitions.
- Threshold-zone ringing: watch for multi-crossing near VIH/VIL.
- Power-state waveforms: capture ON/OFF/partial-on transitions, not only “already stable” frames.
- Input threshold: align analyzer threshold with the receiver’s VIH/VIL intent.
- Sampling & triggers: ensure rate and trigger capture short glitches and power-up frames.
- Decode sanity: confirm the tool’s mode assumptions do not create false NAK/bit-slip events.
- Injection current: use a current probe or series-R drop when VIN>VDD conditions exist.
- Rail lift: observe VDD rise when the endpoint is unpowered.
- Boundary retest: repeat at temperature corners if the interface is margin-limited.
- Timestamp errors: correlate NAK/CRC/framing with waveform/crossing events.
- Recovery behavior: confirm the system returns to a valid state after faults.
- Split endpoints: isolate which device and pin class triggers the issue (data vs clock vs enable).
B) Five common “instrument artifacts” that create false conclusions
The analyzer’s logic threshold differs from the receiver’s VIH/VIL, so “NAK/bit-slip” appears even when the real endpoint is fine (or disappears when the endpoint is not fine).
Short ringing bursts near VIH/VIL are missed or aliased, producing misleading “clean” decodes while the receiver actually sees multi-crossings.
Long ground leads or poor return referencing exaggerate ringing and overshoot. Always interpret “abs max crossings” with a measurement setup that preserves the real return path.
Capturing only stable runtime hides the failure mechanism. Many compatibility breaks occur during plug-in, reset, rail ramp, or partial-power events.
Mode/polarity framing assumptions in tools can label transitions as protocol failures. Validate by cross-checking raw edges against expected thresholds and state transitions.
C) Pass criteria (proof template)
No overshoot/undershoot crosses abs max limits during steady operation and during power/plug transitions.
VIH/VIL crossings occur with stable margin (≥ X) before sampling windows; ringing does not cause repeated crossings near thresholds.
When VIN>VDD cases exist, injection/clamp current stays below X and unpowered rails do not lift above X (project-specific X).
Scope guard: This section proves compatibility by measurement; component selection details remain on protection/translation pages.
Engineering Checklist (Bring-up → Production) ✅
Use three gates to prevent “works on one bench” failures: Bring-up gate for first link, Debug gate for shortest root-cause path, and Production gate for fixture/ATE consistency and drift control.
Bring-up gate (first link)
- Action: confirm receiver input type (CMOS/TTL/Schmitt). Decision: if unknown, treat as worst-case thresholds and measure.
- Action: verify VIH/VIL and VOH/VOL under stated IOH/IOL. Decision: fail if margins are not documented (X placeholder).
- Action: test power sequences (VIN-first, VDD-first, partial-on). Decision: fail if rail lift occurs.
- Action: reserve a current-limit / series-R validation point. Decision: required when VIN>VDD is possible.
- Action: capture scope traces during reset/plug events. Decision: fail if abs max is crossed.
- Action: validate unpowered tolerance (Ioff/fail-safe) by measurement. Decision: fail if clamp current is uncontrolled.
- Action: check “stuck-line” recovery behavior. Decision: pass only if the interface returns to a valid idle state.
- Action: record the baseline thresholds/rails/fixtures. Decision: required before performance tuning.
Debug gate (shortest path)
- Action: gate on abs max first. Decision: any crossing ⇒ Unsafe (stop).
- Action: verify analyzer threshold and sampling. Decision: if tool mismatch exists, re-baseline before blaming the bus.
- Action: measure injection/rail lift under VIN>VDD or partial-power. Decision: rail lift ⇒ isolation/translation boundary required.
- Action: check threshold-zone ringing / multi-crossing. Decision: repeated crossings ⇒ edge control / return-path review.
- Action: correlate errors to waveform timestamps. Decision: if correlation exists, classify the root cause (threshold vs injection vs edge vs ground).
- Action: validate recovery path (reset/watchdog). Decision: pass only if stuck states clear deterministically.
- Action: separate endpoints and pins (data vs clock vs enable). Decision: single-pin issues often indicate local clamp/return problems.
- Action: re-run at a corner condition (temp/voltage/fixture). Decision: corner-only failures indicate margin insufficiency.
Production gate (fixture/ATE consistency + drift control)
- Action: standardize test thresholds (VIH/VIL) across stations. Decision: fail if fixtures use “default” logic thresholds.
- Action: lock fixture versions and cable sets. Decision: any change triggers a re-baseline capture.
- Action: log rail conditions and temperature for every failure. Decision: missing context ⇒ non-actionable data.
- Action: define drift monitors (edge time, rail lift signature, error counters). Decision: trend beyond X ⇒ containment.
- Action: run corner retest sampling. Decision: if only corners fail, classify as margin issue (not random).
- Action: enforce “Unsafe” rules in production. Decision: abs max crossing or rail lift ⇒ stop-ship until fixed.
- Action: keep a golden unit + golden trace set. Decision: use as reference for station correlation.
- Action: document pass/fail gates per product. Decision: X values are project-specific and must be explicit.
Applications: Where Voltage Compatibility Actually Breaks Systems
Only high-risk buckets are listed here. Each bucket includes (1) the risk trigger, (2) the failure signature, and (3) where to prove it inside this page. Example part numbers are included as reference only.
A) Use-case buckets that require strict compatibility proof
- Risk trigger: different input types and load-dependent VOH/VOL reduce real noise margin.
- Failure signature: “works on one board” but fails across lots/temperature; intermittent NAK/bit errors.
- Prove here: H2-2 (threshold+NM), H2-3 (input type), H2-6 (timing×voltage), H2-9 (measure).
- Example parts: PCA9306 (I²C level translator), PCA9517A (I²C level translating repeater), TCA9548A (I²C switch/mux), TXS0108E (wide-IO translator).
Verification note: treat “same nominal voltage” as insufficient until VIH/VIL + dynamic crossings are proven.
- Risk trigger: VIN>VDD exposure; “5V tolerant” is about overvoltage structure, not logic thresholds.
- Failure signature: ghost-powering, stuck bus, MCU partial-boot, random lockups after plug/unplug.
- Prove here: H2-4 (injection/back-power), H2-7 (power/hot-plug), H2-9 (current+rail lift).
- Example parts: PCA9306 (I²C translation), TXS0108E (mixed push-pull/open-drain translation), ISO1540 (isolated I²C), TPD1E10B06 (port ESD protection).
Boundary rule: if unpowered tolerance (Ioff / VIN when VDD=0) is undefined, treat as “must-measure” before release.
- Risk trigger: insertion sequence and transient overshoot; ground first/last effects; partial-rail ramp.
- Failure signature: “passes lab ESD once, then becomes fragile”; failures appear only after repeated insertion.
- Prove here: H2-7 (power-state matrix), H2-9 (capture transients), H2-10 (bring-up gate).
- Example parts: TPD1E10B06 (ESD diode), TCA9548A (I²C fanout/address conflicts), MAX3232 (UART↔RS-232), SN65HVD3082E (UART↔RS-485).
Practical guard: measurements must include plug and power transitions, not only steady-state frames.
- Risk trigger: IO clamp/injection creates rail lift when one side sleeps or browns out.
- Failure signature: stuck lines after sleep; unexpected current draw; wake failures and “half-on” states.
- Prove here: H2-4 (injection spec), H2-7 (partial-on), H2-9 (rail lift), H2-10 (production gate).
- Example parts: ISO1540 (isolated I²C to break back-power paths), PCA9306 (EN-controlled translation), PCA9517A (segmented I²C buffering), TPD1E10B06 (I/O protection).
Release rule: unpowered behavior must be proven at system level with measured rail-lift and clamp current.
Example part numbers: verify package/suffix/availability/voltage corner cases. Selection must follow the decision logic in H2-12 and the proof steps in H2-9/H2-10.
B) Risk taxonomy (what actually breaks “compatibility”)
VIH/VIL vs VOH/VOL under real load and temperature (noise margin is the gate).
VIN>VDD or unpowered endpoints cause clamp current and rail lift (hidden system boot failures).
Push-pull conflicts on shared nets and tri-state ambiguity (especially multi-slave lines).
Slow edges or ringing shift threshold crossing relative to sampling windows (speed-up often breaks).
C) Scope guard (keep boundaries clean)
This section maps use-cases to risk types and to the proof chapters in this page. Detailed protection networks, isolation power design, and dedicated translation topologies belong to their respective subpages.
IC Selection Logic: Gates, Red Flags, and a Decision Tree
Selection must be driven by measured-safe power states and datasheet gates. Example part numbers are provided to anchor each branch; final choices require suffix/package and corner verification.
A) Input-side gates (receiver behavior)
- Gate: Is VIN>VDD possible (5V present anywhere, cable hot-plug, back-power paths)? If yes: require explicit overvoltage/injection limits (H2-4/H2-9).
- Gate: Is unpowered input tolerance defined (Ioff / “VIN when VDD=0”)? If no: treat as red flag; prove by rail-lift test (H2-9).
- Gate: Input type identified (CMOS/TTL/Schmitt/overvoltage tolerant). If unknown: measure threshold crossings at the receiver pin.
- Verify: input leakage across corners; leakage can defeat pull-ups and slow edges in open-drain networks.
Example anchors: VIN translation (PCA9306), wide-IO translation (TXS0108E), isolated I²C (ISO1540).
B) Output-side gates (driver behavior)
- Gate: Driver type matches topology (open-drain vs push-pull). Shared nets + push-pull requires contention control (H2-5).
- Gate: VOH/VOL are checked under stated IOH/IOL conditions (load matters). Avoid “typical-only” assumptions (H2-2).
- Gate: Tri-state behavior is explicit for multi-slave lines (SPI MISO, shared UART lines). Undefined tri-state is a system risk.
- Verify: edge rate vs ringing near thresholds; ensure crossing happens before sampling windows (H2-6).
Example anchors: I²C buffer/segment (PCA9517A), channel isolation/address resolution (TCA9548A).
C) Protection & reliability gates (must-not-break rules)
- Red flag: no explicit injection/clamp current guidance for VIN>VDD scenarios → must-measure (H2-9) or isolate (ISO1540).
- Red flag: powered-off behavior missing → treat as unsafe until rail-lift and clamp current are proven.
- Gate: abs max integrity must hold during plug/power transitions (H2-7/H2-9).
- Gate: port protection chosen for the interface (capacitance vs edge rate trade). Example: TPD1E10B06 as a low-voltage I/O ESD anchor.
- PHY boundary: long cables and ground shift move the problem to the PHY. Example anchors: MAX3232 (RS-232), SN65HVD3082E (RS-485).
Outcome rule: If safety gates are not explicitly supported by the datasheet, the decision becomes “must-validate by measurement” before productization.
D) Decision outcomes (with example part-number anchors)
Use when thresholds and power states are proven safe. Common add-on: port ESD protection.
Example: TPD1E10B06 (ESD diode).
Use when voltage domains differ or when bus capacitance/fanout needs segmentation.
Examples: PCA9306 (I²C translator), PCA9517A (I²C repeater), TCA9548A (I²C switch/mux), TXS0108E (wide-IO translator).
Use when partial-power, ground shift, or safety isolation is required. Isolation changes delay budgets and must be validated.
Example: ISO1540 (isolated I²C).
For long cables and large ground shifts, compatibility moves from logic-level UART to the physical transceiver.
Examples: MAX3232 (RS-232), SN65HVD3082E (RS-485).
Recommended topics you might also need
Request a Quote
FAQs: Thresholds, 5V Tolerance, Contention, Power States, and Proof
Each answer uses a fixed 4-line format and keeps a strict boundary: thresholds, 5V tolerance/injection, driver contention, power sequencing, and measurement criteria.
