I²C Pull-Up Sizing: Calculate Rp from Bus Capacitance
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This page provides a step-by-step method to estimate Cb, compute Rpmin…Rpmax, validate it with clean measurements, and decide when to upgrade with buffering, isolation, or edge-acceleration when passive pull-ups cannot meet both timing and robustness.
H2-1 · Definition: What “Pull-Up Sizing” Actually Controls
Pull-up sizing is not guesswork. It is the intersection of three constraints: rise-time compliance (RC edge budget), low-level sink margin (VOL/IOL limits), and pull-up power (low-level current over duty-cycle). The “right” Rp is the resistor range that satisfies all three at worst-case bus capacitance.
Rp and total bus capacitance (Cb) set how fast SDA/SCL cross the receiver threshold. Too large → slow edges → sampled “1” arrives late.
Rp that is too small increases low-level current. If any device cannot sink it, VOL rises and “0” becomes noisy or marginal under load.
Low level burns roughly VDD²/Rp while the line is held low. Smaller Rp can quietly become a battery and thermal budget problem.
Overly strong pull-ups can sharpen edges, worsen ringing/overshoot, and cause multiple threshold crossings that confuse sampling.
- Why it points here: the edge reaches the “valid high” threshold too late at worst-case Cb.
- Fast check: run the same transaction at a lower bus speed; if it stabilizes, rise-time margin is suspect.
- Likely direction: Rp too large, Cb underestimated, or “extra capacitance” added by protection/connector/fixture.
- Why it points here: rise-time is being measured with the wrong definition, or ringing causes threshold re-crossing.
- Fast check: verify the rise-time metric (30–70 vs 10–90) and re-measure with a short ground spring.
- Likely direction: measurement definition mismatch or overly strong edges creating threshold jitter.
- Why it points here: low-level sink current increased beyond a device’s capability, lifting VOL and stressing the budget.
- Fast check: measure steady-state VOL while a device holds the line low; compare against the device’s sink rating.
- Likely direction: Rp too small, multiple pull-ups effectively in parallel, or low-VDD/temperature corner reducing margin.
H2-2 · Compliance Targets: Which Rise-Time Definition Are You Budgeting?
Rise-time budgeting must use the same definition in both calculation and measurement. A common failure mode is “passing” the wrong metric (for example, measuring 10–90% while the compliance limit is defined for 30–70%). This section locks down the measurement definition and the target fields that must be captured before any RC math is trusted.
- tR(30–70): time from 0.3·VDD to 0.7·VDD (often used in I²C compliance definitions).
- tR(10–90): time from 0.1·VDD to 0.9·VDD (a frequent oscilloscope default).
- Receiver-referenced: time to cross a receiver threshold (useful for debugging when VIH/Vth differs from ideal percentages).
- tR limit: use the I²C specification limit for the selected mode (or a stricter device limit).
- VDD used in measurement: record rail min/nom/max (percent-based metrics shift with VDD).
- Threshold note: if a receiver has Schmitt/filtering, treat it as an additional timing boundary.
- Margin policy: reserve headroom (measurement noise, corner capacitance, temperature, fixtures).
- Scope settings: define the same percentage points used in the RC budget (avoid default traps).
- Pass criteria: tR meets the chosen definition and stays stable across repeated captures.
- Cb sensitivity: small capacitance changes can break compliance; measure in the real assembly.
- Probe discipline: a long ground lead can fabricate ringing or hide it (wrong conclusions either way).
- Device notes: some parts impose stricter rise-time or filtering constraints than the bus spec.
- Do not assume: use the exact timing limits for the implemented HS signaling segment.
- Measurement focus: confirm the definition and the receiver threshold behavior used by endpoints.
- Pass criteria: compliance at worst-case VDD/Cb, not just on an unloaded bench.
A 10–90% rise-time number cannot be compared to a 30–70% limit. Configure the measurement points explicitly or convert with a consistent model.
Protocol decoders often use fixed thresholds and sampling assumptions. Use the scope for compliance timing; use the analyzer for framing and statistics.
Long probe grounds and improper bandwidth limits can distort the edge. A “clean” trace may be filtered; a “noisy” trace may be self-inflicted.
H2-3 · First-Principles RC Model: Derive Rise-Time from Rp·Cb
The pull-up edge on an open-drain bus is a first-order RC charge. With the bus released, the node voltage rises toward VDD with time constant τ = Rp·Cb. Rise-time is therefore a direct proxy for Rp·Cb, but only when the same rise-time definition is used in both calculation and measurement.
Node voltage: V(t) = VDD · (1 − e−t / (Rp·Cb))
This assumes the bus is dominated by Rp charging an effective capacitance Cb. Ringing/overshoot may exist in real layouts, but the compliance rise-time budget is still anchored to the threshold-crossing time captured by this RC form.
Derived from Δt = Rp·Cb · ln(0.7/0.3). Use when the compliance limit is defined in 30–70% terms.
Derived from Δt = Rp·Cb · ln(0.9/0.1). Use only when measurement and the limit use the same 10–90% definition.
- Bus mode: Standard / Fast / Fast+ / Hs (use the mode actually deployed).
- tR limit: the compliance rise-time upper bound for that mode (or a stricter system target).
- Definition: 30–70% or 10–90% (must match the measurement setup).
- Cb
_worst: worst-case effective bus capacitance from the capacitance budget.
Units check: tR in seconds, Cb in farads → Rp in ohms. Convert carefully (µs↔s, pF↔F). A single unit slip can move Rp by 10×.
- Why margin exists: Cb varies with population, layout options, protection parts, fixtures, and temperature.
- How to apply: target a practical rise-time below the limit (reserve headroom for variance and measurement error).
- Output: a recommended “design Rp upper bound” that is smaller than the raw Rpmax calculation.
The computed Rp window “looks reasonable” but fails on the real assembly. A mismatch between measurement definition and limit is a top cause.
The bench setup passes, but the populated product fails. Extra protection, connectors, or channels quietly increase Cb and consume timing margin.
Multiple pull-ups in parallel reduce effective Rp. That can increase power and stress sink margin even when rise-time looks “better”.
H2-4 · Capacitance Budget: How to Estimate Cb Without Lying to Yourself
The RC formula is simple; the hard part is Cb. Effective bus capacitance is the sum of endpoint pins, protection parts, routing parasitics, connectors/cabling, switching elements, and measurement loading. A reliable pull-up design uses a traceable budget plus a worst-case configuration, then validates the estimate by measurement.
Input pin capacitance accumulates with device count. “One more slave” often matters more than expected at Fast+/Hs.
Low-cap arrays can still dominate the budget when placed on every connector line. This is a top source of “bench vs product” mismatch.
Trace length, plane coupling, and via fields add distributed capacitance. Long stubs and fanout routing quietly grow Cb.
Connector population and cable versions shift capacitance. Worst-case must match the longest/most-loaded field configuration.
Segmentation helps, but each inserted element has input capacitance and leakage. Budget both “on” channels and disabled stubs.
Probes and fixtures can add capacitance and change the observed edge. Record the measurement setup as part of the “Cb estimate”.
“Worst-case” is a configuration choice: maximum device population, longest routing/harness variant, all protection parts populated, and any test fixture that will be present in validation. Compute Cb for that specific configuration.
- Pins: extract Cpin from each endpoint datasheet and multiply by device count.
- Protection: add ESD/TVS capacitance per line and per connector population.
- Routing: estimate trace/via capacitance using length and stack assumptions (keep the method consistent).
- Inserted elements: include mux/switch/isolator input capacitance and any disabled stubs that remain connected.
Add margin for part tolerances, population options, and measurement loading. Record assumptions (device count, cable variant, which ESD array, probe type). Without this, future revisions will silently invalidate the Rp calculation.
- 1) Confirm effective Rp: include any parallel pull-ups that are enabled in the system configuration.
- 2) Measure tR with the locked definition: 30–70 or 10–90, with a controlled probe setup.
- 3) Back-calc: Cb ≈ tR / (k · Rp), using k = 0.8473 (30–70) or 2.197 (10–90).
The back-calculated Cb is an effective capacitance that includes fixtures and probes. Its value is most useful as a cross-check: if it is much larger than the budget, a missing contributor (often protection or harness) is likely.
H2-3 · First-Principles RC Model: Derive Rise-Time from Rp·Cb
The pull-up edge on an open-drain bus is a first-order RC charge. With the bus released, the node voltage rises toward VDD with time constant τ = Rp·Cb. Rise-time is therefore a direct proxy for Rp·Cb, but only when the same rise-time definition is used in both calculation and measurement.
Node voltage: V(t) = VDD · (1 − e−t / (Rp·Cb))
This assumes the bus is dominated by Rp charging an effective capacitance Cb. Ringing/overshoot may exist in real layouts, but the compliance rise-time budget is still anchored to the threshold-crossing time captured by this RC form.
Derived from Δt = Rp·Cb · ln(0.7/0.3). Use when the compliance limit is defined in 30–70% terms.
Derived from Δt = Rp·Cb · ln(0.9/0.1). Use only when measurement and the limit use the same 10–90% definition.
- Bus mode: Standard / Fast / Fast+ / Hs (use the mode actually deployed).
- tR limit: the compliance rise-time upper bound for that mode (or a stricter system target).
- Definition: 30–70% or 10–90% (must match the measurement setup).
- Cb
_worst: worst-case effective bus capacitance from the capacitance budget.
Units check: tR in seconds, Cb in farads → Rp in ohms. Convert carefully (µs↔s, pF↔F). A single unit slip can move Rp by 10×.
- Why margin exists: Cb varies with population, layout options, protection parts, fixtures, and temperature.
- How to apply: target a practical rise-time below the limit (reserve headroom for variance and measurement error).
- Output: a recommended “design Rp upper bound” that is smaller than the raw Rpmax calculation.
The computed Rp window “looks reasonable” but fails on the real assembly. A mismatch between measurement definition and limit is a top cause.
The bench setup passes, but the populated product fails. Extra protection, connectors, or channels quietly increase Cb and consume timing margin.
Multiple pull-ups in parallel reduce effective Rp. That can increase power and stress sink margin even when rise-time looks “better”.
H2-4 · Capacitance Budget: How to Estimate Cb Without Lying to Yourself
The RC formula is simple; the hard part is Cb. Effective bus capacitance is the sum of endpoint pins, protection parts, routing parasitics, connectors/cabling, switching elements, and measurement loading. A reliable pull-up design uses a traceable budget plus a worst-case configuration, then validates the estimate by measurement.
Input pin capacitance accumulates with device count. “One more slave” often matters more than expected at Fast+/Hs.
Low-cap arrays can still dominate the budget when placed on every connector line. This is a top source of “bench vs product” mismatch.
Trace length, plane coupling, and via fields add distributed capacitance. Long stubs and fanout routing quietly grow Cb.
Connector population and cable versions shift capacitance. Worst-case must match the longest/most-loaded field configuration.
Segmentation helps, but each inserted element has input capacitance and leakage. Budget both “on” channels and disabled stubs.
Probes and fixtures can add capacitance and change the observed edge. Record the measurement setup as part of the “Cb estimate”.
“Worst-case” is a configuration choice: maximum device population, longest routing/harness variant, all protection parts populated, and any test fixture that will be present in validation. Compute Cb for that specific configuration.
- Pins: extract Cpin from each endpoint datasheet and multiply by device count.
- Protection: add ESD/TVS capacitance per line and per connector population.
- Routing: estimate trace/via capacitance using length and stack assumptions (keep the method consistent).
- Inserted elements: include mux/switch/isolator input capacitance and any disabled stubs that remain connected.
Add margin for part tolerances, population options, and measurement loading. Record assumptions (device count, cable variant, which ESD array, probe type). Without this, future revisions will silently invalidate the Rp calculation.
- 1) Confirm effective Rp: include any parallel pull-ups that are enabled in the system configuration.
- 2) Measure tR with the locked definition: 30–70 or 10–90, with a controlled probe setup.
- 3) Back-calc: Cb ≈ tR / (k · Rp), using k = 0.8473 (30–70) or 2.197 (10–90).
The back-calculated Cb is an effective capacitance that includes fixtures and probes. Its value is most useful as a cross-check: if it is much larger than the budget, a missing contributor (often protection or harness) is likely.
H2-5 · Compute the Safe Resistor Window: Rpmax vs Rpmin (clamp method)
Pull-up selection is a bounded problem. The upper bound comes from rise-time compliance (too large → slow edges), while the lower bound comes from low-level sink capability and VOL targets (too small → excessive sink current and elevated VOL). The safe design region is the intersection: [Rpmin, Rpmax].
- VDD (pull-up rail): the actual pull-up voltage domain used on SDA/SCL.
- Rise-time definition: 30–70% or 10–90% (must match calculation and scope).
- tRlimit: rise-time upper bound for the deployed bus mode (or a stricter system target).
- Cb
_worst: worst-case effective bus capacitance for the worst-case configuration.
- VOL_target: the low-level voltage target (use the stricter of spec vs device requirements).
- IOL_weakest: the minimum guaranteed sink current of the weakest device that can pull the line low.
- Parallel pull-ups: account for any multiple resistors enabled at the same time (effective Rp changes).
- Units: µs↔s, pF↔F, kΩ↔Ω (unit slips commonly cause 10× errors).
Use the same rise-time definition as the compliance limit and measurement setup. Then compute:
Rpmax is only meaningful when Cb
When the line is held low, the pull-up resistor sources current into the pulling device. To keep the low level below the target, the resistor must not demand more current than the weakest pull-down can guarantee:
IOL_weakest should be the minimum guaranteed sink capability of the weakest device that can pull the line low (master, any slave, or inserted elements). If SDA and SCL have different pull-down paths, compute Rpmin per line.
Smaller Rp increases low-level current and pushes VOL upward when the pull-down device saturates. A design that meets rise-time but violates VOL will produce “0-level instability” and temperature/lot sensitivity.
Multiple pull-ups in parallel reduce effective Rp and can violate Rpmin even when each resistor value looks safe by itself.
A feasible passive pull-up window exists. Choose a value inside the window while reserving margin for worst-case capacitance and measurement variance.
Passive pull-up cannot satisfy both rise-time and VOL/sink constraints. Typical next moves include: lower speed, segmentation/buffering, or active pull-up/edge accelerator. The detailed selection is routed to later sections.
pF ↔ nF is a 1000× change. Always convert to farads before computing Rp. “400 pF” is 4e−10 F, not 4e−7 F.
µs ↔ s is a 1e6× change. If a computed Rp seems off by orders of magnitude, re-check time units first.
1 / Rp_effective = Σ(1/Rp_i). Two equal pull-ups halve the resistance and double low-level current.
H2-6 · Power & Thermal: When Smaller Rp Quietly Becomes a Battery Problem
A smaller pull-up resistor improves edges, but it also increases low-level current whenever the bus is held low. In battery-powered or always-on systems, the dominant cost is often the average low-level power, which scales with duty cycle and with the effective Rp after any parallel pull-ups are combined.
This is the instantaneous dissipation in Rp while the bus is low. It is not the average unless the line is low nearly all the time.
D_low is the fraction of time the line is low (bus activity + waveform shape + any “stuck-low” conditions). Underestimating D_low is a common battery failure mode.
Multiple boards, multiple ports, or multiple “enabled by default” resistors often create an effective pull-up much smaller than expected:
Rp_effective ↓ increases both P_low and P_avg, and also tightens the Rp_min constraint from VOL/IOL. Always compute power using Rp_effective, not a single resistor value.
- VDD: pull-up rail voltage.
- Rp_effective: after combining parallel pull-ups.
- D_low: low-level duty cycle (use worst-case bus activity estimate).
- P_low: VDD² / Rp_effective
- P_avg: D_low · VDD² / Rp_effective
- Stuck-low check: evaluate D_low = 1 as a reliability guardrail.
Gate pull-ups by mode or activity so low-level power is not paid during long idle periods.
Use event-triggered pull-up acceleration to improve rise-time without paying continuous DC current.
Reduce Cb per segment so a larger Rp can still meet rise-time, improving power and sink margin simultaneously.
H2-7 · Edge Integrity & EMC: Ringing, Overshoot, and Why “Stronger Pull-Up” Can Hurt
A smaller pull-up resistor speeds up the edge, but faster edges excite parasitics (return-path inductance and distributed capacitance). The result can be overshoot, ringing, and multiple threshold crossings, which degrade robustness and can worsen EMI.
- Use a short ground spring (or coax reference) and compare against a long probe ground lead.
- Measure at two points (near source and near far endpoint) to separate local ringing from branch-driven ringing.
- Count threshold crossings around Vth/VIH; more than one crossing indicates chatter risk.
- Increase Rp moderately to reduce edge aggressiveness (verify rise-time still meets the selected definition).
- Add a small series resistor near the main driver/branch entrance to provide damping.
- Avoid placing the effective pull-up at a point that strongly excites a long stub; prefer topology-aware placement.
- Disable scope bandwidth limiting and excessive averaging that can hide ringing.
- Align the measurement definition (30–70 vs 10–90) with the compliance target to avoid “wrong-window” decisions.
- Check whether the probe itself is loading the node (capacitance and ground inductance).
- Do not “solve” ringing with stronger pull-up; prioritize damping (series-R) and topology-aware pull-up placement.
- Re-check the effective Rp when multiple pull-ups can be enabled in parallel.
- Zoom around the input threshold and count crossings; multiple crossings indicate a chatter mechanism.
- A/B test: increase Rp slightly or add small series-R; immediate improvement points to edge-induced chatter.
- Confirm that the reference point (ground/return) is stable during transitions to exclude measurement artifacts.
- Use “slower-but-clean” edges: Rp increase + damping resistor to force a single clean threshold crossing.
- Reduce stub excitation by avoiding star-like branches for critical nodes (route to topology guidance if needed).
- Probe ground inductance: long ground leads often inject ringing and exaggerate overshoot.
- Bandwidth limiting: aggressive filtering can make edges look compliant while threshold chatter remains.
- Trigger definition mismatch: wrong rise-time definition leads to wrong Rp decisions.
H2-8 · Multi-Voltage, Level Shifting, Isolation: Pull-Up to Which Rail?
In multi-voltage and isolated systems, pull-ups are not a single “global” choice. The pull-up rail determines VIH/VIL margin and can create leakage paths or ghost-powering. Level shifting and isolation can also change the effective Rp, threshold behavior, and edge shaping—so Rp calculations must follow the actual structure.
Pull-ups tie to the shared VDD and the bus behaves as a single open-drain domain.
- Parallel pull-ups (effective Rp shrinks).
- Protection capacitance (Cb grows) and edge-induced ringing (route to edge/EMC checks).
Recompute the resistor window using worst-case Cb and the correct rise-time definition; verify edge integrity if EMI/false edges appear.
A low-voltage controller interfaces with higher-voltage endpoints (or vice versa) and requires a structure that preserves open-drain behavior.
- Open-drain semantics must remain intact; wrong structures can create contention or false edges.
- Pull-up rail choice can create leakage or ghost-powering into an unpowered domain.
- Inserted elements add capacitance and shape the edge; recompute the resistor window.
Verify VIH/VIL margin per domain, confirm the pull-up rails, and measure rise-time on each side if the structure creates two distinct nodes.
Safety or functional isolation, long-noise-return paths, or partitioned subsystems. Each side behaves as a distinct bus.
- Two buses → two resistor windows; compute Rp separately per side.
- Edge shaping or assist inside the isolator/buffer can invalidate pure Rp·Cb assumptions; measure on each side.
- Propagation delay becomes part of the system timing budget (route to timing/structure guidance if needed).
Lock rails per side, recompute Rp_min/Rp_max per side, and verify rise-time using the same compliance definition on both sides.
- With one domain unpowered, measure SDA/SCL voltage and current paths; check for unexpected “lifted” rails.
- Compare idle-state leakage and low-level current with pull-ups enabled/disabled.
H2-9 · Engineering Checklist: Design → Bring-up → Production Gates
This chapter turns pull-up sizing into an executable workflow. Each gate has measurable outputs, a pass criteria, and the fastest fail-action. The goal is stable operation across corners, not a “looks-good-on-scope” demo.
Freeze the measurement definitions and worst-case assumptions so computations and validations share the same target.
- Mode (Std/Fast/Fast+/Hs) and rise-time definition (30–70 or 10–90).
- Pull-up rail (VDD), VOL target, weakest sink capability (IOL).
- Cb worst-case configuration (devices, protection, routing, connectors).
All definitions and worst-case assumptions are documented and traceable (X = completeness threshold).
Stop computation until mode, rise-time definition, pull-up rail, and the worst-case Cb configuration are locked.
Compute the safe resistor window and ensure the selected nominal value remains inside it under all configuration options.
- Compute Rp_max from rise-time limit and worst-case Cb (using the selected definition).
- Compute Rp_min from VOL target and weakest IOL sink capability.
- Compute the feasible window: [Rp_min, Rp_max] and select Rp_nom inside the window.
- Re-check Rp_effective when multiple pull-ups can be enabled in parallel.
Feasible window exists; Rp_nom and all configuration-derived Rp_effective stay within the window (X = guardband policy).
If the window is narrow or missing, route to segmentation/buffering, active pull-up, or a lower speed grade (structure change required).
Reserve board-level escape hatches so bring-up can stabilize the bus without re-spins.
- Multiple Rp footprints (primary + optional population) to tune Rp_effective.
- Optional series-R / RC damping footprints near key branch points (for ringing control).
- Protection options with known capacitance (avoid untracked Cb growth).
- Cross-rail/isolation structure documented (two sides may require two independent windows).
Bill of materials and footprints support at least one controlled stabilization iteration without a board respin (X = minimum options).
Add optional Rp and damping footprints before tape-out; otherwise bring-up risks non-actionable failures.
- Use the selected definition (30–70 or 10–90) and keep it consistent across logs and plots.
- Use short ground reference (ground spring/coax) to avoid probe-induced ringing artifacts.
- Measure at two points (near source and far endpoint) to separate local vs branch-driven behavior.
Measured rise time ≤ limit using the locked definition; measurement method is documented (X = station checklist completeness).
- Capture analog waveform and protocol decode in the same time window.
- Track error stats: NAKs, retries, timeouts, bus-stall recovery events.
- Check correlation: if errors spike without waveform anomalies, re-check structure (parallel pull-ups, cross-rail/isolation nodes, threshold chatter).
Error events are explainable with measured evidence or are routed to the correct structure branch (X = correlation confidence threshold).
- Tune Rp within the computed window; re-check Rp_effective with all optional pull-ups enabled.
- If ringing/chatter is observed: enable damping (series-R / RC) and re-measure threshold crossings.
- If cross-rail or isolation is present: validate rise time and window separately on each side.
Error rates stabilize within the defined window (X = NAK/retry/timeout limits over Y minutes).
- Temperature corners (cold/hot), VDD corners (min/max), and key BOM alternates.
- Harness/connector variants where capacitance and parallel pull-ups change.
- Isolation/level shifting variants where the bus becomes multiple nodes.
Worst-case corner passes: rise time ≤ limit, VOL ≤ target, average power ≤ budget (X = guardband policy).
- NAK count and NAK rate, bucketed by address and read/write direction.
- Retry count and timeout count (include timeout policy version).
- Bus-stall and recovery events (including reset sequence path).
- Optional: sampled rise-time/VOL statistics at station (for trend detection).
Logs are traceable to unit, station, corner condition, and firmware version (X = required field completeness).
Do not ship at the edge of compliance. Use a conservative, station-enforceable guardband for rise time, VOL margin, and error rates.
Guardband and re-test triggers are written into production SOP (X = documented thresholds).
- Rise time: ≤ spec limit (using the locked definition).
- VOL: ≤ VOL_target (checked against weakest IOL).
- Power: average pull-up power ≤ budget (worst-case D_low).
- Robustness: NAK/retry/timeout rates ≤ X within Y minutes (bucketed per endpoint).
- Rise-time definition is locked and used consistently (plots, logs, and pass criteria).
- Cb is worst-case (includes device pins, protection, routing, connector/harness options).
- Rp_effective is verified for all configuration options (parallel pull-ups, modules, population variants).
- Bring-up measurements use short ground reference and at least two measurement points.
- Production SOP includes corners + minimal logging fields so failures remain diagnosable.
H2-10 · Applications (Buckets Only): Where Pull-Up Sizing Becomes the Root Cause
These buckets highlight where pull-up sizing most often becomes the hidden root cause. Each bucket is a short routing guide: scenario → most common failure → where to focus next.
Scenario: many endpoints, protection devices, long routing, and large aggregate pin capacitance.
Most common failure: rise-time margin collapse near the limit → intermittent NAKs and temperature sensitivity.
Next focus: capacitance budget and the computed Rp window (Cb accuracy is usually the limiter).
Scenario: backplanes/harnesses, plug-in modules, and multiple places where pull-ups can exist.
Most common failure: Rp_effective shrinks due to parallel pull-ups; edges become aggressive and ringing increases.
Next focus: verify Rp_effective across configurations; add damping if threshold chatter appears.
Scenario: remote sensors over cables, noisy environments, and large distributed capacitance.
Most common failure: pull-up tuning alone cannot restore robustness because physical-layer constraints dominate.
Next focus: route to a long-reach/extender architecture (pull-up is only one part of the solution).
Scenario: battery-powered systems with long sleep intervals and short burst traffic.
Most common failure: smaller Rp silently increases average pull-up power and shrinks thermal/robustness margin.
Next focus: compute P_avg using worst-case D_low and consider switchable/dynamic pull-up strategies.
- Intermittent NAK / rise-time near the limit → prioritize Cb budget and the Rp window.
- Power budget surprises or configuration-dependent failures → verify Rp_effective and duty-cycle power.
- Ringing, overshoot, false edges → prioritize damping and edge integrity checks.
- Cross-rail or isolation present → treat as two nodes and validate each side separately.
- Need bring-up/production repeatability → use the gate checklist and the unified pass criteria.
IC Selection Logic (Only What Pull-Up Sizing Needs)
When passive pull-ups cannot create a valid Rp window (Rpmin…Rpmax), the fix is usually a structure upgrade that changes the effective capacitance, edge behavior, or isolation boundary—so the window becomes real.
Scope guard: This section lists trigger conditions, upgrade categories, and specs to verify. It does not expand into full topology/long-cable theory.
Trigger Conditions (Gate-Like, Checkable)
- T1 · No window: Rpmin > Rpmax (cannot meet both tr and VOL/IOL).
- T2 · Window too narrow: small tolerance to parallel pull-ups, variants, temperature, or production drift (window width < X).
- T3 · EMC conflict: decreasing Rp fixes tr but worsens ringing/overshoot; increasing Rp improves ringing but breaks tr.
- T4 · Cb is structurally large: capacitance dominated by node count/connectors/cabling and cannot be reduced enough by layout alone.
- T5 · Boundary required: isolation or multi-voltage segmentation forces two distinct bus domains that must be sized independently.
Interpretation: Any trigger means passive Rp alone is no longer the only knob. The next step is choosing a device category that changes the physics (isolates Cb, reshapes edges, or creates a new node).
If/Then Upgrade Paths (with Example Material Numbers)
IF (T1/T2/T4): window is missing/narrow, or Cb is dominated by fanout/connectors.
THEN: use a buffer/repeater or switch/mux to create smaller independent segments.
WHY it helps: segmentation reduces effective Cb per node and prevents parallel pull-ups and branches from collapsing the Rp window.
Example parts (verify package/suffix/voltage/frequency):
TI TCA9517A— level-shifting I²C bus repeater (capacitance isolation via buffering).NXP PCA9517A— level translating I²C repeater (two 400 pF domains typical concept).TI TCA9548A— 8-channel I²C switch/mux (fanout + address conflict + segment selection).NXP PCA9548A— 8-channel I²C switch with reset (segment isolation + recovery hook).TI TCA4307— hot-swappable I²C buffer with stuck-bus recovery (often used as a “boundary” device).ADI LTC4312— 2-channel hot-swappable 2-wire multiplexer with bus buffering (capacitance isolation + selection).
Spec checklist (pull-up sizing critical): per-side supported Cb, VOL behavior (offset vs true low), propagation delay, idle/enable rules, leakage when disabled, stuck-bus recovery/reset behavior.
IF (T5): safety/functional isolation or ground potential differences require separation.
THEN: choose a bidirectional I²C isolator so each side can be sized with its own Rp window.
WHY it helps: isolation forces a clear boundary; pull-ups, thresholds, and Cb are no longer “shared” across the system.
Example parts (verify isolation rating/options):
TI ISO1540 / ISO1541— bidirectional I²C isolators (ordering options differ).TI ISO1640 / ISO1641— robust-EMC, hot-swappable I²C isolators (variants add features).ADI ADuM1250 / ADuM1251— hot-swappable bidirectional I²C isolators.ADI ADuM2250 / ADuM2251— hot-swappable bidirectional I²C isolators (higher isolation variants exist).Skyworks/Silicon Labs SI8600— 2-channel I²C digital isolator (order-code dependent).
Spec checklist (pull-up sizing critical): per-side pull-up requirements, propagation delay (timing margin impact), CMTI/EMC robustness, input thresholds (open-drain behavior), leakage when unpowered, default state on power-up/hot-plug.
Route: Isolation Strategy · Multi-Voltage & Level Translation
IF (T1/T3): tr demands a smaller Rp, but Rp cannot be reduced due to power, IOL/VOL limits, or EMC ringing sensitivity.
THEN: use controlled edge acceleration (strong pull-up only during transitions) or an internal current source approach.
WHY it helps: faster edges are achieved without permanently shrinking Rp, protecting battery budget and reducing continuous low-state dissipation.
Example parts (verify speed grade + bus behavior):
ADI LTC4311— I²C/SMBus rise-time accelerator (slew-limited boosted pull-up behavior).TI TCA4311A— hot-swappable 2-wire bus buffer with rise-time accelerator features (used as boundary + edge help).TI TCA4307— hot-swappable buffer with rise-time accelerators and stuck-bus recovery.TI TCA9800— buffer/repeater with internal current source (can reduce external pull-up dependency on one side).NXP PCA9600— bus buffer designed to isolate capacitance for higher loading cases (route to long-reach details).
Spec checklist (pull-up sizing critical): acceleration trigger threshold, boosted pull-up strength/current, stability with ringing/overshoot, off-state leakage, behavior when one side is unpowered, interaction with parallel pull-ups, and any timing offset added by the device.
Route: EMC & Edge Control · Long-Reach I²C (if cables dominate)
Selection sanity check: devices that “translate” must preserve open-drain semantics and must not create hidden parallel pull-ups that collapse the calculated Rp window. Always re-check Rpmin/Rpmax with the device’s effective pull-up behavior and leakage.
Decision Tree: Passive Pull-Up Fails → Create a New Window
The diagram maps common “no-window” cases to three practical upgrades: segmentation, isolation, or controlled acceleration.
Material-number note: exact order codes (package/grade/suffix) vary by temperature range, automotive options, and stock status. Selection should be locked only after verifying datasheet timing, leakage, and bus behavior against the computed Rp window.
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FAQs: Pull-Up / RC / Measurement Definition (No Scope Creep)
Fast troubleshooting only. Every answer is a fixed 4-line checklist: Likely cause / Quick check / Fix / Pass criteria.
Metrics used (data structure)
- tr(30–70) or tr(10–90) (same definition in calc & measurement)
- Cb_worst (sum of pin + trace + connector + ESD + cable, with margin)
- Rp_eff = 1 / Σ(1/Rp_i) (parallel pull-ups across boards/options)
- VOL vs IOL_weakest (sink capability at corners)
- NAK / retry / timeout rates (per 1k transactions over Y minutes)
- D_low (low-level duty cycle) → P_avg ≈ (VDD² / Rp_eff) · D_low
Triage flow (shortest path): Sanity → Window → Edge/EMC → Boundary → Escalate.
Questions (12) — fixed 4-line answers
400 kHz intermittent NAK: compute t_r first or check VOL first?
Likely cause: Rp window was never verified; either t_r margin (Rp_eff·Cb_worst) or VOL/IOL margin fails at corners.
Quick check: compute Rp_max from t_r_limit and Cb_worst, compute Rp_min from VOL_target and IOL_weakest, then measure both t_r and VOL at the failing condition.
Fix: move Rp_nom inside the intersection (or remove parallel pull-ups); if no intersection, segment (buffer/switch) or reduce speed.
Pass criteria: t_r(definition) ≤ X, VOL ≤ X, NAK rate ≤ X / 1k transactions over Y minutes.
A smaller pull-up made the bus less stable: ringing or threshold-crossing chatter?
Likely cause: faster edges excited parasitic L, creating overshoot/ringing and multiple crossings near VIH/Vth.
Quick check: re-measure with a short ground spring and sufficient bandwidth; count threshold crossings at VIH/Vth and compare source vs receiver pin.
Fix: slightly increase Rp (still within Rp_max) and add a small series-R near the driver/branch to damp ringing; reduce stubs or segment.
Pass criteria: crossings ≤ X, overshoot/undershoot within X, retries/NAKs ≤ X / 1k over Y minutes.
Scope shows compliant rise-time, but protocol still fails: is measurement definition/probing lying?
Likely cause: rise-time definition mismatch (30–70 vs 10–90) or probe/limit settings hide ringing and shift the apparent edge timing.
Quick check: verify the scope measurement definition, disable excessive bandwidth limits, and measure at the receiver pin with proper probing (short ground, minimal loop).
Fix: re-budget using the correct definition and receiver-level measurements; if errors correlate with ringing, apply damping (series-R/segmentation) rather than only shrinking Rp.
Pass criteria: t_r(definition) ≤ X at the receiver pin and error events ≤ X / 1k over Y minutes.
After multiple boards share one bus, it suddenly fails: parallel Rp collapse or Cb jump?
Likely cause: system-level Rp_eff became too small (parallel pull-ups) and/or Cb_worst increased (extra nodes, connectors, ESD), breaking the original sizing.
Quick check: inventory all pull-ups across boards/options, compute Rp_eff, then measure t_r with one board vs all boards to identify the dominant change.
Fix: enforce a single pull-up owner per segment (depopulate others) or add a switch/buffer boundary so each board has a controlled node and window.
Pass criteria: Rp_eff stays within the computed window, t_r ≤ X, idle/low-state current ≤ X, errors ≤ X / 1k over Y minutes.
NAK increases at cold/hot temperature: Rp drift or input threshold/leakage shift?
Likely cause: corner conditions changed the effective window (IOL/VOL capability, leakage, or VIH/Vth behavior), not just the nominal Rp value.
Quick check: capture t_r and VOL at Tmin/Tmax and VDD corners; compare against the same rise-time definition and the weakest-sink assumption.
Fix: re-select Rp_nom with margin for corner leakage/IOL, or isolate/segment the slow/heavy portion; consider controlled acceleration if power limits block smaller Rp.
Pass criteria: t_r ≤ X and VOL ≤ X across Tmin…Tmax and VDD(min)…VDD(max); NAK rate ≤ X / 1k over Y minutes.
One slave “drags” the rising edge: input capacitance or leakage current?
Likely cause: that device adds abnormal C_pin and/or DC leakage, effectively increasing Cb_worst or fighting the pull-up.
Quick check: isolate the device using a mux/switch (or temporarily disconnect) and compare t_r; measure idle-high leakage/clamp current at the pin if possible.
Fix: segment the bus so that device sits on a smaller node; reduce external capacitance on that branch; replace or re-qualify the device if leakage is out-of-family.
Pass criteria: removing/isolating the device changes t_r by ≤ X (expected range), leakage ≤ X, system t_r ≤ X at the receiver pin.
Pull-up to 3.3 V but a device is 1.8 V: how to judge VIH/VIL margin safely?
Likely cause: the pin is not tolerant to the pull-up rail (clamp/leakage/over-voltage), shrinking margins and sometimes causing ghost powering.
Quick check: confirm I/O tolerance and absolute maximum ratings; measure the high level at the device pin and check for clamp current when the device is unpowered.
Fix: pull up to the lowest compatible rail or use a level-shift boundary that preserves open-drain semantics; re-check the Rp window per node.
Pass criteria: VIH margin ≥ X, clamp/leakage current ≤ X, no ghost-power behavior, t_r ≤ X with the correct definition.
After adding an ESD array, rise-time degrades: how to estimate its capacitance impact fast?
Likely cause: the ESD device added enough capacitance to increase Cb_worst, pushing t_r beyond the limit.
Quick check: measure t_r before/after; back-calculate ΔC using the same definition and an assumed coefficient (e.g., t_r ≈ k·Rp_eff·Cb).
Fix: choose a lower-capacitance ESD part, move protection to a boundary/segment, or add buffering so protection capacitance stays local.
Pass criteria: ΔC stays within the Cb budget (≤ X), t_r ≤ X at receiver, and error rate ≤ X / 1k over Y minutes.
Long cable and passive pull-ups never work: when is segmentation or a differential extender mandatory?
Likely cause: distributed cable capacitance/noise makes the required Rp violate VOL/IOL or power constraints, so the Rp window is physically impossible.
Quick check: estimate cable C per meter and compute the needed Rp_max; if Rp_min > Rp_max (no intersection), passive tuning cannot solve it.
Fix: create new nodes via buffering/segmentation, use active edge help where appropriate, or move to an extender/differential transport; reduce speed as a containment step.
Pass criteria: stable operation over length L with error rate ≤ X / 1k over Y minutes, and endpoint t_r/VOL within limits (definition-consistent).
Low-power duty-cycle: how to translate Rp into average power and battery-life impact?
Likely cause: average dissipation is underestimated because D_low and Rp_eff (parallel pull-ups) were not included in the budget.
Quick check: compute P_avg ≈ (VDD² / Rp_eff) · D_low and compare to measured supply current during representative traffic patterns.
Fix: increase Rp within the window, remove unintended parallel pull-ups, or use switchable pull-ups / controlled acceleration so strong pull-up exists only during edges.
Pass criteria: I_avg ≤ X and estimated battery-life ≥ X while maintaining t_r ≤ X and VOL ≤ X under worst-case D_low.
Production: “same lot, different boards” show different edges — Cb distribution or assembly/layout variation?
Likely cause: Cb_worst is not controlled in production (variant ESD/connector/layout/assembly), or pull-up stuffing options change Rp_eff across units.
Quick check: correlate t_r with BOM options and assembly variants; sample-measure t_r at a fixed test point and compute distribution (P50/P90/P99).
Fix: lock the capacitance contributors (ESD C, connector family), define a single pull-up owner, add gate criteria and a testpoint for repeatable t_r measurement.
Pass criteria: t_r distribution P99 ≤ X, VOL ≤ X, and field error rate ≤ X across sample size N and corner screening.
Logic analyzer shows occasional decode errors: can threshold/sample-rate/bandwidth settings mislead?
Likely cause: analyzer thresholds/sampling are not aligned to the real VIH/VIL timing, or the setup hides/reveals noise differently than the receiver input.
Quick check: set analyzer thresholds explicitly, increase sample rate, and cross-check with a scope measurement at the same node to verify single threshold crossing.
Fix: treat the analyzer as a protocol/event tool and validate edges with the scope; if crossings/ringing exist, apply damping or segmentation rather than trusting decode alone.
Pass criteria: analyzer reports 0 decode errors over N frames and scope shows crossings ≤ X with t_r ≤ X at the receiver pin.
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