Low-Power Hooks for I²C / SPI / UART Serial Buses
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Low-Power Hooks are deliverable engineering controls that make I²C/SPI/UART sleep–wake behavior measurable, deterministic, and recoverable—not a slogan. The target is to minimize average power while bounding wake latency and guaranteeing first-transaction success with evidence (tags/logs/counters) and a proven recovery gate.
Definition & Goals: what “Low-Power Hooks” really means
“Low-Power Hooks” is an engineering deliverable: a set of system-level mechanisms that guarantees sleep/wake/recovery without data loss, avoids bus lock-ups, and remains measurable and production-testable.
What this topic optimizes
- Average power (µA/mA): total energy per representative cycle, not just the sleep current snapshot.
- Wake latency (µs/ms): time from wake event to the first verified transaction completion.
- Robustness: lock-up probability, recovery success rate, and maximum time-to-recover (MTTR) under brown-out/noise edge cases.
Typical operating scenarios (choose priorities upfront)
- Periodic sampling: minimize average power while keeping deterministic wake-to-sample latency.
- Event-driven wake: prioritize wake reliability (missed wake = functional failure), then optimize idle residency.
- Long standby + burst communication: prioritize robustness (no “wake-then-deadlock”), then optimize burst cost and retry budget.
The core tension: clock gating vs. state retention
- Clock gating reduces dynamic power, but can increase wake complexity and the probability of “first-transaction failure” if timing/bring-up ordering is weak.
- State retention / bus-hold / sticky-state reduces recovery risk and wake time, but costs leakage/hold power and requires explicit domain planning.
Pass criteria (placeholder): stable sleep entry, deterministic wake-to-first-transaction, and recovery within threshold X across voltage/temperature cycles.
Minimum deliverables (hooks that make sleep/wake “provable”)
- Domain map: always-on vs. switchable rails/clocks; retention coverage for critical state.
- Wake chain: wake sources, enable ordering, “ready” checkpoints (rail good → clock stable → peripheral ready).
- Safe pin states: default levels for CS/SCLK/lines, bus-hold strategy, and ghost-power avoidance at boundaries.
- Recovery state machine: sanity checks, re-init steps, first-transaction guard, and bounded retries/timeouts.
- Instrumentation: GPIO tags, counters, reset-cause logging, and production-test entry to validate residency/latency/robustness.
Power Accounting: average power model & what to measure
Low power must be reported as energy per representative cycle, not as a single “sleep current” number. Average power follows Pavg = Etotal / T, where Etotal is the sum of segment energies across sleep, wake, communication bursts, and recovery.
A practical energy ledger (include the “hidden” terms)
- E_sleep_static: baseline sleep leakage and always-on background.
- E_hold_retention: bus-hold, state retention, pull-up/hold costs (domain-dependent).
- E_wake_transient: rail settling, clock start/lock, and peripheral enable surges.
- E_comm_burst: TX/RX activity during the intended workload burst.
- E_retry_recovery: failed transactions, retries, and recovery state machine execution.
Design rule: if E_retry_recovery is non-negligible, the system is not low-power in the field.
Parameters that dominate average power (capture distributions, not only averages)
- Sleep residency (duty cycle) and wakeups/hour.
- Burst profile: message size, burst duration, and inter-burst gaps.
- Retry budget: mean and tail (P95/P99) retries per wake or per hour.
- Pull-up/hold cost (e.g., I²C): depends on line-low occupancy and which rail sources the pull-up.
- Driver activity (SPI/UART): switching activity during burst and recovery retries.
Measurement method (repeatable, segment-based, and audit-friendly)
Step 1 · Add GPIO tags to mark segments
- Tag points: Sleep entry, Wake ISR, First transaction start, First transaction done, Recovery begin/end.
- Use tags as triggers for both current measurement and bus decoding.
Step 2 · Integrate energy per segment
- Compute E = ∫ V(t)·I(t) dt per segment; keep the same cycle length T for comparisons.
- Validate model closure: Etot ≈ ΣE_segment within measurement tolerance.
Step 3 · Stress the tail (field realism)
- Sweep voltage/temperature and intentionally trigger borderline wake conditions.
- Track how E_retry_recovery scales; sudden growth indicates a robustness gap, not a “power optimization” issue.
Pass criteria (placeholder): segment energies remain bounded; retry/recovery energy stays below threshold X per hour across stress conditions.
Definition & Goals: what “Low-Power Hooks” really means
“Low-Power Hooks” is an engineering deliverable: a set of system-level mechanisms that guarantees sleep/wake/recovery without data loss, avoids bus lock-ups, and remains measurable and production-testable.
What this topic optimizes
- Average power (µA/mA): total energy per representative cycle, not just the sleep current snapshot.
- Wake latency (µs/ms): time from wake event to the first verified transaction completion.
- Robustness: lock-up probability, recovery success rate, and maximum time-to-recover (MTTR) under brown-out/noise edge cases.
Typical operating scenarios (choose priorities upfront)
- Periodic sampling: minimize average power while keeping deterministic wake-to-sample latency.
- Event-driven wake: prioritize wake reliability (missed wake = functional failure), then optimize idle residency.
- Long standby + burst communication: prioritize robustness (no “wake-then-deadlock”), then optimize burst cost and retry budget.
The core tension: clock gating vs. state retention
- Clock gating reduces dynamic power, but can increase wake complexity and the probability of “first-transaction failure” if timing/bring-up ordering is weak.
- State retention / bus-hold / sticky-state reduces recovery risk and wake time, but costs leakage/hold power and requires explicit domain planning.
Pass criteria (placeholder): stable sleep entry, deterministic wake-to-first-transaction, and recovery within threshold X across voltage/temperature cycles.
Minimum deliverables (hooks that make sleep/wake “provable”)
- Domain map: always-on vs. switchable rails/clocks; retention coverage for critical state.
- Wake chain: wake sources, enable ordering, “ready” checkpoints (rail good → clock stable → peripheral ready).
- Safe pin states: default levels for CS/SCLK/lines, bus-hold strategy, and ghost-power avoidance at boundaries.
- Recovery state machine: sanity checks, re-init steps, first-transaction guard, and bounded retries/timeouts.
- Instrumentation: GPIO tags, counters, reset-cause logging, and production-test entry to validate residency/latency/robustness.
Power Accounting: average power model & what to measure
Low power must be reported as energy per representative cycle, not as a single “sleep current” number. Average power follows Pavg = Etotal / T, where Etotal is the sum of segment energies across sleep, wake, communication bursts, and recovery.
A practical energy ledger (include the “hidden” terms)
- E_sleep_static: baseline sleep leakage and always-on background.
- E_hold_retention: bus-hold, state retention, pull-up/hold costs (domain-dependent).
- E_wake_transient: rail settling, clock start/lock, and peripheral enable surges.
- E_comm_burst: TX/RX activity during the intended workload burst.
- E_retry_recovery: failed transactions, retries, and recovery state machine execution.
Design rule: if E_retry_recovery is non-negligible, the system is not low-power in the field.
Parameters that dominate average power (capture distributions, not only averages)
- Sleep residency (duty cycle) and wakeups/hour.
- Burst profile: message size, burst duration, and inter-burst gaps.
- Retry budget: mean and tail (P95/P99) retries per wake or per hour.
- Pull-up/hold cost (e.g., I²C): depends on line-low occupancy and which rail sources the pull-up.
- Driver activity (SPI/UART): switching activity during burst and recovery retries.
Measurement method (repeatable, segment-based, and audit-friendly)
Step 1 · Add GPIO tags to mark segments
- Tag points: Sleep entry, Wake ISR, First transaction start, First transaction done, Recovery begin/end.
- Use tags as triggers for both current measurement and bus decoding.
Step 2 · Integrate energy per segment
- Compute E = ∫ V(t)·I(t) dt per segment; keep the same cycle length T for comparisons.
- Validate model closure: Etot ≈ ΣE_segment within measurement tolerance.
Step 3 · Stress the tail (field realism)
- Sweep voltage/temperature and intentionally trigger borderline wake conditions.
- Track how E_retry_recovery scales; sudden growth indicates a robustness gap, not a “power optimization” issue.
Pass criteria (placeholder): segment energies remain bounded; retry/recovery energy stays below threshold X per hour across stress conditions.
Clock Gating Strategy: gate what, keep what
Clock gating is safe only when boundary conditions remain enforced: wake detection, timeout timebase, watchdog recovery, and deterministic pin states must survive the sleep boundary.
Clock layers (what is actually being gated)
- System / SoC clock: CPU + fabric timing base; impacts resume ordering and timekeeping.
- Peripheral clock: I²C/SPI/UART controller logic; must be restored before any transaction.
- IO / pad clock: pad sampling/drive and synchronizers; protects pin stability across sleep.
- Sampling clock: oversampling / internal sampling windows; affects first-transaction validity.
Must-keep capabilities (Always-On / Wake domain)
- Wake chain: wake cause latching and a reliable event path.
- Timeout timebase: bounded waits for bus sanity, recovery, and first-transaction guard.
- Watchdog / fail-safe: a hard stop when firmware state machines stall.
- Minimal logging: wake cause, reset cause, retry/timeout counters for auditability.
Pass criteria (placeholder): timeouts remain active during and after sleep; pin safe-states remain deterministic; recovery completes within threshold X.
Common failure modes (sleep boundary hazards)
FM1 · Timeout base gated off
- Symptom: rare “never returns” hangs during wake or first transaction.
- Quick check: timeout counters stop changing; waits have no bound.
- Fix: move timeout timer to AON or restore timer before enabling buses.
FM2 · IO / pad domain gated off
- Symptom: CS/SCLK/lines drift; false wake or ghost-power paths appear.
- Quick check: pin readback differs before/after sleep; safe-level not held.
- Fix: enable bus-hold/keeper, retain pads, or enforce safe states before gating.
FM3 · Wrong entry/exit ordering
- Symptom: first transaction fails → retries explode → average power increases.
- Quick check: first-transaction success rate drops only after gating changes.
- Fix: define an ordered checklist: safe pins → gate clocks → sleep; wake → clocks → peripherals → sanity → first txn.
Sleep/Wake Handshake: designing deterministic wake latency
A reliable wake-up must be a measurable chain: event detect → rail ready → clock stable → peripheral ready → bus sanity → first verified transaction.
Wake paths (choose based on domain availability)
- GPIO wake: simplest and robust; record wake cause and debounce if needed.
- RTC wake: deterministic periodic tasks; ideal for sampling loops.
- Peripheral IRQ wake: only safe if the IRQ and its latching remain in Always-On or retained logic.
- Bus-event wake (e.g., address match): useful but sensitive; requires strict ordering, logging, and bounded retries.
Latency budget: assign time and pass criteria per segment
- Detect: wake cause latched (tag + counter).
- Rail ready: PGOOD/threshold stable for a defined window.
- Clock stable: PLL lock or safe clock selected (no undefined timing).
- Peripheral ready: reset complete, key registers restored, FIFOs cleaned.
- First verified transaction: sanity check passes and the first transaction verifies (ACK/CRC/frame).
Pass criteria (placeholder): each segment meets its time budget; first-transaction success rate meets threshold X without unbounded retries.
Two-stage wake (fast proof, then full enable)
Stage 1 · Minimal bring-up (fast)
- Enable Always-On timer + logging; latch wake cause and reset cause.
- Restore only required clocks and one bus path for sanity + first transaction.
- If Stage 1 fails, enter bounded recovery instead of “trying forever”.
Stage 2 · Full enable (stable)
- Enable high-speed clocks and full peripheral features only after Stage 1 passes.
- Promote performance gradually to avoid tail-latency spikes from unstable initial conditions.
Bus-Hold & Sticky-State: preventing float, ghost-power, and surprise states
Sleep robustness often depends on “holding” more than “turning off”. Across the sleep boundary, pins must not float, peripherals must not be back-powered through IO, and the wake resume must not inherit surprise states.
Bus-hold targets (define a sleep safe-state spec)
- Line levels: define High/Low/Hi-Z per signal; ensure the chosen state is still enforced in deep sleep.
- Chip-select & enables: CS/EN/RESET must be deterministic to prevent accidental commands and false wake paths.
- Pull-ups & keepers: choose external pull-ups, keepers, or pad retention based on which power domain remains alive.
- Direction control: 3-wire / bidirectional pins must not flip direction across sleep, avoiding contention and extra current.
- Isolation enables: isolator / level-shifter EN must track power domains to avoid floating or backfeed.
Sticky-state policy (retain intentionally, reset intentionally)
- Retain: configuration that shortens wake time (modes, thresholds, safe defaults) when retention is reliable.
- Do not retain: transient state machines, FIFOs, and error flags that can poison the first transaction after wake.
- Shadow & replay: keep a minimal “golden config” shadow and re-apply non-retained items in a fixed order on resume.
Resume recipe (ordered, proof-friendly)
- Read-back sanity: verify pin states and key retained bits match expectations.
- Clear sticky errors: clear latched error flags and reset transient counters.
- Re-apply non-retained config: restore only what is required for first transaction validity.
- First-transaction guard: execute a bounded verification transaction before enabling full throughput.
Ghost-power audit (backfeed must be measurable and bounded)
Typical backfeed paths
- IO high drives into a powered-off peripheral through pad clamp/ESD structures to VDD.
- Pull-ups referenced to a live rail while peripheral VDD is off (common in open-drain buses).
- Level shifters/isolators enabled with mismatched domains, creating unintended current paths.
Field-proof checks (fast)
- VDD lift: when peripheral VDD is “off”, measure whether it rises above threshold X (placeholder).
- Reverse current: measure backfeed current below threshold X (placeholder).
- Pin determinism: compare pin readback before/after sleep; no drift beyond defined logic thresholds.
Common fixes (hook-level)
- Reference pull-ups/keepers to the correct domain or use switchable pull-ups tied to the peripheral rail.
- Add series resistance or powered-off-protection switches where backfeed risk is high.
- Control isolator/level-shifter EN so “powered-off” truly isolates, avoiding surprise current paths.
Pass criteria (placeholder): powered-off peripherals stay below VDD threshold X; backfeed current below X; first-transaction success rate above X after sleep cycles.
Protocol-Specific Low-Power Hooks (I²C / SPI / UART) — only what matters for sleep/wake
This section intentionally avoids protocol encyclopedias. It extracts only three hook categories per bus: sleep safe state, wake trigger, and first verified transaction.
I²C low-power hooks
Sleep safe state
- Pull-up reference rail must match the intended power domain plan (avoid backfeeding powered-off peripherals).
- Before sleep, lines should be released and read back High; pin hold must remain effective in deep sleep.
Wake trigger
- Prefer GPIO/RTC/peripheral IRQ wake; bus-event wake is safe only when address-detect logic remains available in AON/retained logic.
- Always latch wake cause and count wake attempts for audit.
First transaction guard
- On wake, check SCL/SDA levels; if abnormal, enter a bounded “hung-bus” recovery entry before any workload.
- Use bounded retries/timeouts; unbounded waiting is a power and robustness failure.
SPI low-power hooks
Sleep safe state
- CS must be held inactive deterministically; avoid floating CS during sleep.
- SCLK must remain quiet across sleep; 3-wire direction/OE must be forced to a safe state to avoid contention.
Wake trigger
- SPI rarely acts as a wake source; use GPIO/RTC/IRQ and keep wake cause logging.
- Avoid enabling high-speed clocks until Stage-1 bring-up passes.
First transaction guard
- Restore mode/config, then enable SCLK, then perform a read-back verification (ID/status) before full throughput.
- Bound retries and record first-transaction outcomes to correlate power spikes with wake failures.
UART low-power hooks
Sleep safe state
- RX/TX must be deterministic to avoid false start-bit detection; confirm internal pulls remain active in deep sleep if relied upon.
- If powered-off protection is not guaranteed, prevent backfeed by not driving into an unpowered peer.
Wake trigger
- Wake-on-RX requires low-power detect logic and a valid timebase; break/idle wake is practical but must be bounded against noise.
- Always latch wake cause and count wake attempts for auditability.
First transaction guard
- Re-sync baud (auto-baud or divisor restore) before trusting received frames; flush boundary noise if needed.
- Track framing/parity error rate in the first N bytes after wake; keep below threshold X (placeholder).
Pass criteria (placeholder): each bus meets its defined sleep safe state; wake cause is logged; first-transaction verification passes within bounded time and retries.
Brown-Out / Hot-Plug Recovery: never resume into a broken bus
Sleep boundary, brown-out, and hot-plug are the same failure class: recovery must be state-first (sanity), then rebuild (re-init), then prove (first guarded transaction). Never resume straight into workload traffic.
ResetCause evidence (must be logged, not guessed)
- Power-good history: PGOOD stable window ≥ X ms (placeholder) before trusting peripherals.
- BOR / reset flags: brown-out indicators and reset-reason registers map to a single ResetCause enum.
- Wake cause latch: wake pin/RTC/IRQ is captured even if the resume later escalates to re-init.
Minimum log fields
reset_cause · wake_cause · pgood_stable_ms · bus_sanity_fail_flag · reinit_count · first_txn_ok_flag · retry_count
Recovery template (ordered, bounded, proof-friendly)
- Bus sanity check: do not start workload traffic; verify line/idle states and enter bounded recovery if abnormal.
- Peripheral re-init: clear transient state (FIFOs/errors), re-apply required configuration in a fixed order.
- First guarded transaction: execute a low-risk verify transaction (ID/status) with bounded retries/backoff before full enable.
Pass criteria (placeholder): sanity completes ≤ X ms; first-transaction verifies within ≤ X ms; failures converge to re-init or fail-safe with logged error codes.
Typical entry actions (hook-level, no protocol sprawl)
I²C
- Check SCL/SDA released High; if SDA is stuck Low, enter bounded clock-out recovery entry then re-check.
- Do not proceed until sanity passes or the system reports a fail-safe code.
SPI
- Force CS inactive and keep SCLK quiet; clear peripheral transient state before enabling full-speed clocks.
- Optional bounded “dummy clocks” can realign peripheral state before the first verify read-back.
UART
- Flush boundary noise and re-sync framing/baud before trusting the first received frame.
- Discard the first frame(s) within a bounded window if sync is not yet confirmed.
Firmware State Machine: timeouts, retries, and idempotent transactions
Low-power systems fail when a partial transaction meets retries and state divergence. A robust implementation enforces idempotent behavior, bounded waiting, and budgeted retries with explicit failure exits and telemetry.
Idempotency rules (repeat without side effects)
- Prefer verifyable writes: write then read-back to confirm the target state rather than assuming success.
- Avoid toggle semantics: commands that flip state on each execution must be wrapped with pre-check and post-verify.
- Non-idempotent operations: gate EEPROM/page writes or multi-step commits behind a two-stage guard (prepare → commit) where possible.
Timeout hierarchy (short → long → watchdog)
- Short timeout: per wait-point (ACK, FIFO, idle). Goal: prevent single-point stalls.
- Long timeout: per transaction. Goal: force convergence to recovery within X ms (placeholder).
- Watchdog: last-resort for control-plane failures; reboots must re-enter the H2-7 recovery gate.
Requirement: timebase for timeouts must remain valid across the chosen sleep depth (avoid “timeouts disabled by clock gating”).
Retry budget & telemetry (retries must have a cost ceiling)
- Max retries: set per transaction type; exceeding budget is a failure, not a “maybe later”.
- Backoff: apply bounded backoff to avoid tight retry loops that destroy average power.
- Report fields: retry_count, timeout_stage, last_error, reset_cause, first_txn_fail_flag.
Transaction wrapper (template)
- Pre-check: bus sanity + domain readiness + pin safe-state.
- Execute: run one bounded transaction (no unbounded waits).
- Verify: read-back/CRC/frame validity with explicit pass criteria (placeholder).
- Retry/backoff: bounded attempts, backoff, and telemetry updates.
- Fail-safe: converge to re-init/recovery gate and surface error codes.
Pass criteria (placeholder): any transaction terminates within bounded time; repeated execution does not create side effects; failures always return a diagnosable code path.
Verification & Instrumentation: prove low power without self-deception
A low-power design is only real when it is measurable, repeatable, and diagnosable. Verification must cover average power, wake latency tail behavior, recovery success rate, and boundary conditions across stress dimensions.
Probe triplet (minimum instrumentation set)
1) GPIO tags
Stage markers aligned with current waveforms: sleep_entry · wake_detect · rail_ready · clock_ready · sanity_begin/end · reinit_end · guard_txn_done · resume.
2) Log fields
reset_cause · wake_cause · pgood_stable_ms · sleep_depth · first_txn_ok_flag · bus_sanity_fail_flag · last_error_code · timeout_stage.
3) Counters
wake_count · guard_fail_total · reinit_total · retry_total · i2c_nak_total · crc_error_total · uart_framing_total · brownout_total.
Measurement rules (avoid “pretty sleep current” traps)
- Use segmented energy: integrate sleep / wake spike / traffic / retry-recovery and close the accounting loop.
- Use tail latency: report wake and recovery as p95/p99 and maximum, not only average.
- Count retries: retry/backoff time is part of average power and must be visible in counters and logs.
Pass criteria (placeholder): I_avg ≤ X; T_wake_p99 ≤ X; recovery_success ≥ X%; T_recover_max ≤ X; failures converge to fail-safe within ≤ X ms with codes logged.
Stress test matrix (dimensions × metrics)
- Dimensions: temperature · voltage · cable/length · noise injection · sleep cycles (N) · load profile.
- Metrics: I_avg · E_wake · T_wake_p99 · first_txn_success · recovery_success · retry_budget_usage.
- Reliability: run long sleep/wake loops and record drift in success rate and retry growth.
Hardware Hooks Checklist: pins, rails, and layout choices that enable low power
Hardware hooks must exist before firmware can measure, control, and verify low-power behavior. The checklist below focuses on pins, power-domain boundaries, default states, and layout pitfalls that directly impact sleep/wake success and true average power.
Pin hooks (control + safe defaults + observability)
- WAKE: a deterministic wake input; debounced/qualified in the chosen sleep depth.
- PWR_EN: controls switchable rails; supports staged bring-up (minimal → full).
- ISO_EN (if isolation/level shifting exists): aligns IO validity with rail state to prevent backfeed.
- PERIPH_RST: forces known peripheral state after brown-out/hot-plug.
- GPIO tag pins: exported stage markers for power/latency correlation during validation.
Rails & pull strategy (Always-On vs Switchable)
- Define domains: Always-On domain retains wake/timebase/log; Switchable domain powers high-cost peripherals.
- Pull-ups must match rail intent: open-drain pulls tied to an always-on rail can backfeed an off peripheral.
- Default-state safety: CS inactive, SCLK quiet, I²C released, UART RX idle are enforced by pulls/keepers/retention.
Pass criteria (placeholder): peripheral VDD rise during off-state ≤ X; backfeed current ≤ X; safe-state pins hold within defined levels across sleep.
Layout pitfalls (only what impacts low-power correctness)
- Leakage paths: contamination, flux residue, and high-impedance nodes can dominate µA budgets.
- Floating inputs: undefined levels cause spurious wake events and retry storms; enforce pulls/keepers.
- Over-strong pulls: pulls that are too small waste static power; size against required edge/timing and duty.
Engineering Checklist: design → bring-up → production
The page becomes deliverable when the low-power hooks are enforced as three gates. Each item includes an action, evidence, and pass criteria (threshold placeholders). Example material numbers are provided as references; verify package/suffix/availability and system constraints.
Gate 1 — Design (freeze definitions, hooks, and evidence)
1) Freeze the average-power accounting model
Evidence: segmented buckets: E_sleep / E_wake / E_txrx / E_retry and required counters (wake_count, retry_total, error totals).
Pass criteria: model closes within ≤ X% vs measured energy for a defined duty profile.
2) Freeze power domains and timebase survivability
Evidence: Always-On vs Switchable domain map showing which blocks remain alive (wake detect, timeout timebase, minimal logs).
Pass criteria: timeout logic remains valid in the chosen sleep depth; no “infinite wait” states.
3) Freeze safe default states at sleep boundaries
Evidence: schematic annotations for pulls/keepers/retention: CS=inactive, SCLK=quiet, I²C=released, UART RX=idle.
Pass criteria: pin levels remain within defined VIH/VIL margins across sleep without ghost-power.
4) Freeze recovery gate and failure convergence
Evidence: state machine: ResetCause → Sanity → Reinit → Guard Txn → Resume with explicit fail-safe branch.
Pass criteria: recovery completes ≤ X ms or exits to fail-safe with codes logged (no unbounded retries).
5) Freeze instrumentation triplet: tags, logs, counters
Evidence: GPIO tag list + log field list + counter list aligned with power and latency measurements.
Pass criteria: every failure path produces a diagnosable code and increments counters.
6) Freeze retry and timeout budgets
Evidence: max retries per transaction type + backoff policy + short/long/watchdog timeout hierarchy.
Pass criteria: retry cost ceiling enforced; retry storms cannot dominate average power.
Reference parts (Design gate examples)
- Load switch (SW rail): TI TPS22916, TPS22918, TPS22965
- Voltage supervisor / reset: TI TPS3839, TI TPS3808, Microchip MCP100
- RTC wake source: Micro Crystal RV-3028-C7, Abracon AB1805, NXP PCF85263A
- Duty-cycle timer: TI TPL5110, TI TPL5010
- GPIO expander (safe-state assists): TI TCA9535, NXP PCA9535
Note: material numbers are references; select variants by voltage range, package, leakage, enable polarity, and required default behavior.
Gate 2 — Bring-up (measure segmented energy, tails, and recovery)
1) Validate segmented energy with GPIO tags
Evidence: current waveform aligned to tags (sleep_entry → wake → sanity → guard_txn → resume) and per-segment energy totals.
Pass criteria: E_wake + E_retry remain below defined budgets (placeholders) for the target duty cycle.
2) Verify wake latency ladder (tail-focused)
Evidence: T_wake measured from true trigger to guard_txn_done; report p95/p99/max.
Pass criteria: T_wake_p99 ≤ X; T_recover_max ≤ X (placeholders).
3) Inject boundary failures and enforce convergence
Evidence: brown-out/hot-plug cases trigger ResetCause; hung-bus/fault injections route through Sanity → Reinit → Guard Txn.
Pass criteria: recovery_success ≥ X% over N cycles and stress corners (placeholders); failures exit with codes.
4) Validate retry budgets as power budgets
Evidence: retry_total and retry time share remain bounded; backoff does not create long tail explosions.
Pass criteria: retry_budget_usage ≤ X and does not dominate I_avg (placeholders).
Reference parts (Bring-up instrumentation examples)
- Power/energy monitor: TI INA228, TI INA226, ADI LTC2944
- Fuel gauge (battery nodes): TI BQ27441, Maxim MAX17048
- Bus isolation w/ enable (if needed for power domains): TI ISO1540, ADI ADuM1250
Gate 3 — Production (test mode, BIST, exportable diagnostics)
1) Provide a deterministic factory test mode
Evidence: mode forces a known sleep depth, fixed wake source, and bounded transaction scripts.
Pass criteria: production sequence completes ≤ X s with deterministic logs and counters.
2) Provide BIST/loopback hooks and counter control
Evidence: loopback/guard transaction can be executed without external stimulus; counters can be read and cleared.
Pass criteria: guard_txn_success ≥ X% over N cycles at production conditions (placeholders).
3) Exportable diagnostics and error codes
Evidence: standardized error codes map to recovery branches; logs include reset_cause/wake_cause/timeout_stage.
Pass criteria: field returns can be triaged using codes + counters without reproducing full lab conditions.
Reference parts (Production hooks examples)
- Programming / test connector: Tag-Connect TC2030 (spring-pin cable system)
- Reset/supervisor for deterministic boot: TI TPS3839, Microchip MCP100
- Load switch for rail sequencing tests: TI TPS22916, TPS22965
Applications (typical profiles for low-power hooks)
The goal is not protocol coverage; it is selecting the right hooks to meet power, latency, and robustness targets for common field profiles. Each profile lists the critical hooks and reference parts (verify constraints and variants).
Battery sensor node (periodic sample + event wake)
- Power profile: long sleep, short wake bursts; retries can dominate I_avg.
- Critical hooks: RTC/timer wake, safe default bus states, retry budget + backoff, segmented energy measurement.
- Common failures: spurious wake, ghost-power through pull-ups, partial transactions with re-tries.
- Pass criteria: I_avg ≤ X; T_wake_p99 ≤ X; first_txn_success ≥ X% (placeholders).
Reference parts
RV-3028-C7 · AB1805 · TPL5110 · TPS22916 · TPS3839 · MAX17048 · BQ27441
Industrial monitoring (long standby + alarm bursts)
- Power profile: standby for hours/days; bursts must resume deterministically.
- Critical hooks: ResetCause logging, recovery gate (sanity→reinit→guard), error codes + counters for field triage.
- Common failures: brown-out resumes into a broken bus, long-tail recovery, repeated retries increasing I_avg.
- Pass criteria: recovery_success ≥ X% over N cycles; T_recover_max ≤ X (placeholders).
Reference parts
TPS3839 · TPS3808 · TPS22965 · INA228 · INA226 · ISO1540 · ADuM1250 · TC2030
Portable instrument (fast wake + data consistency)
- Power profile: frequent wake; tail latency defines UX and measurement readiness.
- Critical hooks: staged bring-up (minimal→full), guard transaction before measurement, idempotent configuration writes.
- Common failures: first frame invalid after wake, partial configuration, silent state divergence across retries.
- Pass criteria: T_wake_p99 ≤ X; first_txn_success ≥ X%; retry_budget_usage ≤ X (placeholders).
Reference parts
TPS22916 · TPS3839 · INA226 · RV-3028-C7 · TCA9535 · TPS22918
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FAQs (Low-Power Hooks)
These FAQs close common bring-up and field-debug loops strictly within the Low-Power Hooks boundary. Each answer uses a fixed 4-line, data-oriented structure to drive measurable verification.
