• Check: Port-zone keep-out and zoning (PHY/Mag/connector as a single “EMC island”).
  Why: The port boundary is the dominant CM injector / antenna feed for RE/RI failures.
  Pass: Port-zone boundary is explicit; sensitive clock/SoC zone is separated by X mm and no return-plane cuts cross the boundary.
• Check: Continuous reference planes under diff pairs; no slot/cut that forces detoured return current.
  Why: Return detours increase loop area and convert DM energy into CM radiation.
  Pass: Return continuity verified by layout review; any unavoidable split has a deliberate stitch strategy with spacing ≤ X.
• Check: “Low-C ESD clamp option” is designed-in at the connector boundary (footprint + placement rules).
  Why: ESD robustness depends on where current returns, not only on the diode rating.
  Pass: TVS pads sit at the boundary; the return path to chassis/shield is shorter than X; example parts: Nexperia PESD2ETH-D / PESD2ETH-AX, Semtech RClamp0524P.
• Check: Shield bond strategy is explicitly chosen (360° bond / hybrid bond / capacitive bond) with leakage trade-off recorded.
  Why: Shield termination dominates CM spectral peaks and immunity behavior.
  Pass: Strategy is documented with “allowed leakage vs EMC target”; the bond hardware is placed at connector entry, not inside the core zone.
• Check: Magnetics/connector placement supports short CM loop (connector → magnetics → PHY) without plane discontinuity.
  Why: Long CM loops and cavity-like gaps become efficient antennas.
  Pass: Placement corridor is ≤ X; example integrated magnetics options (as BOM seeds): Pulse J0011D21BNL, Würth 7499111121A.
• Check: PHY selection includes robustness hooks (ESD tolerance class, diagnostic counters, stable link recovery behavior).
  Why: The same layout can behave differently due to PHY recovery policy and latch sensitivity.
  Pass: A robustness checklist is mapped to candidate PHYs; examples: TI DP83822I (10/100), TI DP83867IR (GbE), Microchip LAN8742A (10/100), Microchip KSZ9031RNX (GbE).
• Check: Time sync domain is treated as an EMC victim (clock rails, reference routing, isolation from port CM).
  Why: Small CM events can cause timestamp steps even when the link stays up.
  Pass: Clock domain has its own return/decoupling integrity; candidate timing parts (BOM seeds): Renesas 8A34001, Microchip ZL30732A, Microchip ZL30364, Skyworks/SiLabs Si5341A.
• Check: PoE/PoDL current paths are not allowed to share noisy impedance with PHY reference.
  Why: Surge/EFT often couples through common impedance and causes resets/CRC bursts.
  Pass: Power-return segmentation is explicit; ports have a defined surge return; example PoE parts: TI TPS23881 (PSE), TI TPS2372/TPS2373 (PD), ADI LTC4266 (PSE), ADI LTC4267 (PD), and PoDL PD seed: ADI LTC9111.
• Check: “Pass criteria fields” are designed into firmware/logging from day-0.
  Why: EMC failures must be measurable beyond “link up/down”.
  Pass: The system logs: CRC/PCS errors, link flap counts, reset cause, timestamp step, PTP offset drift, and recovery time; thresholds are defined as X.

• Check: Baseline “clean-room” link metrics are captured (PRBS/loopback counters, idle noise floor).
  Why: EMC debugging requires a known-good baseline to detect degradation patterns.
  Pass: Baseline dataset exists for each port type and cable class; variance bands are defined as X.
• Check: Near-field scan points are pre-defined (port boundary, magnetics edge, clock island, PoE hot loop).
  Why: “Search everywhere” wastes time; EMC needs repeatable measurement points.
  Pass: A scan map exists with coordinates and probe orientation; top 5 hotspots are tracked over revisions.
• Check: CM vs DM classification step is mandatory before any fix (current clamp / probe A-B / shield bond toggle).
  Why: Fixes that reduce DM can increase CM peaks (worsening RE/RI).
  Pass: Every debug log starts with CM/DM classification and measured delta; no fix is accepted without the delta.
• Check: Pre-ESD and pre-RI screening is performed on representative harnesses, not only short lab cables.
  Why: Harness length and shield continuity shift resonance and CM spectral peaks.
  Pass: At least X harness variants are screened; results are tied to revision control.
• Check: Timestamp integrity is tested under disturbance (step/jump detection + correlation with error counters).
  Why: TSN/PTP can fail “silently” when timing jumps but link stays up.
  Pass: Timestamp step ≤ X; PTP offset drift ≤ X; latency spike ≤ X under defined disturbance level.
• Check: Recovery behavior is audited (auto-negotiation retry, watchdog policy, brownout handling).
  Why: Many EMC failures appear as recovery storms rather than a single drop.
  Pass: Recovery does not amplify disturbance; no oscillation; “self-recover ≤ X ms” is met.
• Check: A/B validation recipe exists (shield bond change, return shorting, reroute, isolation reference swap).
  Why: Controlled A/B is the fastest route from symptom to coupling path.
  Pass: Each hypothesis has an A/B test that changes only one coupling variable and yields a clear measurable delta.
• Check: Port “forensics pack” is enabled (error counters + temp/voltage + event timestamps).
  Why: Field EMC issues require black-box evidence to avoid guesswork.
  Pass: Logs include: voltage rail min/max, thermal, link state machine, error histograms, and reset root-cause flags.
• Check: Reference BOM options are validated early for EMC deltas (at least 2 ESD clamps and 2 magnetics choices).
  Why: Vendor swaps can shift parasitics and CM spectra even with “same footprint”.
  Pass: A controlled “swap matrix” exists with before/after EMC deltas; acceptance thresholds are X.
• Check: Pre-compliance test scripts are automated and repeatable.
  Why: Repeatability is the foundation of regression control.
  Pass: The same script reproduces results within X dB / X% across runs and operators.

• Check: Production sampling plan includes EMC-sensitive variants (cable class, shield termination, PoE class).
  Why: EMC robustness often collapses at worst-case combinations.
  Pass: Sampling covers defined corners; failure rate ≤ X; trend charts exist per corner.
• Check: Incoming inspection checks EMC-critical parasitics for swappable parts (TVS/magnetics/connector).
  Why: “Same part number, different lot” can shift capacitance and CM response.
  Pass: A quick-screen method exists; parts outside the X window are quarantined.
• Check: Field firmware keeps robust logging enabled with rate limits (no log storms).
  Why: The most valuable EMC evidence is captured during rare events.
  Pass: Logs are retained and bounded; event summaries are preserved with timestamps and counters.
• Check: Drift monitoring focuses on CM-related metrics (link flap rate, CRC bursts, timestamp steps).
  Why: Gradual degradation is often CM-driven (shield bond aging, corrosion, loosening).
  Pass: Alerts trigger when metrics exceed X over Y time; a triage playbook is linked.
• Check: RMA acceptance criteria is tied to measurable robustness failures, not subjective symptoms.
  Why: Consistent RMA decisions prevent random “fixes” that break compliance later.
  Pass: RMA rules cite measurable thresholds (X), required logs, and required reproduction steps.
• Check: Post-rework verification includes fast EMC regression (ESD spot-check + near-field signature).
  Why: Rework changes return paths and shield bonding unexpectedly.
  Pass: Reworked units pass the defined quick-regression suite and match baseline signature within X.
• Check: Certification alignment is maintained (no unreviewed layout/part changes after compliance lock).
  Why: Late changes invalidate compliance assumptions and increase certification risk.
  Pass: Engineering change control requires EMC sign-off with measurable deltas and pass criteria.
• Check: Golden-unit fleet is maintained for A/B comparisons across production months.
  Why: Long-term drift must be distinguishable from measurement artifacts.
  Pass: Golden units are periodically re-tested and remain within X window; anomalies trigger supplier and process review.
• Check: Known “EMC killers” are blocked by manufacturing rules (missing shield spring, wrong torque, omitted bond).
  Why: Small mechanical omissions often dominate CM radiation and immunity collapse.
  Pass: Work instructions contain explicit checks; inspection rejects non-conforming assembly.
• Check: Field update policy includes safe recovery throttles (avoid retry storms under EMI).
  Why: EMI-triggered retries can overload networks and degrade deterministic TSN behavior.
  Pass: Recovery is bounded; maximum retry rate is limited; rejoin behavior meets X.

Likely cause: latent soft damage (micro-arcing / shield contact drift) raising CM sensitivity or margin loss.

Quick check: compare pre/post-ESD trends: CRC burst rate, link retrain count, rail min, temperature; repeat a light disturbance A/B to see threshold shift.

Fix: force discharge return at the port boundary (short, chassis-referenced path); eliminate secondary discharge paths across PHY/clock zones; add drift monitoring fields.

Pass criteria: within X hours after ESD: link flap = 0; CRC ≤ X per Y minutes; timestamp step ≤ X; no increasing error trend.

Likely cause: a CM spectral peak exciting a geometry antenna (cable + shield seam/slot) at that band.

Quick check: clamp CM current and scan near-field at the failing band; A/B change shield termination or cable routing and see if the peak tracks the geometry.

Fix: reduce CM loop area and seam/slot leakage at the port entry; restore return continuity; reduce peak energy instead of shifting it into a sensitive neighbor band.

Pass criteria: failing-band peak ≤ X dBµV/m (or X dB margin); adjacent bands do not increase by more than X; link metrics remain within X.

Likely cause: time/clock victim domain disturbed (reference modulation) while PCS still meets link margin.

Quick check: correlate timestamp steps with rail min and error counters; separate “time-only” failures from link degradations using synchronized logs.

Fix: isolate time/clock routing and return from port CM; harden reference rails; keep recovery actions bounded to avoid timing storms.

Pass criteria: timestamp step ≤ X; PTP offset drift ≤ X over Y minutes; latency spike ≤ X; link flap = 0 under RI level X.

Likely cause: common-impedance coupling triggers brownout/reset and then unthrottled retries amplify instability.

Quick check: check rail min and reset-cause flags during Surge; plot retrain/retry rate and see if it saturates after the event.

Fix: add brownout guard + bounded recovery (backoff/rate limit/cooldown); separate Surge return from PHY reference impedance.

Pass criteria: recovery time ≤ X ms; retry/retrain rate ≤ X per second; link stable for Y minutes; reset count = 0 (or ≤ X if allowed).

Likely cause: shield termination geometry changed (loss of 360° contact or added pigtail loop), increasing CM antenna efficiency.

Quick check: inspect shield bond method and measure CM current; A/B swap harnesses and hold routing identical to confirm vendor-driven delta.

Fix: enforce a mechanical termination spec (360° bond, controlled seam/slot); prohibit long pigtails; lock routing/strain relief to minimize loop area.

Pass criteria: RE margin ≥ X dB across sensitive bands; harness-to-harness delta ≤ X dB; CM current RMS ≤ X under baseline load.

Likely cause: VFD switching excites CM injection on the cable and/or lifts local reference via shared return impedance.

Quick check: clamp CM current and correlate CRC bursts with VFD events; check local ground/reference movement and rail dips.

Fix: shorten/strengthen return paths, reduce loop area, improve shield bond at entry; isolate noisy power return from PHY reference domain.

Pass criteria: CRC burst ≤ X per Y seconds during VFD transitions; link flap = 0; timestamp step ≤ X; rail min stays above X.

Likely cause: full-speed operation excites a CM resonance (cable/structure) or concentrates energy into a sensitive band.

Quick check: compare CM current spectrum at both speeds; see whether the failing peak moves with rate or stays fixed (geometry resonance).

Fix: fix CM loop/slot antenna and impedance discontinuities; avoid “hiding” by slowing down if TSN latency/determinism is required.

Pass criteria: at full speed: RE ≤ X with ≥ X margin; TSN latency/jitter budget still met (latency spike ≤ X, jitter ≤ X).

Likely cause: EFT injects through shared impedance, pulling PHY reference and triggering link state machine instability.

Quick check: capture rail min/ground shift near PHY during EFT; check reset-cause and link state transitions; compare with and without shield bond A/B.

Fix: separate noisy return paths, improve local reference integrity, and bound recovery behavior; ensure EFT return does not traverse the port-to-core boundary.

Pass criteria: under EFT level X: link flap = 0; reset count = 0; CRC ≤ X; recovery time ≤ X ms.

Likely cause: cabinet installation changes shield/chassis bond and creates a larger loop area or new seams/slots.

Quick check: compare shield termination and cable path between lab vs cabinet; measure CM current and hotspot signature in both setups.

Fix: standardize cabinet bonding and routing rules (no big loops, controlled 360° contact); close seams and restore intended return paths.

Pass criteria: cabinet setup meets RE/RI at level X with ≥ X margin; link flap = 0; CRC ≤ X; timestamp step ≤ X.

Likely cause: temperature shifts contact resistance and reference/threshold margins, increasing CM sensitivity and timing drift.

Quick check: temperature sweep: track CM current, rail min, CRC, timestamp step, and link stability; inspect shield bond/contact points for resistance drift.

Fix: stabilize mechanical bonding and reference integrity; ensure time/clock domain isolation holds across temperature; enforce production drift monitoring.

Pass criteria: across -X to +X °C under RI/CI level X: CRC ≤ X; timestamp step ≤ X; offset drift ≤ X; link flap = 0.

Likely cause: more air discharges and higher peak voltages expose discontinuities in bleed/ground paths and increase secondary discharge events.

Quick check: verify continuity of the intended discharge return (bond points, fasteners, springs); compare failure rate vs humidity and identify the discharge location sensitivity.

Fix: remove return-path discontinuities; enforce robust chassis/shield bonding at the entry; prevent discharge current from crossing PHY/clock victim zones.

Pass criteria: at humidity ≤ X% and ESD level X: functional drop = 0; self-recover ≤ X ms; reset count = 0; logs complete.

Likely cause: CM current dominates emissions and immunity coupling while DM integrity still appears “good” on the scope.

Quick check: measure CM current with a clamp; A/B change only the shield bond/return continuity and confirm RE/RI track CM change, not DM eye quality.

Fix: treat CM loop + seam/slot antenna as first-order; repair return detours; enforce symmetry and controlled chassis interface at the port entry.

Pass criteria: CM current (RMS or peak) ≤ X; RE/RI meet level X with ≥ X margin; link flap = 0; timestamp step ≤ X.