Source Impedance & Matching for Instrumentation Amplifiers
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Source impedance and tiny mismatches (ΔR/ΔC) often turn common-mode interference into differential error—so “great DC CMRR” can still fail in the real world. This page shows how to model, match, protect, and verify the input network so AC CMRR and step behavior stay predictable from cable to INA.
What “Source Impedance & Matching” Really Means in INA Front-Ends
In an instrumentation amplifier (INA) front-end, “source impedance” is not just a resistor value. It is the total input impedance seen by each pin across frequency—sensor/bridge resistance, lead and connector parasitics, input RC networks, ESD/protection elements, and the INA input interface itself. Matching is therefore about controlling the imbalance between the two paths: ΔZ(f) = Z+(f) − Z−(f).
A practical definition: a 4-layer impedance stack
- Sensor / bridge intrinsic: bridge arms, sensor output resistance, inherent imbalance and drift.
- Interconnect: cable/lead resistance and inductance, connector/contact resistance, parasitic capacitance to shield/chassis.
- Protection & input RC: series protection resistors, symmetric RC filters, ESD/TVS parasitic capacitance.
- INA input interface: input capacitance and bias paths; architecture-dependent sensitivity to external impedance.
Controllable knobs vs field variables
Controllable knobs (design can lock them)
- Make Rprot and RC networks symmetric (minimize ΔR and ΔC).
- Choose protection devices with tight and matched parasitic C (avoid hidden ΔC).
- Select an architecture/input type that tolerates the expected Zsrc range (e.g., high-Z sources may require FET inputs).
- Preserve symmetry in interfaces and fixtures used for validation (avoid measurement-created mismatch).
Field variables (design must be tolerant to them)
- Cable swaps and routing changes (parasitic C and R shift).
- Bridge imbalance and temperature-driven drift (ΔR can be time-varying).
- Connector/contact variability (intermittent ΔR and nonlinear artifacts).
- Environmental coupling to shield/chassis (effective ΔC changes with handling).
Design target: reduce ΔZ(f) where it matters, then validate robustness by stressing ΔR/ΔC conditions.
Scope guard
Detailed bridge wiring/layout recipes and EMI theory are handled in their dedicated pages. This section locks the terminology and the impedance boundary only.
Why DC CMRR Can Look Great While AC CMRR Collapses
High DC CMRR in the datasheet does not guarantee high AC CMRR on a real board. In practice, AC CMRR is frequently limited by common-mode to differential-mode conversion created by impedance imbalance: when Z+(f) ≠ Z−(f), a portion of common-mode voltage becomes a differential error at the INA input.
The usual root cause: ΔZ(f) dominates the system
- DC / low frequency: mismatch is often driven by ΔR (bridge imbalance, lead resistance drift, contact variability).
- Higher frequency: mismatch is often driven earlier by ΔC (ESD/TVS capacitance differences, cable-to-shield capacitance, probe/fixture parasitics).
- Key takeaway: the INA can have excellent intrinsic CMRR, yet the front-end behaves poorly if ΔR/ΔC converts CM into DM.
A fast debug order that avoids dead ends
- Probe/fixture symmetry first: eliminate measurement-created ΔC (probe capacitance, ground leads, clip asymmetry).
- Parasitic C next: verify ESD/TVS parts, connectors, and input RC are symmetric (ΔC is a frequent early limiter).
- Then ΔR: confirm matching of series resistors and the stability of lead/contact resistance over temperature and handling.
Passing DC tests is necessary but insufficient. AC behavior must be validated in the signal band with ΔZ-aware tests.
Measurement-ready pass criteria (placeholders)
- In the required signal band, CM-to-DM gain remains below a project-defined threshold.
- For a defined CM step, the induced DM spike at the measurement node remains below a budgeted limit.
- Results remain stable under controlled ΔR/ΔC perturbations (cable handling, fixture swap, intentional mismatch).
Out of scope here: EMI theory deep-dives, detailed layout recipes, and clamp leakage modeling are handled in their dedicated pages.
The Minimal Math Model: How ΔR / ΔC Turns Common-Mode Into Differential Error
Treat the front-end as two nominally identical paths. When the two input impedances are not equal, common-mode excitation creates an in-band differential error. The goal is not a long derivation, but a workable budget handle: a frequency-dependent conversion factor from Vcm(f) to Vdm,err(f).
Minimal model assumptions (so the estimates stay valid)
- Small mismatch: ΔR ≪ R and ΔC ≪ C in the band of interest.
- Common-mode excitation: both inputs see the same injected disturbance source.
- Use in-band budgets: the model is applied over the signal bandwidth where performance matters.
- Architecture note: the exact coefficient depends on the input interface, but the dominant term still tracks ΔZ(f).
Static mismatch (ΔR): unequal CM drops become a DM error
If the two paths have different effective series resistance (R+ vs R−), common-mode currents create slightly different voltage drops. The residual becomes a differential term at the INA pins.
Budget handle (engineering estimate)
Define ΔR = R+ − R− and a representative path resistance R.
For small mismatch, Vdm,err ≈ Vcm × kR, where kR scales with ΔR/R (same order of magnitude in the band where the CM current exists).
Field behavior: ΔR often behaves like a slow variable (temperature, contact resistance, bridge imbalance drift).
Dynamic mismatch (ΔC): unequal shunting increases with frequency
Parasitic and intentional capacitances to shield/chassis/ground shunt common-mode energy. If C+ and C− differ, the shunting is unequal and the remaining CM at each pin is not the same—creating a differential error.
Frequency trend (what matters most)
Capacitive impedance drops as 1/(2πfC), so ΔC-driven imbalance usually becomes visible
earlier as frequency increases. Cable handling, probe capacitance, and ESD/TVS capacitance mismatch commonly show up as “AC CMRR collapse”.
Typical ΔC sources (names only)
ESD/TVS device capacitance • connector/fixture parasitics • cable-to-shield capacitance • asymmetric RC • probe capacitance
Convert CM-to-DM into an input-referred uV / ppm budget (5-step workflow)
- Define the band: the frequency range where the measurement must meet accuracy/CMRR targets.
- Bound Vcm(f): estimate the common-mode disturbance amplitude versus frequency for the real environment.
- Bound mismatch: set worst-case ΔR and ΔC (tolerances + assembly + cable/fixture variability).
- Compute Vdm,err(f): apply a conversion coefficient k(ΔR,ΔC,f) to obtain the induced differential term.
- Input-refer: express as µV (RMS or peak-peak as required) and ppm relative to the intended full-scale signal.
Decision signal: if the CM-to-DM budget consumes a meaningful fraction of the total error budget in-band, matching and interface strategy must be upgraded before layout is frozen.
Scope guard
This section provides the minimum CM-to-DM math needed for engineering budgets. Detailed EMI theory, clamp leakage modeling, and full architecture derivations are handled in their dedicated pages.
Architecture Sensitivity: 3-Op-Amp vs 2-Op-Amp vs PGA/Chopper (From a Source-R View)
Different INA architectures respond very differently to real-world source impedance variation. The question is not “which is best” in isolation, but how much ΔZ(f) the front-end can tolerate before common-mode turns into measurable differential error in the required band.
3-op-amp INA: typically more tolerant to mismatch
- The input interface is often less sensitive to source resistance because the front-end behavior reduces direct coupling of source-R imbalance into the differential path.
- Better default choice when cable/fixture variability is expected and ΔR/ΔC cannot be fully controlled.
- Still requires symmetric protection/RC; tolerance is not a replacement for matching.
2-op-amp INA: more sensitive to source matching
- Source resistance mismatch (ΔRs) more readily appears as an in-band differential term.
- Cost/power advantages are common in multi-channel measurement, but symmetry requirements become tighter.
- Protection devices and RC networks must be treated as part of Z+(f)/Z−(f) with matched parasitics.
PGA / switched networks and chopper inputs: Rs–RC interaction becomes visible
- Switching or sampling behavior introduces dynamic input currents that interact with Rs and RC, making mismatch show up earlier at higher frequency.
- Zero-drift performance can be excellent for DC error terms, but front-end impedance symmetry is still required to protect AC CMRR and transient behavior.
- Validation should include deliberate ΔR/ΔC stress tests, not only DC checks.
Upgrade triggers (architecture/interface should be reconsidered)
- Cable/fixture changes are frequent and results are not repeatable in-band.
- CMRR drops sharply above the required signal bandwidth, especially when handling cables or probes.
- High source impedance or multiplexing is required while preserving fast settling and robust CM step behavior.
- Protection/RC elements are mandatory but their parasitics cannot be tightly controlled without a tolerant architecture.
Scope guard
Full topology derivations and detailed internal behavior belong to the architecture pages. This section only compares source-impedance sensitivity and provides planning guidance for mismatch tolerance.
High-Z Sources: When “Bias Current × Rs” and Charge Injection Become the Dominant Error
With high-impedance sensors (electrochemistry, pH/ion probes, thin-film sensors, and other weak DC sources), the limiting mechanism often shifts away from “CMRR on paper” and toward currents and charge. Small input currents and leakage paths create large voltage errors across large Rs, and sampling/switching activity can inject charge into a node that cannot recover within the measurement window.
When FET inputs become mandatory (not “premium”, but necessary)
- Ib×Rs dominates: the voltage error created by input bias current across Rs consumes a meaningful fraction of the total error budget.
- Settling fails: the input node cannot settle within the required sampling / conversion window (common with MUX/PGA or switched inputs).
- Handling sensitivity: touching cables or humidity changes cause large shifts, indicating leakage/capacitive imbalance rather than device DC specs.
Key point: high-Z designs are constrained by bias/leakage and charge recovery first; CMRR is addressed after the node is controlled.
Required “accessories” for high-Z sources (what must be designed in)
- Protection resistor ceiling: adding large series resistance on top of a large Rs can break settling and amplify charge-injection artifacts.
- Minimum Cin (charge bucket): a controlled input capacitance can absorb switching charge and reduce node movement, if kept symmetric.
- Buffer/protection priority: when sampling disturbances exist, stabilizing the node (buffer/Cin strategy) usually comes before “stronger” clamping.
Common failure pattern
“Safer” protection networks can quietly add leakage and mismatch. In high-Z systems, those parasitics can exceed the sensor signal itself.
Three-stage strategy for high-Z front-ends
1) Control leakage paths first
Guarding/cleanliness, high-insulation connectors, humidity control, and node shielding ensure leakage does not masquerade as “sensor drift”.
2) Control input bias current next
Bias current creates a voltage across Rs and often drifts with temperature and input common-mode; the input type must match Rs.
3) Control Cin and charge injection last
Use a controlled Cin/RC interface to absorb switching charge and maintain repeatable settling; keep symmetry to avoid ΔC-driven CM-to-DM conversion.
Verification hooks and pass criteria (placeholders)
- Leakage sensitivity: controlled humidity/handling causes drift below a budgeted limit.
- Settling: after a defined disturbance (MUX step, CM step, or sampling phase), the node error falls below a budgeted threshold within the required time.
- Charge-injection stress: switching artifacts remain below a defined amplitude and do not create slow recovery tails.
Scope guard
Leakage modeling details and clamp leakage budgeting are covered in the dedicated “Input Clamp & Leakage Budgeting” page. Sensor physics and application specifics are handled in their application pages.
Protection Resistors Done Right: Noise, CMRR, Settling, and Input Clamp Interaction
A protection resistor is not “free safety”. It trades survivability for noise, settling, bandwidth/phase behavior, and CMRR robustness. The correct value is found by a constrained workflow: set a minimum from protection limits, set a maximum from noise/settling, then lock symmetry so ΔR/ΔC does not create CM-to-DM conversion.
Two benefits (why series protection resistors exist)
- Peak current limiting during ESD/surge/abuse events to keep input structures and clamps within safe operating limits.
- Staged protection with clamps/TVS so energy is dissipated in controlled places rather than inside sensitive inputs.
Four costs (what series resistance can break)
- Thermal noise: higher R increases input-referred noise density and can reduce resolution.
- Bandwidth/phase: R with Cin and parasitic C forms poles that shape transient response and stability margins.
- Settling: with ADC/PGA/switching inputs, R·C time constants can leave residual error inside the conversion window.
- CMRR risk: ΔR and ΔC around Rprot strengthen CM-to-DM conversion (ΔZ(f) grows).
Rule: protection strength can increase, but only inside the remaining noise and settling budget.
Symmetry is a hard constraint (ΔR lock-in)
The same nominal resistor value is not enough. Layout parasitics and part tolerances create ΔR/ΔC that translate common-mode into a differential error. Treat both inputs as a matched network: same value, same package, same placement style, and symmetric parasitics.
Practical lock
First meet protection and dynamic limits, then enforce symmetry so R+ and R− remain equal in the real assembly.
A selection workflow that prevents false tradeoffs
- Set Rmin from protection: limit peak current into clamps/inputs for the required stress cases.
- Set Rmax from noise and settling: keep thermal noise and conversion-window residual below budget.
- Verify in-band CMRR robustness: ensure ΔZ(f) does not create a CM-to-DM term above the allowed limit.
- Lock symmetry: matched parts + symmetric parasitics so ΔR/ΔC remains controlled in production.
If Rmin exceeds Rmax, the protection topology or the input interface must be upgraded (not “forced” by a single compromise value).
Scope guard
Detailed TVS/clamp part selection and immunity standards are handled in the Protection pages. This section focuses on the series resistor’s multi-domain impact and a repeatable value-selection workflow.
Matching Playbook: ΔR Matching, Symmetric RC, and “Don’t Create ΔC by Accident”
Real-world CMRR is protected by impedance symmetry. The goal is to keep the two input paths equal as a function of frequency: Z+(f) ≈ Z−(f). This playbook focuses on the practical actions that prevent common-mode energy from turning into differential error through ΔR and ΔC.
ΔR matching (treat it as system impedance, not a BOM value)
- Same package and same network: matched resistor arrays reduce ΔR created by temperature gradients and assembly variation.
- Same tempco and same thermal environment: ΔR(T) is often dominated by local heating, not initial tolerance.
- Same “contact quality”: connectors, terminal blocks, and fixture contacts can create asymmetric series resistance drift.
- Cable resistance changes: treat cable/contact variation as a source of ΔR and design the interface so it does not become a differential series imbalance.
Rule: if two paths do not share the same thermal and mechanical conditions, ΔR will be created over time even when nominal values match.
ΔC matching (the most common cause of “AC CMRR collapse”)
ΔC is easy to create accidentally because it comes from geometry and parasitics. Once present, it reduces CMRR earlier as frequency increases. Treat every “to-shield/to-chassis/to-ground” capacitance as part of the matching problem.
- Connector and terminal parasitics often differ between pins and layouts.
- ESD/TVS capacitance and placement asymmetry can hard-code ΔC on the PCB.
- Probe and fixture capacitance can dominate “measured CMRR” even when the board is fine.
- Cable-to-shield capacitance changes with bending and proximity to metal; asymmetry turns that into ΔC.
Symmetric RC rules (filtering without creating ΔZ)
Differential-symmetric RC
Prefer matched R and matched C on both inputs so Z+(f) and Z−(f) track across frequency.
Common-mode shunts to a reference
If capacitors go to chassis/ground, their effective reference must be the same for both sides to avoid accidental ΔC.
Focus: RC choices must preserve symmetry first; filtering goals are applied inside the remaining symmetry margin.
Verification playbook (simple tests that reveal ΔR / ΔC)
- Swap test: swap inputs or cable pair—if the error follows the swap, the dominant issue is external ΔZ.
- Probe sensitivity: change probe/fixture or move the cable—large AC changes indicate ΔC is dominating the measurement.
- Intentional ΔC stress: add a small capacitor on one side to quantify sensitivity and validate the model’s direction.
Pass criteria (placeholders)
Under swap, handling, and fixture variations, the in-band CM-to-DM error stays below a budgeted limit and does not create slow recovery tails.
Scope guard
Layout/return-path implementation belongs to “Layout & Grounding”. EMI mechanisms and compliance-oriented filtering belong to “RFI/EMI-Hardened Input”. This section focuses only on matching and CMRR robustness.
When to Buffer, When to Use an INA, When to Use an FDA (Decision Tree by Rs and Dynamics)
Front-end choice should be driven by three inputs: source impedance level, required bandwidth/step dynamics, and common-mode change speed. The decision below provides a repeatable path to the right interface without expanding into full ADC/AAF topology design.
Decision variables (keep them measurable)
- Rs level: whether bias/leakage and charge recovery are first-order constraints.
- BW / dynamics: whether step response and settling time are part of the specification.
- CM change speed: whether common-mode makes fast steps that require recovery robustness.
- Power budget: whether the design is constrained by Iq and thermal limits.
Typical landing zones (why each path exists)
High Rs → buffer-first strategy
Prioritize FET input behavior and controlled Cin so bias/leakage and charge injection do not dominate.
Medium Rs → 3-op-amp INA default
Often provides robust mismatch tolerance and stable in-band behavior under real wiring variability.
Low Rs + fast dynamics → high-speed INA or FDA chain
Drive capability and recovery dominate; FDA + differential chain is common when bandwidth and linearity are primary.
Common wrong turns (signals that the interface is mismatched)
- High Rs combined with switched inputs (MUX/PGA/ADC sampling) without a buffer-first strategy → slow settling and charge artifacts.
- Low Rs high-speed signals routed through a low-drive interface → distortion, recovery tails, or apparent “noise” that is actually settling error.
- Protection/RC increased to “fix stability” → accidental ΔC/ΔZ created, reducing in-band CMRR.
- Fast CM steps judged only by DC CMRR → field failure when CM recovery dominates.
Verification hooks (placeholders)
- Step settling: after a defined step, residual error stays below a budgeted limit within the conversion window.
- CM step recovery: after a common-mode step, differential residue and recovery time remain within budget.
- Cable/fixture sensitivity: swapping probes/fixtures and moving cables does not create unacceptable in-band variation.
Scope guard
Detailed ADC drive and anti-alias filter topology selection is handled in “ADC Drive & Anti-Alias Filtering”. This section focuses only on the front-end interface choice and the required verification hooks.
Application Patterns (Only from the Source-Impedance Angle)
These patterns reuse one template: CM energy becomes DM error whenever Z+(f) ≠ Z−(f). The goal is to identify which real-world impedances create ΔR or ΔC and to apply matching actions without expanding into full system design.
Pattern A — Bridge weighing / pressure: bridge imbalance + cable resistance drift
Trigger
The two input paths see different series resistance over time because cable/contact resistance and bridge imbalance do not change symmetrically.
Impedance error path
ΔRs creates unequal common-mode drops → CM-to-DM conversion rises, especially as frequency increases and parasitics join the network.
Matching action: keep both input paths inside the same impedance “envelope” (same network, same thermal conditions, symmetric protection/RC).
Quick verification
Swap the cable pair or swap INA inputs. If the error follows the swap, external ΔZ dominates and matching must move outward (cable/connector/fixture).
Pattern B — High-side shunt: fast common-mode steps + asymmetric RC/parasitics
Trigger
The common-mode voltage makes fast edges. Any ΔC from ESD, connectors, probes, or cable-to-shield coupling becomes a differential transient.
Impedance error path
CM step → unequal shunt paths through Z+(f)/Z−(f) → DM spike and recovery tail. This is often unrelated to DC CMRR.
Matching action: make RC symmetric first; treat ESD/connector/probe parasitics as ΔC components that must be matched or neutralized.
Quick verification
Repeat the same CM edge with different probes/fixtures. Large variation indicates measurement/cabling ΔC is dominating CM-to-DM conversion.
Pattern C — High-Z electrochemistry: Ib×Rs + input capacitance + sampling disturbance
Trigger
Source impedance is high enough that bias/leakage currents and charge injection define the dominant error and settling behavior.
Impedance error path
Ib×Rs becomes a direct offset term; Cin and switching disturbance create recovery tails that limit usable resolution and repeatability.
Matching action: control leakage paths and bias first, then keep parasitic capacitance symmetric and predictable across both inputs.
Quick verification
Vary sample timing or switching activity. If the reading shifts or takes long to recover, charge disturbance and high-Z settling dominate.
Scope guard
Full system designs belong to the Bridge / Shunt / High-Z application pages. This section only maps the error path from source impedance mismatch to CM-to-DM conversion.
Verification Hooks: How to Measure CM-to-DM Conversion and Prove Matching Works
Matching is real only when it is measurable. Verification should include two categories: common-mode injection (sweep and step) and source-impedance perturbation (intentional ΔR/ΔC and cable/fixture sensitivity).
What to measure (two observables)
CM→DM transfer vs frequency
Apply a controlled common-mode stimulus to both inputs and measure residual differential output across the application band.
DM spike and recovery (CM step)
A fast CM edge can create a DM transient when ΔC or ΔZ exists. Measure peak and recovery tail, not only the DC number.
Rule: good DC CMRR does not prove anything about in-band matching; verification must include the relevant frequency region for the application.
Two test types (repeatable and low ambiguity)
Common-mode injection
- Use a symmetric coupling network so the injection itself does not create ΔZ.
- Run a sweep for “shape” and a step for peak/recovery.
- Measure differentially to avoid grounding artifacts.
Source-impedance perturbation
- Insert a small ΔR in only one input path to quantify sensitivity.
- Insert a small ΔC in only one input path to emulate connector/ESD/probe parasitics.
- Move cables and change fixtures to expose real-world ΔC variation.
Quick triage (fast diagnosis without long debates)
- DC looks perfect but AC fails: suspect ΔC from fixtures, ESD/TVS, connectors, and cable-to-shield coupling before blaming the silicon.
- Cable movement sensitivity: a strong sign of ΔC and termination asymmetry. Confirm by switching probe/fixture and repeating the same CM stimulus.
- Results change with the measurement setup: treat the measurement chain as the primary suspect until proven otherwise.
Production-friendly minimal version (field names, not a full schema)
A simplified line test can still catch matching failures by fixing the stimulus and recording a few derived metrics.
- cm2dm_gain_dB@f1 — CM→DM magnitude at a selected band point
- dm_spike_mV — peak DM transient under a defined CM step
- recovery_time_ms — time to return within a defined residual band
- swap_delta — change after input/cable swap (external ΔZ indicator)
- fixture_sensitivity_flag — indicates strong probe/fixture dependency
Goal: fixed stimulus + fixed pass criteria + automated binning, without relying on “good-looking DC numbers”.
Scope guard
Production reporting, detailed binning, and feedback loops belong to the production-reporting page. This section only defines verification hooks and minimal measurement metrics to prove CM-to-DM robustness.
Engineering Checklist (Design Review in 15 Minutes)
A source-impedance-first review that prevents CM-to-DM conversion and keeps AC CMRR from collapsing due to accidental ΔR/ΔC. Scope is strictly impedance + matching (no layout deep-dive, no EMI theory).
A) ΔR control (resistance mismatch)
- ☐ Keep input series resistors as a matched pair (same value, same package, same vendor lot when possible). Treat them as “gain-critical” for AC CMRR.
- ☐ Prefer resistor arrays / networks when ratios matter (shared substrate improves tracking). If discrete resistors must be used, enforce identical footprint + symmetric placement to reduce thermal gradients.
- ☐ If the sensor wiring can change (lead resistance drift, connector aging), isolate that variation from the INA input by keeping front-end impedance symmetry intact (do not “fix” one side only).
B) ΔC control (capacitance mismatch)
- ☐ Treat “invisible capacitance” as first-class: ESD diode C, connector parasitics, cable type, probe capacitance, and unequal ground-coupling can dominate AC CMRR.
- ☐ If adding input RC filtering, build it as a matched differential pair (R+ = R−, C+ = C−). Avoid “one-sided” fixes that create ΔC.
- ☐ Ensure both inputs see the same ESD topology and the same copper environment (do not place an ESD part on only one input).
C) Series protection resistors (Rseries) — set bounds, then lock symmetry
Costs to budget (4)
Thermal noise · bandwidth/phase shift · settling impact (ADC/PGA drive) · ΔC amplification via R×C mismatch.
Benefits (2)
Input current limiting · staged protection cooperation (ESD/TVS/clamps) without overstressing the INA pins.
Selection flow (do in this order)
- Set minimum by surge/ESD limit current requirement.
- Set maximum by noise + settling + bandwidth targets.
- Freeze the value as a matched pair and protect symmetry throughout the PCB + harness.
D) High-Z sources: bias return + leakage sanity check
- ☐ Confirm a defined input bias return path exists for both inputs (no floating bias condition under all mux/gain states).
- ☐ Ensure “protection” parts do not dominate: input clamp leakage × Rs can create a DC error larger than the signal.
- ☐ If sampling or switching exists downstream (PGA/ADC), check that input capacitance and charge injection do not pull the high-Z node into long settling tails.
E) Verification hooks (prove matching works)
Test 1 · Common-mode injection
Sweep or step common-mode, then measure differential output. Require pass criteria in the band that matters (kHz+ often reveals ΔC issues).
Test 2 · Source-impedance perturbation
Intentionally add small ΔR/ΔC or move the cable/probe; quantify CM-to-DM sensitivity instead of “looks stable”.
Production-friendly variant
Fix injection conditions + thresholds; record binning fields (DM spike, recovery time, AC CMRR spot checks) for consistent screening.
IC Selection Logic (Fields → Risk Mapping → Vendor Questions)
Selection for this page is not “best INA.” It is best match to source impedance + ΔR/ΔC risk. Use fields to expose hidden sensitivity, then ask vendors for missing conditions before committing.
A) Must-have fields (collect these before comparing parts)
Input interaction
- Input bias current (max over temperature) + input leakage conditions.
- Input capacitance (per input pin, differential/common-mode if provided).
- Input protection structure and allowed input current during faults.
CMRR that matters
- AC CMRR vs frequency at the intended gain.
- Test conditions for CMRR (source impedance, balancing network, frequency range).
- Overload / common-mode step recovery (time + output behavior).
Integration constraints
- Input CM range across supply and temperature (near-rail linearity matters).
- Recommended input RC / Rseries ranges (stability + settling guidance).
- Noise metrics (wideband density + 0.1–10 Hz) aligned to the sensor bandwidth.
B) Risk mapping (tie the source to the failure mode)
High-Z source (kΩ → MΩ+)
Dominant risks: Ib×Rs, clamp leakage, Cin/charge injection → long settling tails.
Preferred traits: FET / ultra-low Ib, defined bias return, controlled input protection leakage.
AC CMRR critical (long leads / mismatch risk)
Dominant risks: accidental ΔC (ESD/connector/cable/probe) and R×C mismatch.
Preferred traits: strong AC CMRR characterization + predictable behavior with symmetric input RC.
Fast CM steps (shunt / switching systems)
Dominant risks: common-mode recovery, transient CM→DM spikes amplified by ΔR/ΔC.
Preferred traits: fast recovery specs, stable input network guidance, validated AC CMRR under dynamic conditions.
C) Vendor questions (extract the missing conditions)
- • Provide AC CMRR test setup: source impedance per input, balancing method, gain, and sweep range.
- • Provide input capacitance details (per pin, typical/max, measurement condition). Confirm behavior with external symmetric RC.
- • Provide overload recovery after a defined common-mode step (magnitude, edge rate, load, REF pin condition).
- • Provide input bias current max vs temperature and any dependency on input protection conduction or input fault current.
- • Provide recommended Rseries/Cin ranges and any stability/settling constraints when driving an ADC/PGA front-end.
D) Reference part numbers (starting points only; verify fields above)
These are examples to speed up datasheet comparison for source-impedance sensitivity. Final selection must be driven by worst-case conditions, matching strategy, and verification results.
General-purpose 3-op-amp INA (balanced Rs, strong baseline)
TI: INA826, INA828
ADI: AD8221, AD8220
ADI: AD8221, AD8220
Zero-drift / chopper INA (DC error + low-freq stability)
TI: INA333, INA188
ADI: AD8237
ADI: AD8237
High-speed / fast recovery focus (dynamic CM environments)
ADI: AD8421, AD8429
High-Z / electrometry-leaning (Ib dominates)
TI: INA121 (FET input), INA116 (ultra-low Ib; legacy / check alternates)
ADI: AD8220 (JFET input)
ADI: AD8220 (JFET input)
Digitally programmable gain (watch switching interaction with Rs/Cin)
TI: PGA281
ADI: AD8250, AD8251
ADI: AD8250, AD8251
High common-mode option (difference amplifiers; integrated matching matters)
TI: INA149, INA148
ADI: AD629
ADI: AD629
E) Matching & protection BOM helpers (keep symmetry)
Matched resistor arrays (ΔR control)
Vishay: ACAS 0606 AT / ACAS 0612 AT (thin-film array families with relative tolerance / tracking)
Example MPN: ACASA1100S2200P5AT (illustrates matched-pair concept; choose values per protection/noise bounds).
Example MPN: ACASA1100S2200P5AT (illustrates matched-pair concept; choose values per protection/noise bounds).
C0G/NP0 capacitors (ΔC control)
Murata: GRM1885C1H101JA01D (100 pF, C0G, 0603) — use matched pair for symmetric RC.
ESD diodes (place symmetrically; watch capacitance)
TI: TPD1E05U06 (low-cap ESD family; pick channels/variants as needed)
Nexperia: PESD5V0S1UL (single-line ESD diode; confirm capacitance/leakage vs bandwidth needs).
Nexperia: PESD5V0S1UL (single-line ESD diode; confirm capacitance/leakage vs bandwidth needs).
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FAQs: Source Impedance & Matching (CM-to-DM Control)
Short, actionable answers that stay strictly within source impedance, ΔR/ΔC matching, and CM→DM conversion. Each answer uses the same 4-line structure for engineering execution and verification.
