HDMI / DisplayPort Tx/Rx Redriver & Retimer (HDCP/EDID, Compliance)
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This page helps HDMI/DisplayPort links stay stable at high data rates by turning “black screen / flicker / snow / training & HDCP/EDID failures” into actionable, measurable steps—budget the channel, pick redriver vs retimer, and verify with pass/fail criteria.
It focuses on extension/repair/retiming scenarios across Main Link/TMDS/FRL and control-plane (HPD, DDC/AUX), so teams can debug faster and lock production using logged fields and threshold-based acceptance.
Definition & Page Boundary (HDMI/DP Tx/Rx Redriver/Retimer)
- Extend HDMI/DP links with redriver/retimer placement and practical EQ/retiming rules.
- Debug HDCP/EDID/HPD (and DP AUX) failures that masquerade as “signal integrity”.
- Build an evidence chain for eye/jitter compliance and bring-up readiness.
- USB-C Type-C/PD/Alt-Mode policy and port controller flows (link out only).
- General CDR/equalization theory or math derivations (reference to the CDR/EQ hub page).
- ESD/TVS fundamentals; only placement and parasitic impact relevant to HDMI/DP links.
Definitions (HDMI/DP-specific, engineering-facing)
- Role: reshape channel loss with gain/CTLE/FFE (no clock recovery).
- Best when: loss is moderate and jitter is mostly ISI-driven.
- Trap: “bigger eye” can still worsen BER if noise is amplified or EQ is over-peaked.
- Role: recover clock/data and re-launch, breaking jitter/noise accumulation.
- Best when: loss is high, channel is harsh (dock/backplane), or jitter must be re-timed.
- Trap: lock/re-lock behavior and latency can trigger visible “blink” and control-plane re-auth cycles.
- Repeater is ambiguous in vendor docs; in this page it must resolve to redriver or retimer.
- Mux/Switch changes loss/return-loss and may impact HDCP/EDID/HPD/AUX transparency.
- Trap: control-plane faults can look like SI faults; triage starts with HPD/EDID/AUX before eye tuning.
- HDMI TMDS/FRL + DP Main Link extension using redriver/retimer.
- Control-plane robustness: HDCP/EDID/HPD and DP AUX pass-through/debug.
- Practical EQ/retiming knobs tied to eye/jitter and margin evidence.
- Bring-up/compliance proof: test points, de-embed plan, logs and pass criteria (threshold placeholders).
- USB-C port policy, PD negotiation, and Alt-Mode discovery state machines.
- Generic CDR math, equalizer derivations, or SERDES training theory beyond actionable knobs.
- Full protocol spec commentary; only engineering checks that affect link stability and compliance.
- Standalone ESD/TVS selection theory (only parasitic impact + placement here).
- USB-C / Type-C & Bridges (dock-focused system pages).
- CDR / Retimer & Equalization (generic knobs and measurement artifacts).
- High-speed ESD/TVS arrays + CM chokes (parasitics, placement, matching).
- Protocol bridges & format conversion (if HDMI↔DP or HDMI↔MIPI conversion exists).
Minimum verification loop (do not skip)
Identify/handshake succeeds: EDID readable, training completes (DP), HDCP stable (if enabled), no repeated hotplug cycles.
Target mode holds across cable variance and temperature. Record negotiated rate/lane, error counters, and drop events (thresholds: TBD).
Measurement setup is reproducible (reference plane + de-embed plan). Save eye/jitter artifacts and logs as evidence for reviews.
System Topologies & Where the Problem Appears
Topology determines whether failures are driven by main-link margin, link training (DP), or control-plane (HDCP/EDID/HPD/AUX). Fast triage prevents “eye tuning” from being applied to EDID/AUX problems.
- Only fails at higher modes; lower modes are stable.
- Sensitive to cable length, temperature, or connector batch.
- First check: negotiated mode + error counters (thresholds: TBD).
- Training repeats; final state drops to a lower rate/lane count.
- AUX/DPCD readbacks show retries or timeouts.
- First check: training log + DPCD status snapshots (fields: TBD).
- EDID read fails or HDCP re-auth loops even at low modes.
- Hot-plug changes the outcome; “replug fixes it”.
- First check: HPD bounce + EDID success rate + HDCP retries (thresholds: TBD).
First 5 probes / logs (fastest to differentiate root cause)
- HPD event log: count + timestamps; flag any bounce or repeated toggles (pass: TBD).
- EDID/AUX success rate: retry count, timeout rate (pass: TBD).
- Negotiated mode snapshot: HDMI mode or DP rate/lane count; record any downshift.
- Error counters: CRC/BER-like indicators where available; correlate with temperature and cable ID.
- Training/handshake trace: DP training steps or HDCP auth phases; store for regression comparisons.
Topology gallery (trigger → failure mode → first check → fix hint)
- Trigger: high modes compress margin; small layout defects become dominant.
- Failure: only top mode fails; lower mode is clean.
- First check: negotiated mode + repeatability across temperature.
- Fix hint: prefer layout/return-loss cleanup; redriver only if loss is the limiter.
- Trigger: insertion loss + cable variance; EMI/ESD exposure increases.
- Failure: snow/sparkles or intermittent dropouts; “one cable works”.
- First check: cable ID vs error trend; mode downshift behavior.
- Fix hint: redriver for moderate loss; retimer if loss is high or jitter accumulates.
- Trigger: stacked connectors/vias create return-loss and reflection hotspots.
- Failure: DP training loops; rare drops after warm-up.
- First check: AUX/DPCD stability and reference-plane correctness.
- Fix hint: retimer is common; verify control-plane transparency before tuning EQ.
- Trigger: mux/switch adds loss and can destabilize HPD/EDID/HDCP timing.
- Failure: hot-plug dependent; HDCP/EDID failures dominate.
- First check: HPD bounce + EDID read success + HDCP re-auth count.
- Fix hint: stabilize control-plane first; then address main-link margin.
Link Basics You Must Not Get Wrong (HDMI vs DP)
Before selecting a redriver or retimer, identify the main high-speed bundle and the control-plane. Control-plane instability (EDID/HDCP/HPD/AUX) can look like “signal integrity” but requires a different first fix.
- TMDS: clock/data relationship is explicit; mode downshift often stabilizes quickly.
- FRL: higher bandwidth compresses margin; connector/via/cable variance becomes dominant.
- Control-plane: DDC + HPD (+ HDCP phase). If these flap, do not start with EQ.
- Main Link: rate and lane count define high-speed stress and EQ demand.
- Training: repeats/downshift are direct margin signals; logs are first-class evidence.
- AUX/HPD: sideband failures frequently present as training failures.
- If EDID/HDCP/HPD/AUX is unstable, treat it as control-plane first.
- DP training downshift is a margin signal; capture the negotiated state.
- Higher modes compress eye/jitter budget; topology variance becomes visible.
Rate / lanes / control-plane cheat sheet (verify per spec)
| Mode family | Main-link bundle | Device-choice drivers | Control-plane to not forget | Typical failure signature |
|---|---|---|---|---|
| HDMI · TMDS |
TMDS lanes + clock (verify per spec) |
Loss window, EQ range, connector/via RL sensitivity | DDC (I²C), HPD, HDCP phase stability | High-mode fails, low-mode stable; cable length sensitive |
| HDMI · FRL |
Multi-lane high-speed bundle (verify per spec) |
Higher stress → tighter eye/jitter margin; redriver window narrows; retimer may be needed | HPD + HDCP re-auth sensitivity; DDC stability across hot-plug | Top mode fails; intermittent blink; “eye looks bigger but BER worsens” if EQ is over-peaked |
| DP · Main Link |
Lane count + link rate (verify per spec) |
Training outcome, EQ/retiming strategy, channel loss and RL hotspots | AUX + HPD must be reliable; DPCD reads are first debug evidence | Training loops or downshift; AUX timeouts masquerade as SI failures |
| DP · AUX (sideband) |
Not a high-speed lane (verify per spec) |
Pass-through integrity, ESD/EMI robustness, timing margin for handshakes | AUX retries/timeouts drive training instability | “Only replug works”; training never converges until AUX stabilizes |
Note: values and exact lane definitions vary by revision; treat this table as a selection and debugging structure, and verify details per the applicable HDMI/DP specifications.
Channel Loss & Eye Closure: Budgeting the Link
Link extension succeeds when the channel budget is quantified. The goal is to separate loss-driven eye closure from control-plane instability and to prevent measurement artifacts from producing false “improvements”.
- Effect: high-frequency attenuation shrinks vertical opening.
- Signature: top modes fail first; cable length sensitive.
- Leverage: EQ window and placement; retimer if loss is beyond linear repair.
- Effect: ringing and pattern-dependent errors.
- Signature: certain cables/connectors are always “bad”.
- Leverage: connector/via cleanup; avoid stubs; verify reference plane.
- Effect: BER degrades even if the eye “looks fine”.
- Signature: worsens with nearby aggressors or power noise.
- Leverage: spacing/return paths; filtering; avoid over-peaked EQ that amplifies noise.
- Effect: localized reflection + common-mode conversion.
- Signature: EMI increases; sporadic failures after integration.
- Leverage: backdrill/stackup choices; placement discipline around connectors.
Link budget template (copy/paste structure)
| Item | Value / placeholder | Evidence / measurement plan | Pass criteria |
|---|---|---|---|
| Target mode (rate / lanes) | TBD (verify per spec) | Negotiated state snapshot; training logs if DP | No downshift; no drops (TBD) |
| Allowable loss window (IL/RL) | IL@fN: TBD, RL: TBD | Reference plane + de-embed plan (TBD) | Meets mask/jitter limits (TBD) |
| Segment contributions (waterfall) | Conn A: TBD · Cable: TBD · Conn B: TBD · PCB/vias: TBD | VNA/S-params or fixture plan (TBD) | Segment limits met (TBD) |
| Margin reserve (variance) | Cable batch: TBD · Temperature: TBD · Process: TBD | Multi-cable + temp sweep logs | No failures across sweep (TBD) |
| Control-plane stability (must be clean) | EDID/AUX success: TBD · HPD bounce: TBD · HDCP retries: TBD | Event counts + timestamps | Stable handshake (TBD) |
Measurement traps (false “improvements” to eliminate)
Eye/jitter looks “better” after moving the reference plane or changing fixture settings.
Re-run with the same plane + same de-embed file; compare to a known-good cable/fixture baseline.
Lock measurement settings; document the reference plane; treat the de-embed plan as part of the spec.
Same DUT + different fixtures converge within agreed correlation limits (TBD), and results are reproducible.
Redriver vs Retimer: Decision Rules
A redriver is a linear channel conditioner (gain/CTLE/FFE) that improves eye shape but does not recover the clock. A retimer uses CDR + re-transmit to re-time the stream and reduce channel-related jitter transfer, at the cost of added latency and re-lock behavior.
- Channel loss is within a linear EQ window (budget margin remains).
- Failures track with loss slope, not with re-lock events.
- System latency budget is tight; re-lock must be avoided.
- Loss/ISI is beyond what linear EQ can recover reliably across variance.
- Jitter/BER strongly correlates with channel segments and connectors.
- A clean re-timed hop is needed for long cables or multi-hop topologies.
- DP: negotiated rate/lane, training attempts, downshift counts (TBD).
- HDMI: HPD bounce, EDID read success, HDCP retry counts (TBD).
- Across cables: batch-to-batch variance and temperature sweep stability.
Side-by-side comparison (selection impact)
| Dimension | Redriver (linear) | Retimer (CDR + re-TX) | What it means for selection |
|---|---|---|---|
| Clock recovery | No (passes jitter) | Yes (re-times) | If channel-driven jitter dominates, retimer can cut transfer (TBD limits). |
| EQ range | Limited by linear stability / noise gain | Wider tolerance across loss/ISI variance | If the budget waterfall shows “dominant loss segment”, retimer is more robust. |
| Latency | Minimal | Added (TBD) | If UI/UX switching is sensitive, budget latency + re-lock time explicitly. |
| Re-lock behavior | None (no CDR) | Present (lock time TBD) | Hot-plug / power events may look like “blink”; lock robustness must be verified. |
| Protocol transparency | Often simpler pass-through | Must verify handshake/training behavior | Confirm EDID/HDCP (HDMI) and AUX/training (DP) are stable through the hop. |
Keep the decision evidence close to the selection: negotiated states, retry counts, and variance sweeps are often more predictive than a single eye capture.
Decision flow (evidence-driven)
- Control-plane stable? (EDID/HDCP/HPD for HDMI; AUX/HPD/DPCD for DP) → If not, fix control-plane first.
- Is channel loss beyond the linear EQ window? → If yes, retimer is favored.
- Is BER/jitter strongly correlated with channel segments? → If yes, retimer can cut transfer.
- Must pass training/HDCP transparently? → Verify hop behavior before committing.
- Can latency + re-lock time be tolerated? → If not, redriver is preferred.
Equalization & Retiming Knobs (CTLE/FFE/DFE/Peaking/Loop BW)
Treat knobs as a diagnostic tool, not as a tuning ritual. The same eye can hide very different BER outcomes. The table below maps each knob to typical symptoms, safe fix direction, and placeholder pass criteria.
- CTLE peaking: compensates HF loss, but can amplify noise.
- Gain/slope: improves vertical opening; watch noise gain.
- FFE taps: shapes precursor/postcursor ISI (device-specific).
- CDR loop BW: trades jitter filtering vs tracking ability.
- Lock time: impacts blink behavior on events (TBD).
- Jitter transfer: verify with the target channel variance.
- Over-EQ: eye grows but BER worsens (noise gain / overshoot).
- Under-EQ: high modes fail first; training downshifts.
- Wrong loop BW: stable on bench, drops in system events.
Knob → symptom → fix direction → pass criteria (TBD)
| Knob | Symptom (field) | Fix direction (safe) | Pass criteria (placeholder) |
|---|---|---|---|
| CTLE peaking | High mode fails; DP downshift; “snow” at top resolution | Increase gradually until margin improves; stop if noise artifacts rise | No downshift; stable image; error counters flat (TBD) |
| Gain / slope | Eye height low; link marginal across cables | Raise gain cautiously; validate BER (do not trust eye alone) | BER meets target; no intermittent blinks (TBD) |
| FFE taps | Pattern-dependent errors; sensitivity to cable type | Adjust taps to reduce ISI; re-check across variance set | Stable across cable batch + temperature sweep (TBD) |
| Over-EQ indicator | Eye looks larger but BER worsens; overshoot/EMI grows | Reduce peaking/gain; prioritize BER and stability over “pretty” eyes | Error counters improve; EMI artifacts do not regress (TBD) |
| CDR loop BW | Stable on bench, drops in system events; periodic unlocks | If unlocks track events, widen tracking; if noise dominates, tighten filtering (device-specific) | No unlocks; negotiated state stays fixed (TBD) |
HDCP / EDID / HPD / AUX/DDC: Control-Plane That Breaks the Link
Many “main-link” failures are actually control-plane instability. Before touching EQ or retiming, verify the presence and stability of 5V/HPD, the integrity of DDC/EDID (HDMI), and the reliability of AUX/DPCD transactions (DisplayPort).
Troubleshooting priority (control-plane first)
- Power presence: HDMI 5V present and stable (no drops, no bounce).
- HPD stability: HPD asserted cleanly; count bounce events (TBD) across hot-plug and motion.
- DDC/EDID (HDMI): EDID read succeeds consistently; track ACK/retry/timeout (TBD).
- AUX/DPCD (DP): no AUX timeout; DPCD reads/writes are reliable during training.
- Main link last: only after the above are stable, tune EQ/retiming and evaluate eye/jitter.
- EDID read fails: no ACK / timeout; often looks like “no signal”.
- EDID read wrong: intermittent capability mismatch; unstable modes.
- Hot-plug sensitive: depends on HPD/5V timing window.
- Log: EDID success rate, retry count, and timeout count (TBD fields).
- Verify pull-ups and ESD capacitance do not slow edges excessively (TBD).
- If long DDC wiring exists, consider a dedicated buffer/switch (HDMI-only scope).
- HPD bounce → re-auth: short dips can trigger repeated auth.
- Sideband handling: verify pass-through behavior through switch/retimer.
- Symptom fingerprint: stable at low mode, fails at high mode (TBD).
- AUX timeout: training loops and downshifts mimic main-link issues.
- DPCD reads/writes: errors often correlate with ESD/cap load (TBD).
- Priority: if training repeats, confirm AUX/HPD before EQ tuning.
Compliance: Eye / Jitter / Mask & Test Setups (CTS/ATC Thinking)
“The system works” is not the same as “the link is compliant.” Compliance requires repeatable measurements, consistent reference planes, and evidence packages that survive cross-lab correlation.
Turn specs into steps (setup-first)
- Pick the reference plane: define where “compliance” is evaluated (connector / fixture / coupon) (TBD).
- Describe fixture & interconnect: fixture type, cable, adapters, and exact stack-up.
- De-embed responsibly: specify model source and confirm before/after sanity checks.
- Lock down key settings: trigger/clock recovery, RBW/VBW, and CTLE preset consistency.
- Build an evidence pack: screenshots + report fields + training logs for repeatability.
- Reference plane drift: results become incomparable across runs.
- De-embed mismatch: “improvement” can be a modeling artifact.
- Preset inconsistency: CTLE/receiver presets change mask outcome.
- RBW/VBW: can reshape apparent jitter/noise (settings artifact).
- Trigger/CR: wrong recovery hides real failures.
- Preset/CTLE: must match the compliance target profile.
- Eye: mask hit status, sweep conditions, preset ID (TBD).
- Jitter: RJ/DJ summary, RBW/VBW, CR mode (TBD).
- Logs: training attempts, downshifts, AUX/DDC counters (TBD).
Board Design & Layout: Return Current, Vias, Connectors, ESD/EMI
For HDMI/DP, link margin is often lost at the connector launch, via transitions, and protection placement. The most common “bench OK, system fails” pattern is caused by return-path discontinuity, stubs/reflections, or parasitics from ESD/CM components.
- Impedance: match the stackup target (TBD) and keep geometry stable through launch.
- Length symmetry: control skew, but never sacrifice return-path continuity to chase perfect length.
- Reference continuity: avoid crossing split planes; provide a nearby return bridge at layer changes.
- Stubs: long via stubs create notches and reflections; mitigate with backdrill (TBD).
- Via fence: add ground via stitching around the launch to keep return currents local.
- Fanout: keep the first centimeters clean—no sudden width/spacing jumps, no sharp bends.
- Place near the connector: keep branch length minimal to avoid loading the main link.
- Parasitic C: excessive capacitance closes the eye and can break training at high modes.
- Matching: imbalance converts differential to common-mode → EMI up, margin down.
- Correlate events: flicker/downshift aligned with load/fan/USB changes suggests supply coupling.
- Probe near the IC: check Tx/retimer rails at the pins (TBD bandwidth/probe method).
- Avoid artifacts: poor probing makes ground-bounce look like rail noise.
Layout acceptance checklist (HDMI/DP-focused)
| Item | Why it breaks links | Quick check | Fix action | Pass criteria |
|---|---|---|---|---|
| Return path continuity | Forces current detours → common-mode + EMI + jitter | No plane split crossings under main link | Add return bridges / re-route to continuous reference | TBD (layout review sign-off) |
| Via stub control | Creates reflection notches at high modes | Identify long stubs at connector/retimer transitions | Backdrill / shorten / avoid unused via barrels | TBD (eye/margin stable) |
| Connector launch symmetry | Mode conversion and impedance steps collapse eye | Launch region is short, symmetric, and fenced | Tight geometry control + ground stitching | TBD (training stable across cables) |
| ESD / CM placement | Parasitic C loads the link; mismatch drives EMI | Placed near connector; branch length minimal | Move closer, reduce branch, choose lower C (TBD) | TBD (mask/jitter margin) |
| Rail noise correlation | Supply ripple modulates analog front-end/PLL → jitter | Event time aligns with rail noise bursts (TBD) | Decoupling/filters/layout return fixes before EQ rework | TBD (repeatable across load/thermal) |
Bring-up & Debug Playbook (Symptom → Probe → Fix → Pass)
Debug faster by enforcing a strict layer order: Power/HPD → EDID/AUX → Training → Main link eye/jitter. Each symptom below is mapped to a minimal probe set, a fix action, and a pass criterion (TBD thresholds).
Debug ladder (always in this order)
- Power / HPD: HPD bounce count (TBD), 5V present stability.
- EDID (HDMI) / AUX+DPCD (DP): success rate, timeout counters.
- Training / Negotiation: attempts, downshift events, relock loops.
- Main link: eye/mask margin and jitter evidence, then EQ/retiming knobs.
H2-11 · Engineering Checklist (design → bring-up → production)
This checklist is optimized for HDMI/DisplayPort link extension and repair using redrivers/retimers/switch-with-EQ. Every line is written as a doable action with acceptance placeholders and record-field placeholders to enable repeatable engineering and production gating.
-
Freeze the target mode set (HDMI TMDS vs FRL; DP RBR/HBR/HBR2/HBR3) and map them to a “worst-case” channel condition.
Accept: [Target modes pass] · Log:
MODE_SET, MAX_RATE, LANE_COUNT -
Choose the “first-fix component class” by the link-budget boundary:
If loss/margin is moderate → Redriver; if jitter accumulation / clock recovery needed → Retimer; if multi-source routing is required → Switch-with-EQ.
Accept: [Class locked] · Log:
FIX_CLASS, LOSS_EST_DB, JITTER_SUSPECT -
Lock placement order at the connector (recommended): Connector → ESD/TVS → (optional CM choke) → Redriver/Retimer → SoC/PHY.
Accept: [No stubs, return path continuous] · Log:
PLACEMENT_SEQ, RETURN_PATH_OK -
Control-plane integrity rule: HPD + DDC/AUX must be treated as “first-class” links (ESD choice + pull-ups + routing) before touching Main Link/TMDS/FRL EQ.
Accept: [No HPD bounce / no DDC/AUX timeouts] · Log:
HPD_EVENTS, DDC_ERR, AUX_ERR -
Pre-select “known-good reference parts” for schematic bring-up (examples; verify package/speed/availability):
Accept: [Ref-BOM frozen] · Log:HDMI redriver / retimer examples• TMDS1204 / TDP1204 (HDMI 2.1 FRL-capable redriver family)
• TMDS181 (HDMI 2.0 TMDS retimer), TMDS171 (HDMI 1.4b TMDS retimer)
• IT66313 / IT66319 (HDMI 2.1 retimer family; retiming buffer)DP redriver / retimer examples• TDP142 (DP 1.4 HBR3 linear redriver; AUX/HPD-aware)
• ANX7496 / ANX7497 (DP 1.4 retimer family)
• PS8461 / PS8461E (DP mux + retimer class device)
• PI3DPX1207C / PI3DPX1207B1 (DP1.4 linear redriver class)Control-plane + protection examples• TPD12S016 (HDMI companion: DDC level shifting + load switch + ESD)
• TPD4E05U06 / TPD4E05U06-Q1 (ultra-low-C ESD arrays)
• RClamp0524P (low-capacitance TVS array class)
• DLW21SN261XQ2L (Murata DLW21 series common-mode choke example)REF_BOM_REV, IC_PN_LIST, ESD_PN_LIST, CMC_PN_LIST
-
Control-plane first gate: verify HPD stability + EDID read + DP AUX transactions before tuning any EQ knob.
Accept: [0 unexpected HPD toggles] · Log:
HPD_TOGGLE_CNT, EDID_RD_OK, AUX_TXN_OK -
Preset/EQ sweep with evidence: sweep CTLE/FFE (redriver) or loop/EQ presets (retimer) and record “pass window”, not just “one lucky setting”.
Accept: [Pass window exists] · Log:
PRESET_ID, CTLE_DB, FFE_TAPS, PASS_WINDOW -
Corner capture plan: temperature + supply ± corners must be included early (video links are “almost pass” by default).
Accept: [All corners meet criteria] · Log:
TEMP_C, VDD_V, LINK_RATE, TRAIN_RESULT -
Measurement hygiene: record fixture + reference plane + de-embed settings as immutable metadata (avoid “fake improvement”).
Accept: [Settings reproducible] · Log:
FIXTURE_ID, REF_PLANE, DEEMBED_FILE, RBW_VBW
-
Golden cable set: qualify multiple cables/lengths/vendors and freeze a golden set for line correlation.
Accept: [Golden set defined] · Log:
CABLE_VENDOR, CABLE_LEN, GOLDEN_SET_ID -
Line quick-screen: use a short test script that exercises (1) HPD/EDID or AUX/DPCD, then (2) a worst-case link rate.
Accept: [0 retries beyond threshold] · Log:
EDID_RETRY_CNT, AUX_RETRY_CNT, LINK_UP_TIME_MS -
Fixture-to-system mismatch guard: if fixture passes but system fails, log the control-plane waveforms (HPD/DDC/AUX) before touching the main-link tuning.
Accept: [Correlation documented] · Log:
STATION_ID, FIXTURE_REV, SYSTEM_FAIL_SIG -
Incoming control-plane components (ESD/CMC) must be version-locked; small C changes can destroy eye margin.
Accept: [AVL locked] · Log:
AVL_REV, ESD_PN, CMC_PN
H2-12 · Applications & IC Selection Notes (HDMI/DP)
Applications are presented as scenario cards. Selection notes are presented as requirement → check → part examples. Part numbers are concrete starting points; always verify the exact data-rate mode, package, and compliance constraints.
- Link trait: loss grows with length; worst-case cable dominates margin.
- Common pitfall: main link “almost OK” but EDID/HPD/AUX becomes intermittent due to ESD and weak pull-ups.
- Recommended architecture: connector-side protection + (sink-side) redriver/retimer close to the receiver.
-
Example parts (pick by mode):
• HDMI FRL redriver: TMDS1204 / TDP1204
• HDMI TMDS retimer (legacy TMDS): TMDS181 (6G) / TMDS171 (3.4G)
• DP 1.4 redriver: TDP142 (AUX/HPD-aware)
• Protection: TPD4E05U06 or RClamp0524P (choose by capacitance/standard)
- Link trait: routing introduces discontinuities; “good at one config” is not sufficient.
- Common pitfall: a switch/mux changes insertion loss and return loss, breaking training stability.
- Recommended architecture: mux-with-equalization or mux + redriver/retimer, with preset sweep evidence.
-
Example parts:
• DP mux + retimer class: PS8461 / PS8461E
• DP linear redriver class: PI3DPX1207C / PI3DPX1207B1
• HDMI 2-port switch (1080p-class): TMDS261B
• HDMI port companion (DDC/5V/ESD): TPD12S016
- Link trait: HPD toggles are common; EDID/HDCP can repeatedly re-run.
- Common pitfall: HPD bounce or DDC/AUX corruption triggers re-authentication loops that look like “random black screen”.
- Recommended architecture: harden HPD/DDC/AUX, then stabilize main link with a right-class EQ/retiming stage.
-
Example parts:
• HDMI control-plane + ESD: TPD12S016
• HDMI FRL redriver: TMDS1204 / TDP1204
• ESD arrays for control lines: TPD4E05U06 (or automotive TPD4E05U06-Q1)
- Link trait: ground noise and common-mode coupling can translate into jitter at the analog front-end.
- Common pitfall: “works on bench” but fails in system due to ESD/CM filtering choices and return current breaks.
- Recommended architecture: connector-first protection, controlled CM strategy, and an EQ/retiming stage placed to minimize stubs.
-
Example parts:
• ESD arrays: TPD4E05U06 / TPD4E05U06-Q1, RClamp0524P
• CM choke example: DLW21SN261XQ2L (select by insertion loss / skew impact)
• DP redriver: TDP142
- Check: supported signaling mode (TMDS/FRL or DP HBRx) + EQ range vs expected insertion loss.
- Check: additive jitter/noise behavior and whether “bigger eye” can still worsen BER (over-EQ risk).
- Check: whether AUX/HPD/DDC are passed/managed correctly (don’t assume).
- Examples: TMDS1204 / TDP1204 (HDMI 2.1 redriver), TDP142 (DP 1.4 redriver), PI3DPX1207C / PI3DPX1207B1 (DP redriver class)
- Check: re-lock time and behavior during hot-plug or training retries.
- Check: latency budget impact (system-level tolerance differs by product).
- Check: control-plane transparency (HDCP/EDID timing, AUX/DPCD access).
- Examples: ANX7496 / ANX7497 (DP retimer family), TMDS181 / TMDS171 (HDMI TMDS retimer family), IT66313 / IT66319 (HDMI 2.1 retimer family)
- Check: routing-dependent discontinuities (each path is a different channel).
- Check: whether the device changes return loss enough to destabilize training.
- Check: AUX/DDC/HPD handling across the switching event.
- Examples: PS8461 / PS8461E (DP mux + retimer class), TMDS261B (HDMI/DVI 2:1 mux with adaptive EQ; use within its speed class)
- Trap: selecting by “max data rate” but ignoring loss compensation range.
- Trap: fixing main link first while HPD/DDC/AUX is unstable (it will re-break the link).
- Trap: over-EQ makes eye look larger yet increases BER (noise amplification / ringing).
- Trap: production yield collapses due to cable vendor/connector variation (no golden set / no correlation).
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H2-13 · FAQs (HDMI/DP redriver/retimer) — troubleshooting only
Each answer is intentionally short and executable. Every item follows the same 4-line structure and uses measurable fields with threshold placeholders (X/Y/Z) so it can be gated in bring-up and production.
MODE_SET,
LINK_RATE,
LANE_COUNT,
TRAIN_RETRY_CNT,
DOWNGRADE_EVENTS,
HPD_TOGGLE_CNT,
EDID_OK_RATE,
AUX_TIMEOUT_CNT,
HDCP_REAUTH_CNT,
RELOCK_TIME_MS,
CABLE_SET_ID,
TEMP_C,
VDD_MV.
Low resolution is stable, but high resolution goes black — budget first or HDCP/training first?
DOWNGRADE_EVENTS, TRAIN_RETRY_CNT, HDCP_REAUTH_CNT at the failing mode (MODE_SET).DOWNGRADE_EVENTS ≤ X, HDCP_REAUTH_CNT ≤ X, LINK_UP_TIME_MS ≤ Y (TBD).After adding a redriver the eye looks larger, but snow/flicker happens more often — noise or over-EQ?
CTLE_DB, FFE_TAPS, PRESET_ID).PASS_WINDOW ≥ X presets, FLICKER_EVENTS = 0 over T ≥ Y min (TBD).DP keeps repeating link training and finally downshifts to a lower rate — AUX first or Main Link first?
LINK_RATE, or AUX/DPCD transactions are unreliable (timeouts/ESD damage).AUX_TIMEOUT_CNT indicates AUX; repeated TRAIN_RETRY_CNT with low AUX timeouts indicates Main Link.AUX_TIMEOUT_CNT ≤ X, TRAIN_RETRY_CNT ≤ Y, DOWNGRADE_EVENTS = 0 (TBD).Hot-plug sometimes fails — how to capture HPD bounce, and what “pass” looks like?
HPD_TOGGLE_CNT, HPD_BOUNCE_MAX_MS) and correlate with HDCP_REAUTH_CNT/TRAIN_RETRY_CNT.HPD_TOGGLE_CNT ≤ X per plug, HPD_BOUNCE_MAX_MS ≤ Y, LINK_UP_TIME_MS ≤ Z (TBD).EDID is intermittently unreadable — how to quickly validate DDC pull-ups / cable length / buffering?
EDID_RETRY_CNT, EDID_OK_RATE) and measure DDC rise time at the connector (DDC_RISE_TIME_NS).EDID_OK_RATE ≥ 99.9%, EDID_RETRY_CNT ≤ X, DDC_RISE_TIME_NS ≤ Y (TBD).HDCP authentication intermittently fails — how to localize transparency issues vs re-lock triggers?
HPD_TOGGLE_CNT and RELOCK_EVENTS; track HDCP_REAUTH_CNT per hour.HDCP_REAUTH_CNT ≤ X per hour, RELOCK_EVENTS ≤ Y, HPD_TOGGLE_CNT ≤ Z (TBD).A cable swap makes it pass/fail — how to build a cable-consistency screen (golden set)?
CABLE_SET_ID, CABLE_VENDOR_ID, CABLE_LEN_M) while logging DOWNGRADE_EVENTS/TRAIN_RETRY_CNT.GOLDEN_SET_ID: DOWNGRADE_EVENTS = 0, TRAIN_RETRY_CNT ≤ X (TBD).The system works, but compliance fails — how to debug reference plane / de-embed / setup traps?
REF_PLANE_ID, DEEMBED_MODEL_ID, FIXTURE_ID, RBW_VBW.COMPLIANCE_MASK_PASS = true and metadata complete: REF_PLANE_ID/DEEMBED_MODEL_ID present (TBD).EMI fails but functionality is OK — where do CM choke / ESD capacitance trade-offs usually break the link?
ESD_PN, CMC_PN, PLACEMENT_DISTANCE_MM.PASS_WINDOW ≥ X presets, DOWNGRADE_EVENTS = 0 (TBD).After temperature rises the link starts flickering — where is the first probe point for “power noise → jitter”?
TEMP_C/VDD_MV and measure ripple at the device supply pins (not at a distant rail point): RAIL_RIPPLE_MVPP.FLICKER_EVENTS = 0 over T ≥ X min at TEMP_C corners; RAIL_RIPPLE_MVPP ≤ Y (TBD).Retimer occasionally re-locks and the picture “jumps” — how to evaluate loop behavior vs configuration?
RELOCK_EVENTS, RELOCK_TIME_MS) per mode (MODE_SET) and per cable (CABLE_SET_ID).RELOCK_EVENTS ≤ X per hour, RELOCK_TIME_MS ≤ Y, no visible jump events over T ≥ Z min (TBD).In a multi-output distribution, one output is worse — how to separate reflection/return-loss vs connector batch issues?
PATH_ID, CONNECTOR_BATCH_ID) and compare TRAIN_RETRY_CNT/DOWNGRADE_EVENTS.DOWNGRADE_EVENTS = 0, TRAIN_RETRY_CNT ≤ X, and no path-specific fail (TBD).