An industrial Ethernet slave/master controller is the real-time engine above MAC/PHY and below the host CPU/SoC that hardens deterministic behavior: it implements dual-port forwarding (line/ring topologies), hardware timestamp capture and timebase discipline, process-data staging (process image / DPRAM), and diagnostic hooks that keep control cycles predictable across load, topology changes, and production variance.

• Forwarding path control: predictable per-node added delay (fast path vs buffered path) and bounded queueing under load.
• Topology visibility: port role/state, link-change timestamps, and ring/line recovery evidence for root-cause analysis.
• Diagnostics-first behavior: counters and watermarks that correlate burst jitter and stalls to congestion or recovery state transitions.

• Capture-point consistency: ingress/egress timestamp locations must be consistent across ports and test setups to avoid “same DUT, different topology → different accuracy”.
• Timebase discipline: time correction, drift control, and restart behavior must be observable (logs/counters), not assumed.
• Budgetable residuals: quantization + capture point + queueing + discipline residuals should roll up into a measurable p99 offset/jitter target.
• Control consequence: sync instability manifests as sampling-phase variance, which translates to output noise or oscillation risk in tight servo loops.

• Determinism accounting templates (latency/jitter decomposition with pass criteria placeholders).
• Dual-port forwarding behavior checklist (fast path vs buffered, queueing, recovery evidence).
• Timestamp capture-point validation checklist (ingress/egress correlation and station-to-station alignment).
• Process-image/DMA/IRQ realism notes (how host contention becomes cycle jitter).
• Bring-up → production hooks (what to log and how to gate pass/fail).

• Ethernet PHY / Magnetics: signal integrity, EEE, magnetics selection → Ethernet PHY
• TSN Switch/Bridge: 802.1AS/Qbv/Qbu scheduling and switching fabric → TSN Switch / Bridge
• Protection (ESD/Surge/EMI): IEC paths, TVS/CM chokes → Protection & Test

• PHY/MAC: electrical signaling and frame I/O (linked out for details).
• Controller core: deterministic forwarding, timestamp capture, timebase discipline, process-data staging, and diagnostic evidence.
• Host/CPU: configuration, application logic, firmware update, logging, and non-real-time services.

• Fast path (forwarding): port RX → forwarding engine → port TX. Goal: bounded and predictable latency/jitter, minimally impacted by host load.
• Host path (process/config): port RX → process image/DPRAM → DMA/IRQ → host CPU → application. Goal: consistent process-data semantics, diagnostics, and maintainability.

Engineering rule: if real-time behavior depends on host-path timing, the design must prove bounded jitter under worst-case host load.

• Capture-point mismatch: verify ingress/egress timestamp points are identical across ports and testers.
• Queueing variance: log queue watermarks and classify stalls as congestion vs recovery states.
• DMA/IRQ contention: correlate cycle jitter bursts with host interrupts, DMA bursts, and memory bandwidth saturation.
• Restart phase jumps: check timebase initialization and latch phase after warm reset (offset “step” behavior).

Protocol software stacks, configuration tooling, and full TSN scheduling details are intentionally excluded here. This section is strictly about system placement and deterministic data paths.

• Cycle window: the repeat interval that defines control-loop phase and allowable latency budget.
• Process-data window: the reserved portion where real-time I/O must be consistent and bounded.
• Async/acyclic window: background traffic (diagnostics/parameters) that must not steal determinism margin.
• Synchronization residual: remaining offset/jitter after time discipline; this is what shows up as sampling-phase variance.

Engineering rule: comparisons are only meaningful if the same cycle definition, capture points, and statistics (p50/p99 + burst duration) are used.

• On-the-fly data path: forwarding is coupled to in-flight processing, turning “per-node added delay” into a measurable hop contribution.
• Sync impact chain: timebase discipline → cycle boundary alignment → process-data commit phase → control-loop sampling phase.
• Common determinism breakers: queueing variance under load, recovery-state transitions, and inconsistent timestamp capture points across setups.

• RT vs IRT concept: determinism comes from how strictly a predictable process-data window is protected inside each cycle.
• Window ownership: background traffic is allowed only if it cannot violate the reserved process-data phase.
• Common determinism breakers: uncontrolled async traffic, station-to-station measurement mismatch, and recovery behavior that shifts cycle phase.

Scope guard: details of switching fabrics and TSN scheduling belong to the TSN Switch/Bridge page; this section stays at timing-model level.

• Cyclic phase discipline: the value is in stable phase relationships between communication cycles and process-data update points.
• Jitter translation: residual sync error becomes sampling-phase variation, which directly affects high-bandwidth motion control stability.
• Common determinism breakers: phase jumps after warm resets, topology changes that alter hop delays, and hidden queueing variance.

Message formats, object dictionaries, configuration tooling, and full TSN scheduling are intentionally excluded here. This section only covers timing-model concepts that determine cycle and jitter behavior.

• 2× MAC ports: dual-port designs serve line/ring topologies and enable per-hop delay accounting.
• Forwarding modes: cut-through (lowest latency) vs store-and-forward (buffered integrity) must be measurable and selectable by policy.
• Queue visibility: watermarks and drop/throttle behavior must be observable to classify burst jitter as congestion vs recovery.

• Clock domain control: defines timestamp stability and restart behavior across temperature and brownout.
• Timestamp unit: capture points (ingress/egress) must be explicit and consistent across ports.
• Sync timer: anchors cycle boundaries and provides the reference for process-data commit phase.

• Process data staging: separates real-time semantics from host timing noise.
• Mailbox/acyclic channel: isolates non-critical traffic and prevents determinism window violations.
• Buffering discipline: size headroom and commit phase are part of the determinism budget (not optional details).

• Interfaces (category view): SPI/QSPI, parallel bus, PCIe, and other high-throughput links (no vendor naming).
• IRQ latency budget: p99 interrupt latency must be bounded under worst-case host load.
• DMA burst shaping: burst size and coalescing settings must be chosen to avoid cycle-phase drift.

• Counters: CRC/error counters, queue watermarks, offset alarms, restart events.
• Error capture: “last fault snapshot” fields to correlate failures with timebase/queue/recovery states.
• Watchdog + safe-state pins: deterministic fault containment for field reliability and compliance narratives.

End-to-end determinism margin is consumed by fixed latency (cycle margin) and variable latency (jitter/bursts). A practical budget splits the path into measurable segments with consistent capture points.

Scope guard: PHY implementation details belong to the Ethernet PHY page; this section only keeps them as named budget items.

Engineering rule: averages are insufficient; determinism validation must use p99 and burst duration under defined load and topology.

Repeatability requirement: lock node count (N), payload (X bytes), background rules, and statistics window length before comparing runs.

Detailed PHY behavior, protection components, and TSN scheduling mechanisms are intentionally excluded. This budget focuses on measurable end-to-end delay and jitter accounting for controller-based forwarding systems.

• Ingress vs egress: the capture boundary must be specified (before/after queues) and kept identical across ports.
• Comparability: results must remain consistent across testers and fixtures; otherwise “good offset” numbers are not transferable.
• Queue separation: capture strategy must allow distinguishing queueing delay from timebase residuals.

• Local clock stability: drift and warm-reset behavior must be characterized, not assumed.
• Temperature sensitivity: drift across temperature must be measured and budgeted (ppm placeholder).
• Phase jumps: brownout/restart should be tested for phase discontinuities that masquerade as “random jitter.”

• Update interval: controls how quickly residual offset can be corrected under drift and disturbances.
• Filtering: must be selected to avoid slow settling while keeping noise bounded.
• Burst errors: disturbances should trigger bounded re-lock behavior with measurable settle time.

802.1AS and TSN scheduling (Qbv/Qbu) are intentionally excluded here. They belong to the TSN Switch/Bridge topic page; this section focuses on HW timestamp guarantees that remain valid regardless of TSN policy.

Full-frame validation completes late in the receive path, so deterministic behavior under errors depends on the controller’s mode and policy. When error counters rise, a robust design must prove whether forwarding stays bounded or transitions to a defined containment mode.

Flow-control events can introduce hidden tail latency and head-of-line blocking. Determinism validation must confirm whether cycle traffic remains bounded when backpressure triggers.

TSN scheduling details and full protocol specifications are intentionally excluded. This section focuses on controller forwarding behavior, queueing principles, and explicit congestion/flow-control checkpoints.

• Trigger: which fault or power condition engages bypass, and what evidence confirms engagement?
• Delay impact: does bypass introduce additional variable delay that affects cycle budgets?
• Failure modes: define what happens if bypass fails (alarm and safe-state behavior).

Full MRP/HSR/PRP mechanisms are intentionally excluded. This section only lists controller-level hooks and the measurable questions required to bound recovery time and determinism impact.

The process image is a memory-mapped view of cyclic inputs and outputs. Determinism depends on coherent snapshots: the host must not read a mixed-state image that spans different cycle phases.

Mailbox traffic carries non-cyclic functions (configuration, diagnostics, and service operations). It must be contained so bursts cannot inflate cyclic p99 delay or disturb host update phase.

Host interface choice changes transaction granularity, interrupt rate, DMA burst behavior, and bus contention. Determinism requires the interface to support bounded copy time and stable update phase.

Object dictionaries, detailed message formats, and configuration tooling are intentionally excluded. This section focuses on coherent process images and host-side DMA/IRQ behavior that affects determinism.

• Clocking: define reference source, domain boundaries, and cycle phase anchor.
• Power: bound ripple/transients; verify ground return paths for noisy cabinets.
• Reset & straps: deterministic boot state for port roles and safe-state behavior.
• Host bandwidth: interface sustains process-image copies inside update window.
• Thermal: verify junction margins at target load with realistic airflow.

• Link establishment: role/port mapping correct; no unexpected flaps.
• Timestamp sanity: ingress/egress capture points consistent across ports.
• Cycle stability: measure p99 jitter and burst duration at steady load.
• Isolation quick test: enable background traffic; prove p99 remains bounded.
• Snapshots: log offsets, error rates, watermarks at event entry.

• Station correlation: same DUT across stations/cables/switch peers yields consistent metrics.
• Logging schema: firmware version, temperature, supply, offsets, jitter, CRC/sec, watermark.
• Threshold decisions: define re-test rules and gray-zone handling (bounded retries).
• Yield guard: detect drift via environment fields (temp/humidity/supply) before blaming silicon.

• Error rate counters: CRC/sec, drop/throttle/alarm events with timestamps.
• Last desync snapshot: record offset/jitter + port state at the moment of loss.
• Port visibility: optional mirror/trace hooks for correlation and root-cause capture.
• Recovery timeline: detect → isolate → recover → settle timestamps for audits.

Motion control (drives/servos/synchronous I/O)

• Primary requirement: cycle-to-cycle determinism so control loops see a stable update cadence (no bursty delivery).
• Controller focus: bounded per-hop forwarding delay, stable queueing under load, and a predictable “update window.”
• Diagnostics focus: capture “last desync snapshot” (offset, port state, CRC rate) to correlate timing alarms with network events.

Modular remote I/O (distributed sensors/actuators)

• Primary requirement: stable process-image coherency (inputs/outputs latched per cycle) as node count increases.
• Controller focus: deterministic handling of background traffic (acyclic/diagnostic) without stealing time from cyclic I/O.
• Field reality: error counters (CRC/sec, link flap) must be easy to log and threshold in production tests.

Robotics / factory cell (multi-axis sync + fast root-cause)

• Primary requirement: tight sync domain (timestamp consistency + stable timebase discipline).
• Controller focus: bounded re-lock time after disturbance and explicit port-state visibility for maintenance workflows.
• Operational focus: deterministic recovery targets (in cycles/ms), not “eventually recovers.”

Gateway / bridge (role boundary only)

Slave/Master controllers are often used as deterministic “edges” around a control domain. This page only covers role-driven constraints: cycle timing, dual-port forwarding behavior, and diagnostic artifacts (not protocol translation details).

• Master-side need: coherent scheduling/logging (timestamps + counters) and consistent cycle generation.
• Slave-side need: stable process-image exchange and bounded forwarding latency in line/ring topologies.
• Hard rule: keep deterministic traffic isolated from opportunistic traffic (acyclic/config/diagnostics).

Application sizing placeholders (fill-in for requirements)

• Node count (in the same sync domain): X
• Update rate / cycle time: X µs … X ms (add p99 jitter ≤ X)
• Topology constraint: line / ring; max segment length X; recovery target X ms / X cycles

1) Protocol support & certification artifacts

• Single-protocol vs multi-protocol: is one hardware platform required to cover multiple product lines?
• Conformance evidence: provide artifacts (reports, versioned logs, test IDs) required by the target ecosystem.
• Role boundary: IO-Device/Slave vs Controller/Master expectations (cycle control + diagnostics).

2) Timing: timestamp resolution, offset stability, re-lock

• Timestamp capture consistency: ingress/egress points must be defined and repeatable.
• Stability: specify p99 offset (with a stated measurement window) and worst-case re-lock after disturbance.
• Timebase drift: quantify ppm across temperature and define calibration/discipline method (high level only).

3) Switching: cut-through, buffering, queues, congestion behavior

• Cut-through vs store-and-forward: define when the device degrades to buffered mode (CRC, errors, policy).
• Worst-case queueing delay under load: provide a bound, not “typical.”
• Loss strategy under overload: drop vs throttle vs alarm; require thresholds.

4) Host interface: bandwidth, drivers, update determinism

• Host BW must fit within the cycle update window (process image + mailbox overhead).
• IRQ/DMA behavior must be predictable (coalescing options; fixed-phase update strategy).
• Driver/SDK maturity matters more than raw peak BW for production maintainability.

5) Robustness (keep metrics here; details linked out)

• Temperature grade: X (industrial/extended).
• EMI/ESD/surge strategy: specify targets, then link to protection/TVS/magnetics pages for implementation details.
• Field diagnostics: require error counters and “last failure snapshot” visibility.

6) Package & thermal (board-level reality)

• Thermal resistance target: θJA ≤ X °C/W (or define allowed junction rise at X load).
• Heat path plan: copper + vias + airflow; define acceptance at ambient X °C.
• Production: thermal margin must be validated under worst-case background traffic.

Hard thresholds (copy/paste into PRD)

• Timestamp resolution ≤ X ns (define capture point: ingress/egress)
• p99 sync offset ≤ X ns (measurement window: X s, steady-state)
• Per-hop added latency (p99) ≤ X ns (background load: X% line rate)
• Worst-case queueing delay ≤ X µs (define overload scenario)
• Host BW ≥ X MB/s (must complete within cycle update window)
• Re-lock time ≤ X ms after disturbance (or ≤ X cycles)
• Production diagnostics: CRC/sec ≤ X; link flap = 0 in X min; snapshot present

Concrete material numbers (reference examples; verify suffix/package/availability)

These examples are widely used Industrial Ethernet controller/ASIC references for deterministic slave/master designs. Some devices integrate PHY/switch functions; selection should still follow the hard-threshold checklist above.

• EtherCAT slave controllers (ESC): LAN9252, LAN9253-I/R4X, LAN9255-I/ZMX018 (Microchip). :contentReference[oaicite:0]{index=0}
• EtherCAT ASIC ESC: ET1100, ET1200-0000-NNNN (Beckhoff). :contentReference[oaicite:1]{index=1}
• PROFINET IO ASIC (2-port switch class): 6ES7195-0BH02-0XA0 (Siemens ERTEC 200P Step 2). :contentReference[oaicite:2]{index=2}
• Industrial Ethernet communication controller (accelerator-style): MC-10287BF1-HN4-M1-A (Renesas R-IN32M3-EC). :contentReference[oaicite:3]{index=3}
• Multiprotocol Industrial Ethernet controller SoCs (fieldbus + Real-Time Ethernet class): NETX 90 (2270.100 / 2270.200 / 2270.300 / 2270.400), NETX 52 (2232.001) (Hilscher). :contentReference[oaicite:4]{index=4}

Recommended topics you might also need

• Ethernet PHY (10/100/1G/2.5G/TSN)
• TSN Switch / Bridge
• Industrial Protocol SoC/Bridge
• Loopback / PRBS / BIST
• Compliance Hooks