Profibus DP/PA & FF H1 PHY: Coupling, Isolation, Timing
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This page distills PROFIBUS-DP/PA and FOUNDATION Fieldbus H1 (MBP) PHY into actionable engineering blocks: topology/termination, coupling + isolation boundaries, and timing-compliance checks that stay measurable from schematic to production.
Use it to build stable links (even with powered buses and harsh field noise) by following clear test points, pass/fail criteria, and a troubleshooting path that never drifts into protocol-layer details.
Scope & quick map: what “DP / PA / FF-H1 PHY” actually means
This page is strictly the physical layer.
It focuses on PHY blocks, coupling & isolation boundaries, and timing / waveform compliance. Protocol stack topics (configuration, function blocks, scheduling, object models, fieldbus engineering tools) are out of scope.
What this page delivers
- A buildable PHY map (DP vs PA/FF-H1) with clean boundary definitions.
- A coupling + isolation mental model: where DC power flows, where AC data lives, and where noise sneaks in.
- A compliance method: how to translate “strict timing” into measurable fields and pass criteria (thresholds as X placeholders).
- A bring-up & troubleshooting path based on test points and controlled A/B comparisons.
Quick scenario selector (pick the closest)
DP (RS-485 PHY)
Typical break: termination / biasing / common-mode stress.
First measurement: end-node waveform + reflection vs topology changes.
PA (MBP 31.25 kbps)
Typical break: power ripple injected into data via coupling network.
First measurement: bus ripple + data waveform at coupler output.
FF-H1 (MBP 31.25 kbps)
Typical break: group delay / filtering that violates waveform templates.
First measurement: waveform template margins across temperature & cable.
DP↔PA coupler / linking device
Typical break: isolation delay / power-domain noise / coupling mismatch.
First measurement: A/B compare across isolation boundary (delay + CM noise).
Why 31.25 kbps MBP vs 1.5 Mbit DP behaves like a different universe
- Data rides on power (MBP): DC injection and AC coupling share the same two wires, so supply ripple and coupling impedance shape the data waveform directly.
- Template-driven compliance: “it communicates” is not proof—waveform templates / timing windows define pass/fail; margins shrink with cable length and spur topology.
- Isolation is a stability boundary: field common-mode stress and ground potential differences turn into receiver errors unless the isolation + return paths are engineered explicitly.
- Topology dominates physics: trunk/spur reflections and attenuation often dwarf “silicon quality”; fixing topology/termination beats swapping PHY parts.
Physical layer building blocks: the buildable modules (and what must be measurable)
A stable fieldbus PHY is not “a transceiver + a cable”. It is a chain of modules where each module must map to a measurable symptom and a controlled fix. The following breakdown keeps the design implementable, testable, and production-repeatable.
Mandatory measurement nodes (TP1 / TP2 / TP3)
- TP1 (PHY-side): isolate silicon health — verify waveform shape before cable/topology effects dominate.
- TP2 (post-isolation/coupling): quantify boundary impact — delay, group-delay distortion, and injected ripple.
- TP3 (connector/trunk): quantify field wiring impact — reflections, attenuation, and common-mode stress under real cable runs.
DP (RS-485 PHY) — keep only Profibus-critical physics
Transceiver
Role: differential drive/receive with common-mode tolerance.
Failure shape: CM stress shifts receiver decision; “random” errors track cabinet ground events.
Measure: TP3 diff + CM simultaneously; correlate with ground potential / surge events.
Termination & bias
Role: control reflections and define a deterministic idle state.
Failure shape: clean bench behavior but field instability with cable length/spurs; ringing grows at edges.
Measure: TP3 step response / reflection signature while moving termination location (A/B comparison).
Protection & (optional) isolation
Role: discharge ESD/surge without corrupting the signal path.
Failure shape: “more protected but less margin” when capacitance/leakage reshapes edges.
Measure: TP2/TP3 waveform deltas with protection populated vs depopulated; keep pass criteria as X thresholds.
PA / FF-H1 (MBP 31.25 kbps) — powered bus + template compliance
MBP PHY
Role: modulate/demodulate on a powered line while meeting waveform templates.
Failure shape: excessive filtering or group delay makes “average” look better but reduces template margin.
Measure: TP1 vs TP2 waveform template margin; sweep temperature and cable to find the weakest corner.
Power injection / isolation
Role: deliver DC power to the trunk while preventing supply ripple from becoming data distortion.
Failure shape: periodic “wander-like” link behavior synchronized to DC/DC ripple or load transients.
Measure: bus ripple spectrum + data waveform at TP2; verify improvement with controlled ripple reduction (A/B).
Coupling L/C + damping
Role: create a clean AC data path on top of DC power; control resonance and edge-shape.
Failure shape: ringing/over-shoot under certain trunk/spur conditions; errors disappear on short cables only.
Measure: TP2 step response and settling; tune damping until overshoot < X and settling < X (placeholders).
Coupler / linking device — treat as a boundary instrument, not a black box
Isolation boundary
Role: break ground loops and survive common-mode events without destroying timing margin.
Failure shape: delay/skew drift across temperature or part swaps; “same design, different unit” behavior.
Measure: TP1↔TP2 propagation delta; log worst-case drift and keep acceptance as X (per compliance budget).
Power domains
Role: keep logic-side noise from entering the field-side coupling network (and vice-versa).
Failure shape: link errors correlate with internal DC/DC load steps; ripple moves with mode changes.
Measure: ripple at isolated rails + TP2 waveform; verify fix by changing load profile / filter (controlled test).
Diagnostic sampling points
Role: make root cause measurable; avoid “guessing by swapping”.
Failure shape: no stable correlation between symptom and action because TP nodes are missing or noisy.
Measure: ensure TP pads + ground reference; validate probe method does not distort the bus (pass as X).
Topology & termination: trunk/spur physics, reflections, and common-mode traps
Fieldbus stability is often decided by wiring geometry rather than silicon. Trunk/spur topology changes the line impedance map, which then converts into reflection, attenuation, and common-mode (CM) stress. This section stays strictly at the physical layer: topology → observable waveform signatures → corrective actions.
Trunk/spur effects (what changes on the waveform)
Reflection
Spurs create impedance discontinuities; edges launch echoes that return to the trunk. The signature is a second “step” or ringing after the main transition, growing with spur length and count.
- Probe: TP3 at an end node / connector.
- A/B: move termination to the real end; change only one spur variable.
- Pass: ringing < X, settling < X (X from compliance budget).
Attenuation
Distributed capacitance and node loading reduce amplitude and slow edges. The signature is a “soft” transition and reduced template margin that worsens with trunk length.
- Probe: TP3 at the farthest node.
- A/B: same node, change only cable length (or add a known section).
- Pass: amplitude / edge metrics above X margin (X from template).
CM noise
Shield/ground potential differences inject common-mode swings. A link can look “fine” in differential-only view yet fail as the receiver threshold shifts with CM events.
- Probe: differential + CM concurrently at TP3.
- A/B: change only shield bonding strategy; log CM delta.
- Pass: CM swing < X and error-free under stress (X budgeted).
Termination placement (why “missing termination” can be worse than “extra termination”)
- Missing termination increases reflections, often creating unpredictable edge-shape changes as spur geometry shifts. It can pass on short benches yet collapse on real trunks.
- Wrong / extra termination can overload the line and reduce amplitude, shrinking margin in a different way. Both failures are measurable at TP3.
- The fastest correlation check is a one-variable A/B experiment: keep all nodes fixed, move termination to the true end, then record the reflection signature delta at TP3.
Practical pass criteria (placeholders)
Define X from the compliance template / system noise budget, then enforce: ringing < X, settling time < X, and a stable decision window across cable and temperature corners.
DP (RS-485) vs PA/FF (MBP) — topology ties into different failure paths
- DP / RS-485: biasing and fail-safe decisions interact with CM drift. A “stable idle” requires CM-aware measurement, not only differential amplitude.
- PA/FF MBP: data is carried on a powered bus. Topology changes not only reflections but also the power-impedance map, making ripple injection and resonances more likely.
Coupling networks (PA/FF MBP): power + data on one pair, with controlled damping
MBP carries data on a powered bus. The coupling network is therefore not optional “glue”: it defines how DC power enters, how AC data passes, and how resonance is damped. The objective is to preserve waveform-template margin while preventing ripple and ground-related common-mode stress from turning into data distortion.
Three-path model (keep roles separate)
DC path
Role: inject DC power with minimal ripple coupling into the signal decision region.
Failure: errors correlate with load steps or DC/DC mode changes.
Check: measure bus ripple + TP2 waveform concurrently.
AC path
Role: pass the MBP data band without excessive group delay or edge rounding.
Failure: “smooth” looking waveforms yet reduced template margin.
Check: compare TP1 vs TP2 template margin across corners.
Damping path
Role: control resonance so overshoot and settling stay within budget.
Failure: topology-dependent ringing that appears only on real trunks.
Check: tune with one-variable A/B and enforce overshoot < X.
Knobs → symptoms (tune only one knob at a time)
- Coupling strength (C / network gain): more coupling can restore amplitude but can also increase ripple injection or slow edges; validate template margin at TP2.
- Injection inductance (L): improves isolation of supply ripple but can saturate or shift resonances; correlate ripple spectrum with errors under load steps.
- Damping (R/RC): reduces ringing and improves settling, but too much damping can reduce amplitude and erase margins; enforce overshoot/settling pass criteria (X placeholders).
“Works on bench, fails in the field” — the usual physical reasons
- Ripple path: cabinet power events and load steps modulate bus ripple; the injection network turns it into data distortion at TP2.
- Ground/CM path: shield bonding and ground potential differences inject CM swings that leak into the coupling network through parasitics.
- Topology amplification: certain spur distributions move resonances into the worst band; damping that looked “fine” on short cables becomes insufficient.
Isolation strategy: define the boundary between controller and field domains
For long cables and noisy installations, isolation is not “extra protection”; it is the reliability boundary. A correct boundary prevents ground potential differences, common-mode shocks, and noise-domain coupling from turning into timing and waveform non-compliance. This section focuses on engineering decisions, interface hooks, and measurable consequences (no safety textbook content).
Why isolate (three purposes that map to three failure modes)
Ground potential difference
Purpose: stop shield/ground offsets from shifting the receiver decision window.
Observable: differential looks acceptable, but CM moves and errors correlate with cabinet/earth events.
Check: measure differential and CM at the same time near TP3.
Common-mode shock
Purpose: keep surge/ESD energy in the field domain rather than the controller domain.
Observable: intermittent resets, latch-like faults, or timing shifts after transients.
Check: stress events while logging rail dips and waveform disturbances.
Noise-domain partition
Purpose: prevent noisy power and switching currents from modulating crossing time and edge symmetry.
Observable: crossing-time drift and margin loss tied to power mode or load steps.
Check: correlate jitter/edge metrics with supply ripple at TP2.
Where to isolate (placement decisions that impact stability)
Isolate before the PHY
Isolation sits on the digital/control interface side.
Benefit: controller domain stays clean and predictable.
Cost: isolator delay/jitter becomes part of the timing budget (see H2-6).
Isolate after the PHY
Isolation sits closer to the cable/field interface (isolated transceiver/PHY or boundary in a coupler).
Benefit: common-mode shock energy is contained in the field domain.
Cost: coupling/protection layout becomes more sensitive and must preserve waveform compliance.
Coupler boundary rule
Define separate power and signal domains across the isolation barrier.
Keep field-side energy discharge loops from crossing into the controller reference region.
Provide measurable hooks on both sides of the barrier.
Isolation parameters that directly impact timing compliance
- CMTI: insufficient CMTI can translate CM edges into output glitches. Require zero false transitions and crossing-time drift < X under CM stress.
- Propagation delay (tPD) and drift: temperature and supply drift alters the effective timing budget. Log ΔtPD across corners and enforce ΔtPD < X.
- Channel matching / skew: mismatch reduces symmetry and shrinks decision margin. Enforce skew < X and stable duty/edge symmetry.
Pass criteria (placeholders)
Use X from the system compliance template / noise budget: no false switching under CM stress, ΔtPD < X across corners, and stable crossing-time metrics at the defined test points.
Strict timing compliance: turn delay, symmetry, and jitter into measurable pass criteria
“Strict timing” becomes actionable only after the budget is decomposed into measurable segments. The total margin is shaped by PHY delay, isolator delay/drift, coupling network group delay, cable propagation, and receiver decision margin. This section stays at the physical layer and defines what to log and how to judge pass/fail with X placeholders.
Budget decomposition (placeholders)
- PHY delay: device internal timing and edge shaping.
- Isolation delay: propagation + drift across temperature/supply.
- Coupling group delay: MBP coupling/filtering changes crossing behavior.
- Cable propagation: length-dependent latency and attenuation that alters edge shape.
- Receiver margin: the remaining window after waveform imperfections and CM stress.
Budget rule
Treat each segment as a measurable contribution and validate with one-variable A/B sweeps (cable, damping, temperature, supply mode). Use X from the compliance template and noise budget.
What to log (waveform fields that correlate with compliance)
Amplitude & CM
Differential amplitude, CM swing, and CM-to-error correlation.
Pass: CM swing < X and margin > X.
Edge shape
Rise/fall time, overshoot, ringing, settling time.
Pass: overshoot < X and settling < X.
Crossing stability
Zero/threshold crossing time drift and symmetry across edges.
Pass: crossing drift < X and symmetry within X.
Delay & drift
Segment delay (PHY / isolator / coupling / cable) and Δdelay across corners.
Pass: Δdelay < X (template budgeted).
Typical traps (how compliance gets lost)
- Insufficient bandwidth: edges appear slower, crossing time shifts, and margin is mis-estimated.
- Over-filtering: waveforms look “clean” while template margin shrinks; validate with template metrics, not only visuals.
- Under-damping: topology-dependent ringing increases crossing drift; tune damping with one-variable A/B.
- Isolator drift: ΔtPD across temperature/supply consumes budget; log ΔtPD and enforce X limits.
Protection & robustness: survive ESD/surge/faults without breaking signal integrity
Port protection must satisfy two requirements at the same time: (1) energy from ESD/surge/faults is contained and safely returned, and (2) the signal path remains compliant in amplitude, edge shape, and crossing stability. The most reliable way to design this is to separate three paths: Signal, ESD, and Surge.
Three-path model (design and validate each path)
Signal path
Goal: keep waveform template margin and crossing stability.
Risk: added capacitance/mismatch increases rise time and crossing drift.
Check: log amplitude, edge metrics, and crossing drift at TP3.
ESD path
Goal: clamp fast events into the shortest return path.
Risk: long return loops inject CM spikes into the PHY.
Check: confirm no false switching under ESD stress (X placeholder).
Surge path
Goal: limit energy and keep it out of sensitive domains.
Risk: clamp events collapse rails, causing resets and timing drift.
Check: log rail dips + Δdelay under stress (X placeholders).
Component trade-offs (protect without consuming timing margin)
- Low-capacitance TVS/arrays: lower C reduces edge rounding and crossing drift. Validate with a one-variable A/B swap and ensure rise/fall time and crossing drift remain within X.
- Common-mode choke (CMC): effective when CM noise dominates, but mismatch can harm symmetry. Enforce stable differential symmetry metrics and no increase in crossing drift (X placeholders).
- Series R / damping: effective against ringing and reflection, but too much reduces amplitude and slows edges. Tune with one-variable steps and enforce overshoot/settling and amplitude margins (X placeholders).
Field fault mapping (what protection behavior is expected)
Miswiring
Need: contain CM events and prevent domain collapse.
Observe: no resets; CM spikes do not create false edges.
Pass: false switching = 0 (X placeholder conditions).
Short / overcurrent
Need: current limiting, thermal shutdown, and predictable recovery.
Observe: controlled fault state and stable recovery timing.
Pass: recovery returns to compliant waveform fields.
Open / disconnect
Need: stable idle behavior and predictable fail-safe state.
Observe: no idle chatter under noise stress.
Pass: idle stability within X and no false transitions.
ESD / surge
Need: energy returns through ESD/surge path, not through the signal path.
Observe: no false edges and Δdelay stays within X.
Pass: event does not consume timing margin beyond X.
Validation checklist (placeholders)
Log: differential amplitude + CM swing, rise/fall time, overshoot/ringing/settling, crossing drift, and Δdelay. Enforce X limits derived from the PHY compliance template and system noise budget.
Layout & grounding: reusable rules for return paths, zones, and isolation gaps
Fieldbus PHY failures often come from layout, not schematic intent. A stable design makes return paths explicit, separates noisy and quiet zones, keeps the isolation gap clean, and places the port chain in an order that enforces energy paths. This section turns layout into a checklist that remains valid across board revisions.
Return paths (map cable return behavior to the PCB reference)
- Keep the clamp/return loop local to the connector and protection devices; avoid routing transient return currents toward the PHY region.
- Preserve a continuous reference for the signal path; avoid crossing splits that force return currents to detour.
- Validate with probe hooks: log CM swing and crossing drift to detect ground-bounce artifacts (X placeholders).
Isolation gap hygiene (engineering reminders)
- Keep the gap free of copper features that unintentionally couple domains (no accidental bridges).
- Ensure field-side protection discharge loops remain on the field side; do not let energy paths cross the barrier.
- Provide clear, local reference points on both sides for measurement and debugging.
Port chain order + diagnostic test hooks (make stability repeatable)
- Typical order for field-side containment: Connector → Protection → Coupling → Isolation → PHY. Deviations must preserve the ESD/surge return path locality.
- Place TP points where they reveal root causes: TP3 near PHY input, and TP2 (or ISO_IN/ISO_OUT) around the isolation boundary.
- Ensure TP references are local and stable; a poor TP reference converts ground bounce into measurement artifacts.
Layout checklist (placeholders)
Verify: short return loops for clamps, continuous reference for the signal path, clean isolation gap, correct chain order, and TP points that can log CM swing, edge metrics, crossing drift, and Δdelay against X budgets.
Bring-up & compliance test: a step-by-step PHY verification route
A reliable bring-up route separates variables on purpose: validate the board first, then add cable effects, then termination/multi-drop behavior, and finally field noise stress. Each step has a probe point, a short log schema, and pass criteria placeholders (X) that must be derived from the PHY compliance template and system margin.
Bring-up in 4 steps (separate variables; keep evidence comparable)
Step 1 · No cable
Goal: prove board-domain stability.
Probe: TP2 / TP3 (barrier + PHY).
Pass: no false edges; crossing drift < X.
Step 2 · Add cable
Goal: isolate cable attenuation/CM effects.
Probe: TP3 + connector-side A/B.
Pass: amplitude margin > X; CM swing < X.
Step 3 · Termination & nodes
Goal: expose reflection/ringing failure modes.
Probe: connector + TP3 compare.
Pass: settling < X; ringing does not shift crossing > X.
Step 4 · Field stress
Goal: validate barrier + PSU robustness.
Probe: TP2/TP3 + supply noise correlation.
Pass: false switching = 0; Δdelay < X.
Log schema (fields only; no long theory)
Environment
- Cable length / type
- Termination position / count
- Node count / spur tags
- Temperature label (barrier)
Waveform fields
- Differential amplitude
- CM swing
- Rise/fall time
- Overshoot / ringing / settling
- Crossing drift (Δt, X placeholder)
Timing / power fields
- Δdelay (X placeholder)
- Supply ripple (mVpp / mVrms)
- DC/DC mode tag
- Event counters: resets / faults
Production correlation pack (station-to-station consistency)
- Align fixtures, cable type/length, termination placement, and measurement bandwidth settings (list and lock them).
- Treat fixture parasitics as a variable: a clamp or probe load can change edge metrics and crossing drift.
- Pass criteria: cross-station deltas of key fields (Δt_cross, Δdelay, overshoot) must remain < X (placeholders).
Notes for strict PHY scope
This route uses only PHY-observable fields and probe points; protocol stack capture is intentionally out of scope.
Troubleshooting playbook: symptom → fastest check → fix → pass criteria
The fastest PHY troubleshooting route classifies the problem by what probe points reveal: reflection, common-mode events, power/noise coupling, or delay drift. Each path below stays strictly in the physical layer and ends with X-based pass criteria placeholders.
Troubleshooting rules (keep the evidence clean)
- Change one variable per experiment (A/B correlation).
- Confirm probe reference first; ground-bounce artifacts look like jitter.
- Check topology/termination before adding damping or blaming the barrier.
- Log the same fields (amplitude, CM swing, crossing drift, Δdelay) at the same TP points.
- Use X placeholders tied to the template; avoid subjective “looks OK” decisions.
Symptom family A · Intermittent dropouts / bit errors
Path A1 (terminate → reflect → damp → PSU)
Symptom: sporadic errors, worse with longer trunk or more nodes.
Fastest check: confirm termination placement/count; compare connector vs TP3 for ringing/settling.
Fix: correct termination first; apply minimal damping only if ringing dominates; then correlate errors with supply ripple.
Pass criteria: settling < X; crossing drift < X; error events = 0 within the test window.
Path A2 (noise-driven intermittency)
Symptom: errors appear in bursts and correlate with power/load changes.
Fastest check: log supply ripple + CM swing while observing TP2/TP3; look for crossing drift growth under ripple.
Fix: improve barrier-side supply decoupling and return paths; keep clamp loops local to the connector.
Pass criteria: CM swing < X; crossing drift < X; Δdelay drift < X under stress.
Symptom family B · Stable on bench, unstable in cabinet / field installation
Path B1 (ground potential / CM shock)
Symptom: instability appears only after installation; intermittent resets or false edges occur.
Fastest check: compare bench vs field logs of CM swing and false switching at TP2/TP3.
Fix: enforce the isolation boundary (keep surge/ESD return on field side); verify protection placement and return loop locality.
Pass criteria: false switching = 0; resets = 0; CM swing < X in field conditions.
Symptom family C · Same cable, different devices behave differently
Path C1 (threshold / symmetry / filtering deltas)
Symptom: device A is stable, device B fails on the same trunk and wiring.
Fastest check: run a one-variable A/B compare: same cable/termination/noise; log crossing drift, symmetry, and Δdelay.
Fix: if symmetry is worse, reduce mismatch and CM conversion (CMC/placement/return); if drift follows filtering, remove over-filtering and retune damping.
Pass criteria: A/B deltas of key fields (Δt_cross, Δdelay, overshoot) remain < X.
H2-11. Engineering checklist: design review → production readiness
This checklist turns the PHY scope (DP/RS-485 + PA/FF-H1/MBP + coupling/isolation + timing compliance) into stage-gated actions. Each stage ends with a measurable “exit” so issues are caught before field deployment.
- Classify the segment: DP/RS-485 vs PA/FF-H1 MBP; record data-rate, bus power, intrinsic-safety need.
- Topology rule: trunk/spur limits, terminator placement, and “two-terminator” assumption captured in schematic notes.
- Isolation boundary: define Logic Domain vs Field Domain; decide whether isolation is in the coupler/link or at each port.
- Timing budget: PHY delay + isolation delay + coupling group delay + cable propagation → reserve margin “X%”.
- Power injection vs signal coupling (MBP): DC path and AC path explicitly separated; damping element included.
- Protection strategy: ESD/EFT/surge + miswire + short/open → define the safe-fail behavior (limit/thermal/fault pin).
- Diagnostic hooks: plan test points (TP1/TP2/TP3) and measurable fields (Vpp, rise time, ringing, zero-cross shift).
- Compliance plan: decide the physical-layer conformance test flow and fixtures early (bench vs production station).
- Placement order: Connector → TVS/CMC → damping/series R → coupling network → isolation gap → PHY.
- Return-path continuity: define reference plane for the interface region; avoid “slot under return”.
- Isolation keepout: creepage/clearance and guard copper rules captured; no test-pad bridging the gap.
- Coupling components (MBP): tight loop areas for AC coupling; keep noisy power nodes away from RX front-end.
- Grounding: separate quiet analog sense/receive ground from surge/ESD current return where applicable.
- ESD current path: ensure TVS return is short and does not share the sensitive signal reference path.
- Test points: provide high-impedance probe pads + adjacent low-inductance ground; label TP1/TP2/TP3 in silk.
- Thermal: isolate DC/DC hot spots from drift-sensitive timing/delay parts (isolation + comparator/filters).
- Step 1: local loopback / short cable; confirm idle bias, Vpp (MBP), and symmetry at TP1.
- Step 2: add representative cable length; measure ringing and zero-cross timing drift at TP2.
- Step 3: add terminators + multi-node load; confirm margins do not collapse at TP3.
- Step 4: inject realistic noise (supply ripple / CM disturbance) and check the failure signature.
- Log fields: cable length, terminator positions, bus voltage/current, DC/DC temperature, supply ripple RMS.
- Correlation: repeat on second board and second scope probe to rule out setup artifacts.
- Golden waveform: store a “known-good” capture (settings + screenshots + CSV) for future regression.
- Fix iteration: change one variable per run (termination / damping / TVS / isolation supply filter).
- Fixture equivalence: same cable, same terminators, same ground scheme; document the exact harness PN.
- Station-to-station: run one golden unit across all stations daily; track drift of key metrics.
- Thresholds: define X for Vpp / rise time / ringing / timing drift; lock down scope BW/RBW and probes.
- Screening: temperature spot-check and isolation supply ripple check for early drift detection.
- Fault coverage: short/open/miswire test step with expected safe behavior (no damage + clear fail flag).
- Field returns: require waveform + log bundle (cable length, supply noise, ambient, grounding notes).
- Change control: BOM or layout changes must trigger re-run of the physical-layer conformance test set.
- Traceability: lot/date code recorded for PHY/MAU, isolator, DC/DC, TVS, and coupling magnetics.
- onsemi AMIS-49200 / AMIS-49250 (Fieldbus MAU)
- TI DAC8740H (UART) / DAC8741H (SPI) / DAC8742H (UART+SPI)
- TI SN65HVD485E (general RS-485)
- TI SN65HVD1471 / SN65HVD1474 (RS-485, multi-node)
- Example isolated options: TI ISO1410 / ISO1452; ADI ADM2587E, ADM2682E
- TVS for RS-485: Littelfuse SM712 series
- Common-mode choke (optional): TDK ACM2012-900-2P-T001 (choose impedance by noise profile)
- Series damping resistor: 10–47 Ω class (set by waveform/timing; not a default)
- Murata NXE1S0505MC (isolated DC/DC module)
- RECOM R05P05S (isolated DC/DC module)
- Traco Power TEN 3-0511 (isolated DC/DC module)
H2-12. Applications & IC selection notes: scenarios → blocks → pass criteria
The goal is not “pick a product”, but “pick a block-set”: PHY/MAU + coupling + isolation + protection + measurable test points. Use the scenario cards first, then follow the selection flow.
- Long trunk + multiple spurs; bus-powered devices are common
- Noise sources: supply ripple, CM disturbance, ground potential differences
- Selection emphasis: MBP MAU + coupling damping + isolation boundary + test points
- High demand for isolation + predictable fail behavior under surge/miswire
- Selection emphasis: reinforced isolation, high CMTI, low-drift delay, and controlled ESD current path
- Layout emphasis: isolation keepout + “no return sharing” near TVS
- Higher data rate; termination + biasing + CM behavior dominate stability
- Selection emphasis: failsafe receiver, node count (unit load), fault protection, and defined idle behavior
- Robustness: TVS + optional CMC + thermal shutdown/fault indication
- Two domains meet: DP/RS-485 and PA/FF-H1/MBP
- Selection emphasis: domain isolation, clean power injection, and diagnostic taps per domain
- Validation emphasis: station-to-station correlation; golden cable + terminator harness
PA/FF-H1: choose MBP MAU/modem capability + low quiescent + physical-layer compliance readiness.
PA/FF: onsemi AMIS-49200/AMIS-49250, TI DAC8740H/DAC8741H/DAC8742H
- DC path: bus power injection and conditioning must not inject noise into the receive band.
- AC path: coupling capacitor/inductor network defines amplitude and ringing.
- Damping: a controlled loss element prevents “looks OK on bench, fails in plant” behavior.
- Where: isolate at the port, or isolate inside the coupler/linking device boundary.
- Why: ground potential, CM surge, noise-domain separation.
- Timing: delay and drift must be budgeted; avoid “isolation added late”.
Isolated DC/DC: Murata NXE1S0505MC, RECOM R05P05S, Traco TEN 3-0511
- TVS: choose to clamp transients while not reshaping the signal.
- CMC/series R: apply only when it improves measured margins; otherwise it can distort timing.
- Diagnostics: TP pads + fault pins + current sense (if used) must be designed as first-class features.
Optional CMC: TDK ACM2012-900-2P-T001 (pick impedance by EMI/immunity target)
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H2-13. FAQs: PHY troubleshooting (DP/PA/FF-H1, coupling, isolation, timing)
These FAQs only cover the physical layer: waveform, coupling/isolation, protection, layout return paths, timing compliance, and station-to-station correlation. Each answer is a four-line, measurable checklist with threshold placeholders (X).
