SPI CPOL/CPHA Modes (0–3): Master/Slave Alignment Guide

Q: Works at 1 MHz but fails at 8 MHz—mode is right. What’s the first timing-window check?

Likely cause: Sampling margin collapses at higher SCLK (sample point moves too close to the data transition).\nQuick check: A/B test: run the same strong pattern at 1 MHz vs 8 MHz (≥200 frames each) and compare mismatch rate.\nFix: Select the CPHA that places sampling deeper inside the stable window, or lock a conservative SCLK for the target error budget.\nPass criteria: At 8 MHz, N ≥ 200 consecutive frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

Q: Read ID is correct but bulk data has a 1-bit shift—mode mismatch or CS/first-bit timing?

Likely cause: Frame start is wrong (CS→first clock/first sample timing), creating a “phantom shift” even when mode looks right.\nQuick check: Increase tCSS (insert a fixed wait) and re-test with 0xAA/0x55 + counter; compare “first byte” error rate vs mid-stream.\nFix: Enforce a safe sequence: CS assert → wait (≥tCSS) → clock → CS deassert, then re-verify CPHA evidence.\nPass criteria: “First byte” error rate ≈ mid-stream error rate; N ≥ 200 frames with 0 first-byte-only failures.

Q: All 0xFF or all 0x00 looks “OK”—what pattern proves CPHA is correct?

Likely cause: Weak patterns (0x00/0xFF) can mask CPHA errors and still look “stable.”\nQuick check: Use 0xAA/0x55 (and 0x55/0xAA) plus an incrementing counter; repeat ≥200 frames.\nFix: Make strong-pattern proof mandatory in bring-up and production gates; do not accept all-0/all-1 as mode evidence.\nPass criteria: N ≥ 200 frames, bit-shift count = 0, counter monotonic, mismatch rate ≤ X ppm (set X).

Q: One vendor says “sample on first edge”—how to map that to Mode 0–3?

Likely cause: “First edge” wording is ambiguous unless it is referenced to the idle level (CPOL).\nQuick check: Determine CPOL from “SCLK idle level,” then define leading = idle→active and map “first/second” to leading/trailing.\nFix: Translate datasheet text into a single coordinate system: idle + sample edge → pick Mode 0–3.\nPass criteria: Raw waveform evidence (sample point inside stable window) + N ≥ 50 correct ID reads + strong pattern passes.

Q: Analyzer decode looks wrong—how to verify without trusting decode settings?

Likely cause: Decoder mode (CPOL/CPHA) is misconfigured; decode errors do not prove bus errors.\nQuick check: Ignore decode first: verify SCLK idle (CPOL) and whether sampling is away from transitions; then cross-check with AA55/counter.\nFix: Lock the true mode using raw-edge evidence, then configure the analyzer decoder to match the proven mode.\nPass criteria: Raw evidence consistent + N ≥ 200 strong-pattern frames correct; decoder output matches afterward.

Q: Only MISO is wrong, MOSI writes seem fine—what CPHA symptom is most common?

Likely cause: The master samples MISO too close to when the slave updates it (CPHA places sampling near the transition).\nQuick check: Run read-only AA55/counter at fixed SCLK, then flip CPHA (keep everything else constant) and compare mismatch rate.\nFix: Choose the CPHA that moves sampling away from the update edge; if needed, confirm window sensitivity by down-shifting SCLK.\nPass criteria: N ≥ 200 read frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

Q: After reset, the first transaction fails but subsequent ones pass—CS timing or phase?

Likely cause: The first frame violates frame-start timing (tCSS/first-bit) or runs before mode is re-applied after reset.\nQuick check: Add a deterministic post-reset settle + tCSS wait and make the first operation a repeated ID read (≥20 reads).\nFix: Force an init order: apply mode → frame-start guard → lightweight self-test → enable traffic.\nPass criteria: First transaction success rate = subsequent success rate; N ≥ 50 cold-start cycles with 0 first-frame failures.

Q: Two slaves on the same bus need different modes—what’s the safest firmware structure?

Likely cause: Mode is treated as a bus-global default, causing silent mismatches when switching chip-select.\nQuick check: Confirm the driver stores per-slave (CS-bound) config: mode, SCLK, CS timing; verify config is applied on every CS switch.\nFix: Implement a per-slave “config contract”: select CS → apply mode → optional short self-test → transact.\nPass criteria: Any switching order passes: each slave achieves N ≥ 50 strong-pattern frames with 0 bit-shift events.

Q: Mode is correct but an occasional wrong byte appears—what quick re-test isolates phase vs framing?

Likely cause: Either phase margin is thin (sampling occasionally near transitions) or framing is unstable (CS/first-bit occasionally wrong).\nQuick check: Count where errors occur: first byte vs mid-stream; run down-shift SCLK A/B; repeat AA55/counter for ≥500 frames.\nFix: If down-shift improves → treat as window margin (choose safer CPHA or rate). If first-byte dominates → harden CS/first-bit timing.\nPass criteria: At target settings: N ≥ 500 frames, wrong-byte count = 0, mismatch rate ≤ X ppm (set X).

Q: SPI works with slow edges but fails with faster drive strength—what is the first CPHA/edge-placement sanity check? (No SI deep-dive)

Likely cause: With “faster edges,” sampling becomes more sensitive to edge placement; the effective stable window shrinks relative to uncertainty.\nQuick check: Keep mode fixed and down-shift SCLK; then flip CPHA (A/B) to see whether errors track sampling edge choice.\nFix: Select the CPHA that increases sampling distance from transitions, and require AA55/counter proof at the final drive setting.\nPass criteria: Final setting passes N ≥ 500 frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

← Back to: I²C / SPI / UART — Serial Peripheral Buses

This page explains how to correctly align SPI Mode 0–3 (CPOL/CPHA) between master and slave, so sampling happens inside the valid data window and bit-slip is avoided.

It provides a practical mapping model, frame-start (CS/first-bit) rules, and proof-by-test patterns so the chosen mode can be verified and kept stable across resets and firmware revisions.

Definition: What CPOL/CPHA Really Means (and What It Does Not)

CPOL/CPHA defines only two things: the idle level of SCLK and the sampling edge relative to the first clock transition after the bus leaves idle. Getting this definition wrong is the fastest way to create “looks-alive but misreads” behavior (bit-shift / bit-slip) across mixed-vendor masters and slaves.

Terminology (use one coordinate system)

CPOL: SCLK idle level (the level when the bus is not clocking).
Leading edge: the first SCLK transition after leaving idle (idle→active).
Trailing edge: the second transition (active→idle direction within the cycle).
CPHA: which edge is used for sampling (leading or trailing).

The #1 vendor-language trap

“First edge / second edge” is ambiguous unless it is anchored to idle. Some datasheets describe edges as rising/falling (absolute), while others describe leading/trailing (relative to CPOL).

Always determine idle level first → then define leading/trailing.
Do not treat “data valid on edge” as “sample on edge” (valid is a window, sample is a point).

What CPOL/CPHA does not define

Bit order (MSB/LSB first), frame length, CRC policies.
Chip-select polarity/behavior (CS timing is handled separately).
Numeric setup/hold margins (addressed later as timing budget).

This page stays focused on edge alignment to prevent bit-shift/bit-slip.

Minimal coordinate system: idle → leading/trailing edges → sampling point

Use this coordinate system everywhere: determine idle first (CPOL), then name leading/trailing edges, then place the sample point (CPHA).

Mode Map: Modes 0–3 in One Mental Model (No Tables Needed)

The fastest reliable mapping is: CPOL decides idle → CPHA decides sampling edge. Then the “other edge” becomes the natural shift/update edge (where the transmitter changes data), which is exactly why mismatched CPHA creates bit-shift and unstable reads.

30-second alignment workflow

Find SCLK idle in the slave timing diagram → choose CPOL.
Find the sampling edge (where data is captured) → choose CPHA as leading or trailing.
Set MCU to the resulting Mode 0–3, then validate with a strong pattern (e.g., 0xAA/0x55, not all-zeros/all-ones).

Mode 0

Idle: Low (CPOL=0)

Sample: Leading edge (CPHA=0)

Shift: Trailing edge

Mode 1

Idle: Low (CPOL=0)

Sample: Trailing edge (CPHA=1)

Shift: Leading edge

Mode 2

Idle: High (CPOL=1)

Sample: Leading edge (CPHA=0)

Shift: Trailing edge

Mode 3

Idle: High (CPOL=1)

Sample: Trailing edge (CPHA=1)

Shift: Leading edge

Four-mode visual map: CPOL changes idle; CPHA moves the sample point

A common mismatch pattern: the transmitter changes DATA on the same edge the receiver samples. The cure is always the same: anchor edges to idle, then set CPHA so sampling lands inside the stable window.

Quick anti-confusion rules (mixed-vendor safe)

Always choose CPOL first: rising/falling only becomes meaningful after idle level is known.
Sampling is a point: “data valid” describes a window; confirm where the receiver captures.
Shift/update is the other edge: if the receiver samples on the update edge, bit-shift is expected.

Sampling vs Shifting: Where Bit-Slip Is Born

Bit-slip and bit-shift are rarely “mystery protocol bugs.” They usually happen when the receiver samples too close to the moment the transmitter updates DATA. If sampling lands in the change region, metastability and edge ambiguity turn into intermittent misreads—even when the link seems alive.

Failure signatures (what the errors look like)

Fixed 1-bit shift: consistent bit offset across reads (classic edge mismatch).
“Looks OK” with 0x00/0xFF, fails with 0xAA/0x55 (weak patterns hide timing risk).
Only the first byte/bit is wrong: frame start is marginal (edge choice + start timing).
Random, intermittent flips: sampling point sits near the boundary with low margin.

Root-cause shortlist (CPOL/CPHA only)

CPHA mismatch: master updates DATA on the same edge the slave samples.
Wrong edge naming: “first/second edge” interpreted without anchoring to idle.
Sampling too close to update: stable window exists, but the sample point is placed near its edge.
Decoder illusion: analysis tools decode with the wrong mode, masking the real mapping.

This section stays on edge alignment; signal-integrity fixes live in sibling pages.

Fast isolation checklist (minimal changes)

Use a strong pattern (0xAA/0x55 or incrementing counter) to reveal bit-shift.
Reduce SCLK by one step: if errors shrink, sampling margin is tight.
Toggle CPHA only (keep CPOL fixed): disappearance or “signature change” confirms edge conflict.

Pass criteria (placeholder)

Consistent read/write results for N trials with error rate < X. (Choose N/X per system risk.)

Wrong-edge symptom: sampling lands inside the DATA update region (risk zone)

When CPHA is wrong, sampling can coincide with the update edge. The goal is to move sampling into the stable window, away from the change region.

Master/Slave Alignment: Datasheet Language Traps (Cross-Vendor)

SPI timing is often described in incompatible phrases. The safe approach is to translate everything into one coordinate system: determine SCLK idle → name leading/trailing edges → locate the capture (sample) edge → derive CPOL/CPHA → pick Mode 0–3.

Translation dictionary (phrase → meaning)

A) “Sample on rising/falling”

Rising/falling is absolute. Choose CPOL first (idle high/low), then map the stated edge to leading/trailing.

B) “Data valid / captured”

“Valid” describes a window. “Captured/latched” identifies the sample point. Use “captured” for CPHA.

C) “Polarity/phase definition”

If the text defines “phase = sample on first edge,” verify what “first” means: it must be the first edge after idle.

If only a waveform is given (no mode stated)

Read SCLK idle when not clocking → CPOL.
Name leading edge as the first transition after idle.
Locate capture (“sample/latched”) edge → CPHA.
Sanity check: sampling should land inside the stable DATA window, not at the transition.

Output

CPOL + CPHA → Mode 0/1/2/3 (use the mode map from H2-2).

Translation flow: datasheet phrase/waveform → CPOL/CPHA → Mode 0–3

Treat datasheet timing as input data, not truth in prose form. Translate it into the same idle/edge coordinate system, then derive CPOL/CPHA deterministically.

CS, First Bit, and the “Phantom Shift” Problem (Within CPOL/CPHA Boundary)

Some “mode-like” failures are not caused by CPOL/CPHA at all. A common pattern is first-bit loss or first-bit misread at the frame start, which can look like a one-bit shift. This section stays strictly on timing relationships between CS, the first clock, and the first sampling point.

Frame start checklist (safe sequence)

Assert CS (stable active level) and keep it quiet.
Wait tCSS(min): CS→first SCLK edge spacing must meet the slave requirement.
Present first bit on MOSI/MISO according to CPHA rules (see note below).
Start clocking and keep CS stable for the full frame length.
Deassert CS only after the last sample point is safely completed.

CPHA note (frame start)

CPHA=0: first bit must be stable before the first (leading) sample edge.
CPHA=1: sampling occurs later (trailing edge), but the first half-cycle must still be defined cleanly.

Phantom shift signatures (frame-start illusions)

Only the first bit/byte is wrong, remaining bits look correct.
Pattern-dependent failure: 0x00/0xFF looks fine, 0xAA/0x55 fails at the first byte.
Intermittent one-bit offset after occasional CS glitches or early release.
“Mode swap makes it worse”: changing CPOL/CPHA does not consistently fix the first-bit issue.

Quick check

Verify tCSS and confirm the first sample point lands inside a stable first-bit window.

Boundary (avoid sibling-page overlap)

This section discusses CS/SCLK/DATA timing relationships only. It does not cover routing length, termination, ringing, or driver strength. Those belong to signal-integrity and long-trace design pages.

Goal

A frame start that is deterministic: CS asserts → wait → clock → first sample occurs inside a stable window.

Frame start timing: CS assert, tCSS, and the first sample point

The first sample point must land inside a stable first-bit window. If CS timing is too tight or CS glitches, a “phantom shift” can appear even when CPOL/CPHA is correct.

Timing Budget: Setup/Hold Windows That Actually Matter for Mode Selection

Mode selection becomes robust when it is treated as window placement: CPHA decides where the sample point sits relative to the DATA update edge. The usable window is shaped by device timing (tSU/tHD), clock-to-data delays, and total uncertainty. This section focuses on the window model, not on signal-integrity details.

Budget template (structure, no hard numbers)

margin = (half-period) − (tCO + tPD + uncertainty)

half-period: time between edges used as update→sample spacing basis.
tCO: clock-to-data delay at the transmitter side (launch path).
tPD: logic/bridge/isolator delay along the data path (lumped).
uncertainty: total edge/sample ambiguity (lumped guard band).

Pass criteria (quantitative, system-defined)

margin ≥ X ns

Choose X based on SCLK, device timing limits, and system risk tolerance (temperature, lot spread, aging).

X must be > 0: reserve headroom for non-ideal conditions.
Use the same X across tests to avoid “it passed once” traps.

CPHA effect (window placement)

CPHA=0: sample on leading edge → first-bit setup is stricter; sampling is closer to frame start.
CPHA=1: sample on trailing edge → sampling is shifted later within the cycle; can increase usable window for some paths.
In both cases, the sample point must land inside the stable window, away from the update edge.

Guardrail

After changing CPHA, re-check the frame start behavior (CS + first bit) from H2-5.

Sampling window model: stable window, update edge, uncertainty band, and sample point

Use the window model to choose CPHA: place the sample point away from the update edge and inside the stable window, then verify margin against the system-defined threshold.

Power-up Defaults & Safe Negotiation (Avoiding Silent Mismatches)

A mode mismatch at power-up can appear as “all-zeros,” “all-ones,” or occasional correct reads. Many controllers default to Mode 0, while the peripheral may expect a different CPOL/CPHA. A safe bring-up flow treats the default as untrusted and uses repeatable checks to lock the correct mode.

Bring-up playbook (power-up → lock)

Start conservative: use a safe SCLK and stable CS timing.
Try a candidate mode (CPOL/CPHA) with controlled parameters.
Read a fixed ID/WHOAMI register multiple times (consistency matters).
Run a strong pattern check (0xAA/0x55 or counter-based) to reveal bit-shift.
Pass → lock configuration (mode + frequency + CS settings) for normal operation.
Fail → advance to the next candidate mode (bounded attempts; no infinite loops).
Persist the decided configuration if the system requires it (firmware config first; NVM only if applicable).

Guardrails

Use a bounded scan (up to 4 modes) and require N consistent passes before locking.

Logging fields (make bring-up reproducible)

Mode: CPOL/CPHA (Mode 0/1/2/3).
SCLK: frequency and divider/source.
CS timing: tCSS / hold settings or configuration profile name.
Probe: ID/WHOAMI read result and repetition count.
Pattern: AA55 / counter / other.
Failure signature: all-0, all-1, bit-shift, intermittent, timeout.
Attempt index: which mode trial number.
Context (optional): board revision, temperature, supply state.

Why it matters

“Pass once” is not enough. Consistent logs make silent mismatches diagnosable across boards and builds.

Auto-detect state machine (controlled scan with evidence-based lock)

A successful lock requires evidence (repeatable ID reads + strong patterns). Failures should be logged with signatures and bounded retries.

Verification: How to Prove the Mode Is Correct (Logic Analyzer + Golden Patterns)

Verification should be evidence-based: inspect raw edges and sampling points first, then use protocol decode as a cross-check. Weak patterns (0x00/0xFF) can hide bit shifts; strong patterns and repeatability are required to prove correctness.

Tool setup (raw first, decode second)

Identify CS/SCLK/DATA channels and confirm voltage thresholds.
Confirm SCLK idle level and edge placement (leading/trailing).
Locate sampling relative to data stable windows (ignore decode at this step).
Enable decode with the candidate mode and confirm it matches the raw observation.

Rule

Decode output is not evidence until the raw edges and sampling points agree with it.

Golden patterns (avoid weak tests)

Too weak: 0x00 / 0xFF (can look “correct” even with shifts).
Strong: 0xAA / 0x55 (reveals 1-bit shift quickly).
Strong: incrementing counter (reveals dropped/repeated bits and frame-start issues).
Optional: CRC or checksum (use as an extra indicator, not a substitute for edge checks).

Recommended order

AA55 → counter → fixed ID readback.

Pass criteria (evidence-based)

N consistent trials + no bit shift + error rate < X

Choose N and X based on system risk and operating envelope (placeholders).

N should be > 1 (repeatability), not a single “lucky” pass.
Patterns must include AA55 or counter to detect subtle shifts.
Raw-edge confirmation must agree with decode configuration.

Analyzer-style view (simplified): raw edges, sampling points, and decode bubbles

Strong patterns (AA55/counter) combined with repeatable trials are the fastest way to prove CPOL/CPHA correctness and rule out silent mismatches.

Debug Playbook: Bit-slip / Bit-shift Symptoms → Quickest Checks

Bit-slip and bit-shift failures should be treated as a structured workflow: classify the symptom, run the shortest checks in order, and apply actions that stay within CPOL/CPHA and frame-start boundaries. The goal is to avoid “lucky passes” and converge to evidence-based fixes.

Symptom Fixed 1-bit offset

Quick checks

Confirm CPOL/CPHA mapping using leading/trailing edges.
Verify the sample point is not on the data transition.
Validate with 0xAA/0x55 (not 0x00/0xFF).

Actions

Switch CPHA (0↔1) only after raw-edge confirmation.
Re-verify frame start (CS + first bit) after any change.

Symptom Intermittent shift (rare)

Quick checks

Run N repeated trials and record failure signatures (placeholder).
Lower SCLK one step to test window margin sensitivity.
Use AA55 or counter to avoid weak-pattern masking.

Actions

Adopt the mode that places sampling deeper inside the stable window.
Define a pass threshold: error rate < X (placeholder) at target SCLK.

Symptom High-speed only

Quick checks

Reduce SCLK and confirm whether failures disappear (window shrinks at speed).
Check the budget template: half-period vs (delays + uncertainty).
Re-check CPHA placement (sample on leading vs trailing).

Actions

Lock a conservative SCLK or choose a mode that increases sampling margin.
Define margin ≥ X ns (placeholder) for the target rate.

Symptom All 0 / All 1 “passes”

Quick checks

Do not use 0x00/0xFF for mode proof (too weak).
Switch to AA55 and an incrementing counter.
Repeat reads of a fixed ID register for consistency.

Actions

Require strong patterns in verification gates (AA55/counter).
Log the failure signature and stop treating “silent values” as success.

Symptom First byte only wrong

Quick checks

Check CS → first SCLK spacing (tCSS) and stability.
Confirm the first sample point lands in a stable first-bit window.
Verify CPHA frame-start expectations (sample timing vs first bit).

Actions

Increase tCSS (or insert a controlled wait) before the first clock edge.
Lock CS behavior and re-verify with AA55 across N trials.

Symptom Mode change made it worse

Quick checks

Stop using decode as evidence; return to raw edge observation.
Re-check frame start (CS + first bit) and strong patterns.
Verify that the tested mode was actually applied per device.

Actions

Re-run the controlled negotiation flow (mode scan + evidence).
Lock the correct mode and verify repeatability (N trials).

Decision tree: symptom → quickest checks → actions (CPOL/CPHA boundary)

Use the shortest path: confirm mode (raw edges) → confirm CS/first bit → down-shift SCLK to test window sensitivity → verify with strong patterns.

Design Hooks: Firmware & Register-map Practices to Prevent Mode Regressions

Many mode failures are regressions: a port, refactor, or board update silently restores defaults. Preventing this requires a clear configuration contract, a single source of truth for CPOL/CPHA per slave, a lightweight power-up self-test, and production hooks that enforce repeatability.

Regression-prevention checklist (contract first)

Store CPOL/CPHA in a board config / device tree / init table (single source).
Bind the contract per slave (do not assume one SPI bus = one mode).
Apply config before traffic: load cfg → set mode → verify → enable.
Record a config version/hash (placeholder) to detect unintended changes.

Per-slave rule

Each CS target owns its mode and verification gates.

Lightweight power-up self-test (fast evidence)

Read fixed ID/WHOAMI × N and require identical results (N placeholder).
Run a short AA55 or counter test to expose subtle shifts.
On failure, log signature and stop treating all-0/all-1 as success.

Failure signatures

all-0 / all-1 / bit-shift / first-byte / timeout (log + triage)

Production test hooks (ICT/ATE gates)

Pass = N consistent trials + no bit shift + error rate < X (placeholders).
Require at least one strong-pattern step (AA55/counter).
Report the locked mode and config version/hash to the test log.

Purpose

Make regressions detectable by gating and traceable logs.

Config contract flow: board cfg → init (per slave) → self-test → runtime monitor → production hook

Treat CPOL/CPHA as a configuration contract per slave. Enforce it through init order, lightweight self-test, runtime counters, and production gates.

Selection should reduce mode-risk, not create a “part recommendation” page. The checks below focus only on what directly impacts CPOL/CPHA alignment, frame start (CS + first bit), and proof of correctness.

Selection checklist (evidence-first)

Docs clarity

Timing diagram shows SCLK/MOSI/MISO/CS explicitly.
Sampling edge is unambiguous (rising/falling or leading/trailing).
Mode mapping is stated (Mode 0–3 or CPOL/CPHA spelled out).

Mode flexibility

Supports multiple modes (ideal: M0–M3; otherwise document a fixed mode clearly).
Mode behavior is stable across transactions (no hidden “mode changes” without explicit configuration).

CS / frame-start tolerance

Explicit tCSS / tCSH / CS hold requirements are specified.
First-bit stability relative to the first sample point is clear (ties directly to CPHA).

Test hooks (prove the mode)

Has a fixed ID/WHOAMI register for repeatable readback.
Provides loopback/BIST or a strong integrity feature such as CRC (optional but valuable).
Verification can use strong patterns (0xAA/0x55, counter) without relying on weak all-0/all-1 tests.

Red flags (mode-risk)

Only “first/second edge” wording with no waveform to disambiguate.
No CS timing guidance (frame start becomes guesswork).
No strong verification hooks (hard to prove correctness and prevent regressions).

Example part numbers (for documentation/verification practice)

These are concrete examples commonly used in SPI contexts. Always verify the exact mode, timing, package, suffix, and availability from the latest datasheet.

SPI NOR Flash

Winbond W25Q64JV
Macronix MX25L12835F
Micron MT25QL128ABA

Useful for strong-pattern and repeatable read tests.

Sensors / IMU

ST LSM6DSOX
Bosch BMI270
TDK InvenSense ICM-42688-P

Often includes ID/WHOAMI-style verification hooks.

SPI ADC

Analog Devices AD7685
Texas Instruments ADS8320
Microchip MCP3008

Typically publishes explicit timing waveforms and edge requirements.

Usage note

Use these examples to practice: (1) map datasheet language to leading/trailing edges, (2) confirm CS frame start, (3) prove correctness with AA55/counter and repeated trials.

Mode-related selection checklist (box diagram)

Prefer devices with explicit sampling-edge documentation, clear CS timing guidance, and verification hooks that enable strong-pattern proof.

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FAQs (Mode 0–3 / CPOL/CPHA) — Troubleshooting Without Expanding Scope

Each FAQ uses the same 4-line structure so the result is executable and testable: Likely cause, Quick check, Fix, Pass criteria. Numeric thresholds use placeholders (X) that should be set by the system’s target rate and required error budget.

Works at 1 MHz but fails at 8 MHz—mode is right. What’s the first timing-window check?

Likely cause: Sampling margin collapses at higher SCLK (sample point moves too close to the data transition).

Quick check: A/B test: run the same strong pattern at 1 MHz vs 8 MHz (≥200 frames each) and compare mismatch rate.

Fix: Select the CPHA that places sampling deeper inside the stable window, or lock a conservative SCLK for the target error budget.

Pass criteria: At 8 MHz, N ≥ 200 consecutive frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

Read ID is correct but bulk data has a 1-bit shift—mode mismatch or CS/first-bit timing?

Likely cause: Frame start is wrong (CS→first clock/first sample timing), creating a “phantom shift” even when mode looks right.

Quick check: Increase tCSS (insert a fixed wait) and re-test with 0xAA/0x55 + counter; compare “first byte” error rate vs mid-stream.

Fix: Enforce a safe sequence: CS assert → wait (≥tCSS) → clock → CS deassert, then re-verify CPHA evidence.

Pass criteria: “First byte” error rate ≈ mid-stream error rate; N ≥ 200 frames with 0 first-byte-only failures.

All 0xFF or all 0x00 looks “OK”—what pattern proves CPHA is correct?

Likely cause: Weak patterns (0x00/0xFF) can mask CPHA errors and still look “stable.”

Quick check: Use 0xAA/0x55 (and 0x55/0xAA) plus an incrementing counter; repeat ≥200 frames.

Fix: Make strong-pattern proof mandatory in bring-up and production gates; do not accept all-0/all-1 as mode evidence.

Pass criteria: N ≥ 200 frames, bit-shift count = 0, counter monotonic, mismatch rate ≤ X ppm (set X).

One vendor says “sample on first edge”—how to map that to Mode 0–3?

Likely cause: “First edge” wording is ambiguous unless it is referenced to the idle level (CPOL).

Quick check: Determine CPOL from “SCLK idle level,” then define leading = idle→active and map “first/second” to leading/trailing.

Fix: Translate datasheet text into a single coordinate system: idle + sample edge → pick Mode 0–3.

Pass criteria: Raw waveform evidence (sample point inside stable window) + N ≥ 50 correct ID reads + strong pattern passes.

Analyzer decode looks wrong—how to verify without trusting decode settings?

Likely cause: Decoder mode (CPOL/CPHA) is misconfigured; decode errors do not prove bus errors.

Quick check: Ignore decode first: verify SCLK idle (CPOL) and whether sampling is away from transitions; then cross-check with AA55/counter.

Fix: Lock the true mode using raw-edge evidence, then configure the analyzer decoder to match the proven mode.

Pass criteria: Raw evidence consistent + N ≥ 200 strong-pattern frames correct; decoder output matches afterward.

Only MISO is wrong, MOSI writes seem fine—what CPHA symptom is most common?

Likely cause: The master samples MISO too close to when the slave updates it (CPHA places sampling near the transition).

Quick check: Run read-only AA55/counter at fixed SCLK, then flip CPHA (keep everything else constant) and compare mismatch rate.

Fix: Choose the CPHA that moves sampling away from the update edge; if needed, confirm window sensitivity by down-shifting SCLK.

Pass criteria: N ≥ 200 read frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

After reset, the first transaction fails but subsequent ones pass—CS timing or phase?

Likely cause: The first frame violates frame-start timing (tCSS/first-bit) or runs before mode is re-applied after reset.

Quick check: Add a deterministic “post-reset settle + tCSS wait” and make the first operation a repeated ID read (≥20 reads).

Fix: Force an init order: apply mode → frame-start guard → lightweight self-test → enable traffic.

Pass criteria: First transaction success rate = subsequent success rate; N ≥ 50 cold-start cycles with 0 first-frame failures.

Two slaves on the same bus need different modes—what’s the safest firmware structure?

Likely cause: Mode is treated as a bus-global default, causing silent mismatches when switching chip-select.

Quick check: Confirm the driver stores per-slave (CS-bound) config: mode, SCLK, CS timing; verify config is applied on every CS switch.

Fix: Implement a per-slave “config contract”: select CS → apply mode → optional short self-test → transact.

Pass criteria: Any switching order passes: each slave achieves N ≥ 50 strong-pattern frames with 0 bit-shift events.

Mode is correct but an occasional wrong byte appears—what quick re-test isolates phase vs framing?

Likely cause: Either phase margin is thin (sampling occasionally near transitions) or framing is unstable (CS/first-bit occasionally wrong).

Quick check: Count where errors occur: first byte vs mid-stream; run down-shift SCLK A/B; repeat AA55/counter for ≥500 frames.

Fix: If down-shift improves → treat as window margin (choose safer CPHA or rate). If first-byte dominates → harden CS/first-bit timing.

Pass criteria: At target settings: N ≥ 500 frames, wrong-byte count = 0, mismatch rate ≤ X ppm (set X).

SPI works with slow edges but fails with faster drive strength—what is the first CPHA/edge-placement sanity check? (No SI deep-dive)

Likely cause: With “faster edges,” sampling becomes more sensitive to edge placement; the effective stable window shrinks relative to uncertainty.

Quick check: Keep mode fixed and down-shift SCLK; then flip CPHA (A/B) to see whether errors track sampling edge choice.

Fix: Select the CPHA that increases sampling distance from transitions, and require AA55/counter proof at the final drive setting.

Pass criteria: Final setting passes N ≥ 500 frames with 0 bit-shift events and mismatch rate ≤ X ppm (set X).

Why does changing CPOL fix one device but break another—what does idle level imply?

Likely cause: Different slaves assume different SCLK idle levels; changing CPOL flips which edge is “leading,” breaking the other device.

Quick check: For each slave, confirm idle level (CPOL) and the intended sample edge using raw observation + ID + AA55 proof.

Fix: Enforce per-slave mode configuration and apply it on every CS selection; avoid “one-bus-one-mode” assumptions.

Pass criteria: Each slave passes its own contract: N ≥ 200 strong-pattern frames with 0 bit-shift events per device.

Slave requires “data valid on rising edge”—does that mean sample on rising or change on rising?

Likely cause: “Data valid on edge” can describe either sampling or launching; it must be disambiguated against idle and stability timing.

Quick check: Find the waveform (preferred) or use raw observation: determine whether data is stable before rising (sample) or changes on rising (launch).

Fix: Translate to “sample edge vs shift edge,” then map to Mode 0–3; confirm using AA55/counter rather than weak patterns.

Pass criteria: Raw-edge interpretation matches config + N ≥ 200 strong-pattern frames correct + bit-shift count = 0.

SPI CPOL/CPHA Modes (0–3): Master/Slave Alignment Guide

SPI CPOL/CPHA Modes (0–3): Master/Slave Alignment Guide

Definition: What CPOL/CPHA Really Means (and What It Does Not)

Terminology (use one coordinate system)

The #1 vendor-language trap

What CPOL/CPHA does not define

Mode Map: Modes 0–3 in One Mental Model (No Tables Needed)

30-second alignment workflow

Quick anti-confusion rules (mixed-vendor safe)

Sampling vs Shifting: Where Bit-Slip Is Born

Failure signatures (what the errors look like)

Root-cause shortlist (CPOL/CPHA only)

Fast isolation checklist (minimal changes)

Master/Slave Alignment: Datasheet Language Traps (Cross-Vendor)

Translation dictionary (phrase → meaning)

If only a waveform is given (no mode stated)

CS, First Bit, and the “Phantom Shift” Problem (Within CPOL/CPHA Boundary)

Frame start checklist (safe sequence)

Phantom shift signatures (frame-start illusions)

Boundary (avoid sibling-page overlap)

Timing Budget: Setup/Hold Windows That Actually Matter for Mode Selection

Budget template (structure, no hard numbers)

Pass criteria (quantitative, system-defined)

CPHA effect (window placement)

Power-up Defaults & Safe Negotiation (Avoiding Silent Mismatches)

Bring-up playbook (power-up → lock)

Logging fields (make bring-up reproducible)

Verification: How to Prove the Mode Is Correct (Logic Analyzer + Golden Patterns)

Tool setup (raw first, decode second)

Golden patterns (avoid weak tests)

Pass criteria (evidence-based)

Debug Playbook: Bit-slip / Bit-shift Symptoms → Quickest Checks

Design Hooks: Firmware & Register-map Practices to Prevent Mode Regressions

Regression-prevention checklist (contract first)

Lightweight power-up self-test (fast evidence)

Production test hooks (ICT/ATE gates)

IC Selection Notes (Strictly CPOL/CPHA / Mode-Related)

Selection checklist (evidence-first)

Example part numbers (for documentation/verification practice)

Recommended topics you might also need

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FAQs (Mode 0–3 / CPOL/CPHA) — Troubleshooting Without Expanding Scope

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