Repeated START & Page Write for I2C EEPROM/Register Access
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Repeated START (Sr) is the portable way to keep an I²C “write pointer → read data” access atomic without releasing the bus, while EEPROM page write must end with STOP to trigger the internal write cycle and be completed with bounded busy handling (ACK polling + timeout). This page provides wire-true templates, measurable pass criteria, and production-grade recovery rules so reads never “stick” and writes never “silently fail”.
Definition & Why Repeated START Exists
Repeated START (Sr) is a START condition issued without a preceding STOP. It allows a single logical operation to be split into phases (e.g., “write register pointer” → “read data”) while keeping bus ownership and device context.
Engineering meaning (what Sr guarantees)
- Transaction continuity: the phases belong to one combined transaction, without releasing the bus in-between.
- Context continuity: devices that latch an internal pointer/state on the write phase can be read immediately with deterministic behavior.
- Phase switch: direction can switch safely (W → R) while re-addressing the target device after Sr.
Typical combined-transaction use cases
- EEPROM random read: write word address → Sr → read data bytes.
- Register-map read (sensors/PMIC/clock): write register address → Sr → burst read (often auto-increment).
- Command/address phase then data phase: “pointer phase” followed by “payload phase” as one atomic operation.
Why “STOP + START” can be risky (keep this page’s scope)
- Pointer/state may reset: some devices treat STOP as an end-of-command boundary and re-initialize internal state.
- Non-atomic behavior: the read phase may no longer be guaranteed to correspond to the immediately prior pointer phase.
- Bus is released: releasing the bus between phases removes determinism in systems with bus contention (multi-master details belong to the dedicated page).
Pass criteria (bring-up): a logic/protocol capture shows S → Addr(W) → pointer → Sr → Addr(R) → data → P as one combined transaction.
Transaction Primitives Refresher (START/STOP/ACK/NACK)
Combined transactions only behave deterministically when the transaction boundaries are correct. The key primitives are START/STOP and ACK/NACK—especially the last-byte NACK rule during reads.
START vs STOP (engineering semantics)
- START (S): begins a transaction phase; bus becomes “busy”.
- STOP (P): ends a transaction; bus becomes “free”.
- Important for EEPROM: some devices begin the internal write cycle after STOP (write-cycle timing is handled in the Page Write chapter).
ACK/NACK rules that must be correct (read direction)
Rule: For an N-byte read, send ACK after bytes 1…N−1, then send NACK after the last byte, then finish with STOP (or NACK + Sr when immediately starting another phase).
- ACK (during read): “continue, send next byte”.
- NACK (last byte): “done, stop driving more bytes”. This is a bring-up acceptance checkpoint.
Timing names (mention once; no RC math here)
- tSU:STA — START setup boundary (how START is recognized).
- tHD:STA — START hold boundary (how long it remains valid).
- tSU:STO — STOP setup boundary (how STOP is recognized).
Rise-time, pull-up sizing, and RC compliance belong to the “Open-Drain & Pull-Up Network” owner page.
Pass criteria (bring-up): every burst read ends with a visible last-byte NACK followed by STOP (or NACK + Sr when chaining).
Repeated START Semantics & Allowed Patterns
Repeated START (Sr) is a phase boundary inside a combined transaction. It enables a safe W→R (or phase) switch without releasing the bus. The most important rule is simple: after Sr, the target must be addressed again.
Core rules (cross-vendor safe)
- Sr ≠ continue automatically: Sr does not carry the prior address/direction; the controller must send SLA+R/W again.
- Sr is a phase switch: the “pointer/address phase” and “data phase” stay inside one combined transaction.
- Read completion is explicit: burst reads must end with last-byte NACK and then STOP (or NACK + Sr when chaining).
Whitelist patterns (recommended defaults)
Reg read (combined format): S + SLA+W + regAddr + Sr + SLA+R + data… + P
EEPROM random read: S + SLA+W + wordAddr + Sr + SLA+R + data… + P
Burst read end rule: ACK bytes 1…N−1 → NACK last byte → P
Exception boundary (do not blur STOP)
- EEPROM page write often requires STOP: some devices start the internal write cycle only after P. Using Sr instead of STOP can prevent the write cycle from starting (details handled in the Page Write chapter).
- Default rule: finish EEPROM page-write payload with STOP unless the datasheet explicitly allows a different boundary.
Pass criteria (bring-up): after Sr, the trace shows a new address byte (SLA+R/W) before any data phase begins.
EEPROM Random Read: Write Pointer → Sr → Read
EEPROM random read is the canonical “pointer phase → data phase” transaction. The pointer phase writes the word address, then Sr switches to the read phase. Correct read completion requires last-byte NACK and an explicit STOP.
Golden transaction sequence (copy-safe)
Sequence: S + SLA+W + wordAddr(MSB,LSB?) + Sr + SLA+R + data[0..N−1] + P
- After Sr: send SLA+R again before reading bytes.
- Burst end: ACK bytes 0…N−2, then NACK the last byte, then STOP.
Pseudocode (controller-agnostic)
i2c_start();
i2c_send_addr(slave, WRITE); // SLA+W
i2c_send_word_addr(addr); // 8/16-bit word address (datasheet-defined)
i2c_repeated_start(); // Sr (no STOP)
i2c_send_addr(slave, READ); // SLA+R (required after Sr)
for (i=0; i<N-1; i++) data[i] = i2c_read_byte(ACK);
data[N-1] = i2c_read_byte(NACK); // last-byte NACK (end-of-read)
i2c_stop(); // P
Note: word address width and any “block/bank” bits are EEPROM-specific. The transaction remains the same; only the address bytes differ.
Word-address width boundary (keep scope tight)
- 8-bit vs 16-bit word address: determined by EEPROM capacity and datasheet transaction examples; the I²C slave address is not the same as the EEPROM word address.
- Wrong width symptoms: reads look shifted/repeated, or always return a fixed pattern (often 0xFF) despite a “valid-looking” bus capture.
Common bugs (symptom → quick check → fix)
Bug: Sr placed incorrectly
Quick check: capture shows Sr missing or moved before the full wordAddr is sent
Fix: complete the pointer phase (Addr(W)+wordAddr) before Sr, then re-address with Addr(R)
Bug: last byte still ACK (no NACK)
Quick check: analyzer decode shows “ACK” after the final byte, followed by extra clocks/bytes
Fix: ensure the controller issues last-byte NACK, then STOP (or NACK + Sr when chaining)
Pass criteria (bring-up): readback matches expected content and the capture shows last-byte NACK followed by STOP (no extra byte).
Register Read (Sensors/PMIC): Combined Transactions Done Right
Most register-mapped devices use a “write pointer → repeated START → read data” pattern. Correctness comes from two rules: re-address after Sr, and terminate burst reads with last-byte NACK.
Golden templates (cross-vendor default)
8-bit register address: S + SLA+W + reg(8) + Sr + SLA+R + data… + P
16-bit register address: S + SLA+W + regMSB + regLSB + Sr + SLA+R + data… + P
- Pointer phase is WRITE: the register address is sent in a WRITE phase even when the intent is readback.
- Sr requires re-addressing: send SLA+R after Sr before reading any bytes.
- Burst read end: ACK bytes 1…N−1, then NACK the last byte, then STOP.
Auto-increment (AI) boundaries that cause silent read errors
- Window boundary: AI may wrap, freeze, or stop at a block/window edge; long burst reads can repeat values without bus errors.
- Bank/page selection: high address bits may be a bank select; crossing banks in one burst can jump to an unexpected map region.
- Holes / reserved addresses: reading through reserved regions may return fixed patterns or the prior value, often mistaken for SI/noise problems.
Safe strategy: keep burst length inside the datasheet-defined auto-increment window; split reads at window boundaries while keeping the Sr template.
Repeated START vs pointer latch (symptom → cause → countermeasure)
Symptom: STOP + START still reads the “right” register on one device
Cause: pointer/state is kept temporarily by that implementation; behavior varies across vendors and conditions
Countermeasure: treat Sr as the compatibility baseline; do not depend on STOP preserving pointer context
Symptom: same firmware fails after swapping sensor/PMIC vendor
Cause: pointer latch boundary differs (STOP resets pointer on some devices)
Countermeasure: enforce “write reg pointer → Sr → read” and verify Sr + re-address in captures
Pass criteria (bring-up): analyzer decode shows regAddr in the WRITE phase, then Sr → SLA+R, and a burst read ending with last-byte NACK + STOP.
Page Write Fundamentals: Page Boundary, Wrap, and What “Write Cycle” Means
EEPROM writes are constrained by page size and by the internal write cycle. The most common silent failure is crossing a page boundary in a single write burst, which can cause wrap-around overwrite or dropped bytes (device-dependent). Treat page boundaries as hard constraints.
Page size and “one burst maximum”
- Page size (N bytes): a page write can program up to N bytes within the same page window (N is datasheet-defined).
- Crossing a page boundary is unsafe: behavior can be wrap-around overwrite, discard, or other device-dependent outcomes.
Boundary strategy (how to avoid wrap/overwrite)
- Compute remaining bytes to the end of the current page (page_end − start_addr).
- Split the payload: write the first chunk to page_end, then continue at the next page start.
- Finish each chunk with STOP to trigger the write cycle, then wait for completion.
- Never rely on wrap behavior as a feature; treat it as a correctness failure.
What “write cycle” means (tWR semantics)
- STOP is the trigger: many EEPROMs begin internal programming only after STOP following the write payload.
- Device is busy during tWR: access may NACK (busy NACK) or return old data until programming completes (behavior varies by device).
- Engineering rule: verify completion before trusting readback (fixed delay or ACK polling; detailed handling can be implemented as a dedicated recovery step).
Failure signatures (symptom → quick check → fix)
Symptom: immediate readback shows old value
Quick check: read occurs during tWR (no completion wait); STOP boundary is present but no wait is applied
Fix: wait for write-cycle completion (delay or ACK polling) before readback validation
Symptom: missing bytes / corruption only on large writes
Quick check: payload crosses page boundary in a single burst
Fix: split writes at page boundaries; each chunk ends with STOP and completion wait
Symptom: start-of-page bytes overwritten after a cross-boundary write
Quick check: pattern matches wrap-around behavior (end-of-page burst overwrites page start)
Fix: enforce chunking and alignment; do not exceed remaining bytes in the current page
Pass criteria (bring-up): each write chunk stays within a single page, ends with STOP, and readback validation occurs only after write-cycle completion.
Busy Handling: ACK Polling, NACK-as-Busy, and Timeouts
EEPROM page writes are gated by an internal write cycle. A stable production strategy must distinguish busy NACK from real faults, bound waiting time with timeouts, and always exit with a clean bus state.
ACK polling (the minimal, cross-vendor completion check)
Polling probe (recommended): S + SLA+W → (ACK?) → P
- Why SLA+W: it avoids read-phase variables and matches common EEPROM busy semantics; ACK means the device is ready to accept a transaction.
- Each probe must end cleanly: if NACK is observed, generate STOP/bus-free before the next retry.
- Exit condition: the first ACK ends polling; proceed to readback or the next page write chunk.
Production bounds (interval, timeout, retries) — placeholders for platform tuning
X_poll: polling interval (wait between probes)
X_timeout: max time spent polling before escalation
X_retry: max number of probes (optional cap)
X_backoff: optional backoff step (reduce bus pressure under contention)
- Hard rule: never wait unbounded; enforce X_timeout (or X_retry) and exit to a recovery entry on failure.
- Bus hygiene: keep probes short (address-only) and separated by X_poll to avoid starving other traffic.
- Observability: log elapsed wait and final outcome (ACK / TIMEOUT) to correlate field failures.
NACK classification: busy vs real fault (minimum executable checks)
Busy NACK (expected during tWR):
• appears in the post-write window • transitions to ACK within X_timeout • START/STOP still function normally
Real fault NACK / bus failure (not “busy”):
• persists beyond X_timeout • wrong address / device absent • bus cannot reach idle (SDA/SCL stuck low) • controller cannot generate a valid START
Decision rule: treat NACK as busy only inside the expected post-write window; outside that window, escalate to fault handling.
Timeout strategy (minimal executable version)
- Short retry loop: poll at X_poll until ACK or until X_timeout / X_retry is hit.
- Fail cleanup: ensure STOP/bus-free, release bus lock, and return a bounded error to the caller.
- Recovery entry: call a minimal recovery routine (details can live in a dedicated “Error Handling & Recovery” page).
Pass criteria: polling completes within X_timeout on healthy parts; on timeout, the bus returns to idle and the system transitions into a defined recovery path.
Firmware State Machine: “Always Finish Cleanly”
A production-safe I²C implementation is a transaction state machine with strict boundaries. The key rule is simple: every success path and every failure path must end in a defined cleanup state that returns the bus to idle.
Canonical transactions (same skeleton, different middle)
Register Read (Sr): START → ADDR_W → SEND_REG → Sr → ADDR_R → READ… → NACK(last) → STOP → DONE
EEPROM Random Read (Sr): START → ADDR_W → SEND_WORD_ADDR → Sr → ADDR_R → READ… → NACK(last) → STOP → DONE
EEPROM Page Write + Poll: START → ADDR_W → SEND_WORD_ADDR → WRITE_PAYLOAD → STOP → POLL(ACK) → DONE / TIMEOUT
Boundary rules: Sr always re-addresses (ADDR_R/ADDR_W). Burst reads end with last-byte NACK. Writes trigger tWR with STOP.
Concurrency boundaries (bus lock, ISR/DMA, and transaction context)
- One active transaction: serialize access with a bus lock or queue; do not interleave bytes from different transactions.
- ISR/DMA boundary: ISR/DMA may advance the current state only; starting a new transaction is forbidden until cleanup completes.
- Descriptor model: keep address, direction, pointer bytes, length, timeouts, and callbacks in a single transaction context.
“Always finish cleanly” rules (failure branches must converge)
- Any error → FAIL_CLEANUP: NACK, timeout, controller error, or arbitration events must converge to a cleanup state.
- Cleanup goal: generate STOP (or controller-defined bus-free), clear flags/FIFOs, release lock, and return a bounded error code.
- No “silent return”: exiting on error without STOP/bus-free is a primary root cause of stuck buses in production.
- Recovery is an entry point: call a minimal recovery hook only after cleanup (recovery details can live in a dedicated page).
Reset / watchdog: avoid “half-transactions” after reboot (minimum strategy)
- Boot sanity: verify bus-free (SDA/SCL high). If not, enter a minimal recovery path before starting traffic.
- Controller re-init: clear pending interrupts, FIFO, and error flags before the first transaction and after any fatal error.
- Transaction context reset: never reuse partial descriptors; reinitialize length/phase/index on each transaction start.
Pass criteria: analyzer traces show STOP/bus-free after every failure; transactions never overlap; Sr always re-addresses; polling is bounded by X_timeout.
Debugging with Logic/Protocol Analyzer: What “Correct” Looks Like
A reliable capture review focuses on transaction boundaries and mandatory markers. The goal is to separate: Sr semantics issues, missing tWR wait, and ACK/NACK handling faults.
The 6 capture checks that locate most Sr + page-write bugs
- Sr appears and is placed correctly: after pointer/register bytes and before the read address phase.
- Re-address after Sr: the first byte after Sr is always ADDR + R/W.
- Last read byte is NACK: burst reads end with NACK(last) then STOP/bus-free.
- Page write ends with STOP: STOP is the “write cycle trigger” for typical EEPROM page writes.
- Busy NACK is time-bounded: polling shows NACK during tWR and transitions to ACK within X_timeout.
- No long stuck-low: the capture must not show extended SDA/SCL low after STOP; bus returns to idle.
Tip: treat the capture as a transaction checklist. If any item fails, the bug is typically structural (state machine / boundary handling).
“Golden” decode templates for fast visual matching
Register Read (Sr): S → AddrW → Reg → Sr → AddrR → Data… → NACK(last) → P
EEPROM Random Read (Sr): S → AddrW → WordAddr → Sr → AddrR → Data… → NACK(last) → P
Page Write + Poll: S → AddrW → WordAddr → Payload… → P → Poll(S+AddrW: NACK…ACK) → Next
“Looks correct but isn’t”: decoding illusions to avoid
- Sr drawn as STOP+START: some tools display Sr as P+S in the UI. Confirm by checking whether the bus truly enters an idle gap.
- ACK/NACK misread: poor threshold/grounding can corrupt the ACK bit. Cross-check with “extra byte read” symptoms and bus release behavior.
- Decode offset from wrong speed: if the tool’s decode rate is wrong, bytes may be mis-framed. Set decode using measured SCL period, not assumptions.
- Busy NACK treated as fault: inside the post-write window, NACK can be expected. Outside that window, persistent NACK must escalate to timeout + cleanup.
Design Pitfalls & Corner Cases (Strictly on Sr + Page Write)
These corner cases are common in production captures. Each item includes a fast check and a bounded fix. Scope is limited to repeated start semantics, last-byte NACK, page write boundaries, and tWR/busy handling.
Pitfall #1 — Missing re-address after Sr
Symptom: read fails, reads the wrong register, or decode becomes inconsistent after Sr.
Quick check: the first byte after Sr is not an address frame (ADDR_R/ADDR_W).
Fix: force an explicit address phase after Sr in the state machine.
Pass criteria: every Sr is followed by a valid address byte and an ACK (or a bounded error path).
Pitfall #2 — No NACK on the last read byte
Symptom: extra byte is fetched, device does not release as expected, or the next transaction starts unstable.
Quick check: the final data byte shows ACK instead of NACK in the capture.
Fix: implement “NACK(last) + STOP” as a mandatory read termination rule.
Pass criteria: last byte is always NACK; STOP/bus-free is visible after completion.
Pitfall #3 — Cross-page write (wrap/overwrite)
Symptom: data appears shifted, page start bytes are overwritten, failures only occur on larger writes.
Quick check: a single write payload exceeds the remaining bytes in the current page.
Fix: chunk payloads to page boundaries; never allow one transaction to span a page boundary.
Pass criteria: each page write stays within one page; readback verification matches written payload.
Pitfall #4 — Read immediately after write (no tWR wait / unbounded polling)
Symptom: readback returns old values; failures are intermittent and temperature/lot dependent.
Quick check: no poll loop exists, or polling does not enforce X_timeout.
Fix: use ACK polling after STOP; proceed only after ACK or exit via timeout + cleanup.
Pass criteria: busy NACK transitions to ACK within X_timeout on healthy parts; timeout path always restores bus-free.
Pitfall #5 — Controller Sr/STOP automation differs from expectations
Symptom: code requests Sr but the capture shows P+S; or Sr cannot be generated in certain sequences.
Quick check: compare observed bus events against the expected template; use the capture as truth (not the API call sequence).
Fix: verify repeated-start support and transaction boundary rules in the controller TRM; adapt the transaction builder to match hardware behavior.
Pass criteria: capture event markers align with the intended template across resets and error branches.
Pitfall #6 — Page write must STOP to start the internal write cycle
Symptom: payload appears accepted but never programs; readback stays unchanged.
Quick check: no STOP is emitted after the write payload; the bus continues with Sr or a read phase.
Fix: force STOP at the end of every page write, then poll for completion.
Pass criteria: STOP is visible after payload; busy window appears (NACK), then ACK indicates completion.
Engineering Checklist (Design → Bring-up → Production)
This section turns repeated-start + page-write requirements into a practical, tick-box checklist across the full lifecycle. Each item should have evidence (capture/log) and a bounded failure action (timeout + cleanup).
Design checklist (datasheet → firmware rules)
- Freeze datasheet fields (per EEPROM): page size = X bytes, address width = X-bit, tWR(max) = X ms, busy behavior supports ACK polling (Yes/No), write-protect pin behavior (WP / hardware block protect).
- Write chunking rule (mandatory): one page-write transaction must never span a page boundary; payload_len ≤ page_remaining.
- Write completion rule (mandatory): page write ends with STOP to trigger internal programming, then poll until ACK or timeout.
- Polling budget (bounded): poll_interval = X, poll_max = X, total_wait ≤ X ms. Persistent NACK outside the post-write window must escalate (not treated as “busy forever”).
- Read termination rule (mandatory): burst read ends with NACK(last) then STOP/bus-free.
- Failure cleanup rule (mandatory): any error branch must end in STOP (or controller-defined bus-free), and must be time-bounded (no infinite waits).
Concrete EEPROM material examples (fill X fields from datasheets)
Microchip 24LC256 / 24AA256 / 24FC256 · STMicro M24C64 / M24M02 · onsemi CAT24C256 · ROHM BR24G256 (verify package/suffix/availability)
Bring-up checklist (analyzer evidence)
- Sr placement: appears after pointer/register bytes and before the read address phase.
- Re-address after Sr: Sr is immediately followed by ADDR + R/W.
- NACK(last): the final read byte is NACK, then STOP/bus-free.
- STOP after page write: payload ends with STOP before polling begins.
- Busy window looks sane: post-write polling shows NACK(s) transitioning to ACK within X_timeout.
- No stuck-low after cleanup: SDA/SCL return high after STOP; no long low stretches.
Worst-case bring-up exercises
- Full-page writes: write exactly page_size bytes repeatedly, then verify readback.
- Boundary stress: attempt a cross-page payload in test code and confirm firmware chunks it (no wrap/overwrite).
- Power-fail rehearsal: interrupt power during a write and validate boot-time detection + recovery policy.
Production checklist (BIST + counters)
Minimal BIST sequence (recommended)
- Write pattern → STOP (trigger tWR) → ACK poll until done → Readback → CRC/compare → Log counters.
- Use at least: one full-page write, one multi-page (chunked) write, and one random-read verification pass.
Required counters (minimum set)
- poll_count_avg / poll_count_max (distribution matters more than a single average)
- poll_wait_ms_avg / poll_wait_ms_max
- nack_count_total (optionally classify: busy-NACK vs unexpected-NACK)
- timeout_count
- readback_error_count (compare/CRC mismatch)
Pass criteria (placeholders; tune per product)
- poll_max < X ms (derived from tWR(max) + margin)
- timeout_rate < X ppm (per lot / per shift)
- readback_error = 0 (or < X ppm if rework policy allows)
Applications & IC Selection Notes (Strictly relevant to Sr + Page Write)
Only use-cases that depend on combined transactions (write pointer → Sr → read) and EEPROM page-write behavior are listed here. Selection notes focus on the minimum required device/controller capabilities for stable, bounded operation.
Applications (Sr + page write strongly relevant)
1) EEPROM parameter storage (config / serial / calibration)
Templates: Random read: S → AddrW → WordAddr → Sr → AddrR → Data… → NACK(last) → P · Page write: S → AddrW → WordAddr → Payload… → P → Poll(NACK…ACK)
Material examples: Microchip 24LC256 / 24AA256 · ST M24C64 / M24M02 · onsemi CAT24C256 · ROHM BR24G256 (verify suffix/package).
2) Sensor register reads (burst reads, multi-register, FIFO drains)
Template: S → AddrW → Reg → Sr → AddrR → Data… → NACK(last) → P (Sr keeps the combined transaction semantics and avoids relying on vendor-specific “pointer retention after STOP”.)
Material examples: Bosch BME280 · TI TMP117 · Microchip MCP9808 · TI INA219 (verify address map + auto-increment behavior).
3) PMIC / clock / system-control register access (status read, fault clear)
Template: write register address → Sr → read status (burst if needed), then NACK(last) + STOP.
Material examples: Silicon Labs Si5351 · Microchip MCP7940N · NXP PCF8563 · TI TPS65217 (verify register pointer behavior).
IC selection notes (capabilities that matter for Sr + page write)
EEPROM requirements (page write stability)
- Page size + wrap behavior: firmware chunking must match device page boundaries.
- tWR(max) and busy behavior: polling and timeout budgets must be based on worst-case datasheet limits.
- Address width: 8/16-bit word address impacts the pointer phase length and templates.
- Write protection: WP pin / block protection should align with field update policy.
Examples: Microchip 24LC256 / 24AA256 / 24FC256 · ST M24C64 / M24M02 · onsemi CAT24C256 · ROHM BR24G256 (verify ordering codes).
MCU/SoC I²C controller requirements (combined transactions + bounded cleanup)
- Repeated START support: must generate Sr reliably (capture must match the template).
- Last-byte NACK control: hardware/driver must guarantee NACK(last) at the end of burst reads.
- Timeout + stuck detection: bounded waits and forced cleanup (no infinite busy loops).
- Error visibility: interrupts/counters for NACK/timeout/bus errors are strongly preferred for production telemetry.
Concrete MCU examples (controller capability must be confirmed by TRM + capture): ST STM32G031K8 · ST STM32L052C8 · NXP LPC55S16 · Microchip ATSAMD21G18A · TI MSP430FR2355.
“Bus health” telemetry (optional, production-friendly)
- Prefer platforms that can log NACK bursts, timeout counts, and controller reset counts.
- Treat capture evidence as truth: verify actual Sr/STOP behavior on the wire, not only via driver API assumptions.
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FAQs (Repeated START + Page Write + Busy)
Scope guard: only troubleshooting for Sr (repeated START), EEPROM page write, and busy handling (ACK polling / NACK-as-busy). Each answer is structured for fast diagnosis with measurable pass criteria (X placeholders).
Read works once, then always returns the same value — pointer not latched / missing Sr?
Likely cause: The device register pointer was not latched because the combined transaction is broken (missing Sr, or Sr is in the wrong place), or the address phase after Sr is missing.
Quick check: Capture the bus and verify: … RegAddr → Sr → Addr+R appears as one transaction, and Addr+R is re-sent immediately after Sr.
Fix: Use the standard template: S → AddrW → RegAddr → Sr → AddrR → Data… → NACK(last) → P. Do not rely on “pointer retention after STOP”.
Pass criteria: In capture, STOP does not appear between pointer write and read; Sr+AddrR is present; readback changes correctly across ≥ X consecutive reads.
EEPROM write “succeeds” but readback shows old data — tWR not waited / no ACK polling?
Likely cause: Internal write cycle is still in progress (tWR), but firmware reads immediately without polling; or the write transaction did not end with STOP, so the write cycle never started.
Quick check: After the page-write STOP, poll the device address (S + AddrW) and record NACK→ACK timing. If readback changes only after ACK appears, the issue is missing/insufficient busy handling.
Fix: Enforce: page write ends with STOP, then ACK polling until done (or wait tWR(max) if polling is not supported). Only read after completion.
Pass criteria: poll_max < X ms (based on datasheet tWR(max) + margin), readback_error = 0 over ≥ X cycles.
Occasional NACK after page write — device busy or wrong address?
Likely cause: Normal busy NACK during tWR; or unexpected NACK caused by address mismatch (A0/A1/A2 strapping), bus contention, or brownout during the write cycle.
Quick check: Log per-write poll_count and poll_wait_ms. Busy NACK should appear only in the post-write window and must transition to ACK within the expected tWR(max).
Fix: Treat NACK as “busy” only inside the bounded polling loop. Outside the window, classify as fault: verify slave address pins, check VCC stability during tWR, and ensure STOP is issued before polling.
Pass criteria: unexpected_nack_rate < X ppm, poll_wait_ms_max < X ms, and timeout_count = 0.
Data corruption only when writing > page size — page boundary wrap?
Likely cause: The payload crosses a page boundary. Many EEPROMs wrap the internal page buffer and overwrite the start of the page (or exhibit vendor-specific behavior).
Quick check: Write a known ramp pattern across a boundary (end-of-page to next page) and read back both pages. Wrap shows “tail overwrites head” inside the same page.
Fix: Implement mandatory chunking: payload_len ≤ page_remaining. Split writes at every boundary and poll completion after each page-write STOP.
Pass criteria: Boundary stress test passes for ≥ X iterations with readback_error = 0; maximum single-write payload never exceeds page_remaining.
Logic analyzer shows STOP between write and read — controller auto-STOP. How to disable?
Likely cause: The I²C controller/driver is configured for “STOP after write” (two separate transfers) instead of a single combined transfer using repeated START.
Quick check: Compare two captures: current behavior vs expected template. Expected capture must show … RegAddr → Sr → AddrR with no STOP in between.
Fix: Use the driver API or controller mode that supports “combined message / restart / no-stop / repeated-start”. If the stack uses two messages, ensure the first message is flagged as no-STOP and the second begins with a restart.
Pass criteria: Capture shows STOP count between phases = 0 and Sr count = 1 for each register read; functional readback stable across ≥ X devices/boots.
Last byte read is duplicated / one extra byte appears — missing NACK on final byte?
Likely cause: The master ACKs the final byte instead of NACK(last), so the slave continues driving another byte or the controller clocking extends unexpectedly.
Quick check: In capture, inspect the ACK bit after the last intended byte. It must be NACK followed by STOP (or repeated start to another transaction).
Fix: Configure the controller/driver to auto-NACK on last byte or explicitly send NACK before STOP. Avoid “read N bytes” APIs that do not guarantee last-byte NACK.
Pass criteria: last_byte_nack = true in ≥ X captures; no extra/duplicate bytes across ≥ X consecutive reads.
Bus hangs after an error — what are the minimal recovery steps?
Likely cause: The error path does not finish cleanly (no STOP/bus-free), leaving the controller or slave in a half-transaction state; in some cases SDA is held low by a slave still expecting clocks.
Quick check: Measure bus idle state: both SCL=H and SDA=H. If SDA stays low, the bus is not free and must be recovered before retries.
Fix: Use a minimal bounded recovery sequence: (1) request STOP (or controller “abort”); (2) re-init I²C controller; (3) if SDA still low, generate X clock pulses on SCL (GPIO) then STOP; (4) retry up to X times, else fail fast and log.
Pass criteria: bus_stuck_low_count = 0 in normal runs; recovery completes within X ms; retry success rate ≥ (100 − X)%.
Polling never ends — wrong slave address, WP enabled, or power brownout?
Likely cause: The polled address is incorrect (A0/A1/A2 mismatch), the device is not powered/held in reset, WP/block-protect prevents the intended write, or VCC dips during tWR so the device never completes properly.
Quick check: Confirm the physical address straps, then perform a presence scan (AddrW probe) before any write. During failure, log VCC(min) in the tWR window if possible.
Fix: Bound polling: poll_interval = X, total_wait ≤ X ms. On timeout, run cleanup + re-init and classify as fault. If WP is used, verify WP level and block-protect bits match the update policy.
Pass criteria: timeout_count = 0 (or < X ppm), presence_scan_ack = 100%, and poll_wait_ms_max < X ms.
Works at 100 kHz but fails at 400 kHz — timing margins (where to look first)?
Likely cause: Reduced timing margin at higher speed exposes borderline rise-time/hold-time behavior, making Sr placement/ACK sampling fragile (especially on longer traces or heavier loads).
Quick check: Compare captures at 100 kHz vs 400 kHz and check: ACK bit integrity, Sr timing position, and whether any unexpected NACKs appear only at 400 kHz.
Fix: Keep this page scoped: ensure Sr/STOP/NACK(last) logic is correct first. If the logic is correct but 400 kHz still fails, follow the pull-up / rise-time and bus capacitance guidance on the dedicated page (link placeholder).
Pass criteria: At 400 kHz, unexpected_nack_rate < X ppm and readback_error = 0 over ≥ X transactions.
Some EEPROM requires STOP to start the write cycle — how to confirm quickly?
Likely cause: Page write programming begins only after STOP; without STOP, the device stays in “receive buffer” mode and does not enter internal tWR.
Quick check: Run A/B test in firmware: (A) write payload then STOP; (B) write payload but delay without STOP. In capture, only case (A) should show a post-STOP busy NACK window during polling.
Fix: Always end page write with STOP, then poll for completion. Never attempt to “chain” a page write into a read using Sr; treat write completion as a separate phase.
Pass criteria: After STOP, polling shows NACK→ACK within X ms; readback verifies the new data with readback_error = 0.
Write passes on bench, fails in production — fixture or power dip during tWR?
Likely cause: VCC droop or intermittent contact during the internal write window (tWR) corrupts writes or prevents completion, causing timeouts or stale readback only in the production environment.
Quick check: Log poll_wait_ms_max, timeout_count, and readback_error_count per unit. Correlation between long poll waits and failures is a strong indicator. If available, measure VCC(min) during tWR.
Fix: Increase robustness: bounded retry with cleanup, verify presence before write, and add a production BIST: write → STOP → poll → readback → compare. Stabilize fixture contact and power delivery during tWR.
Pass criteria: timeout_rate < X ppm, readback_error = 0, and poll_wait_ms_max < X ms across ≥ X units.
Mixed devices behave differently — vendor differences (page wrap / busy NACK policy). How to stay compatible?
Likely cause: EEPROMs differ in page wrap behavior and busy signaling. Some tolerate more patterns than others; relying on undefined behavior causes cross-vendor failures.
Quick check: Run a compatibility suite per candidate EEPROM: (1) boundary write stress; (2) polling distribution; (3) power-fail rehearsal; (4) readback CRC over ≥ X loops.
Fix: Code to the strict portable rules: (a) never cross page boundaries; (b) STOP always ends page write; (c) poll completion with timeout; (d) treat persistent NACK outside post-write window as fault.
Pass criteria: Across all vendors under test: readback_error = 0, timeout_rate < X ppm, and compatibility suite passes with identical firmware settings.
Tip: For production telemetry, log at least poll_wait_ms_max, poll_count_max, timeout_count, and readback_error_count. Use captures as ground truth for Sr / STOP / NACK(last) behavior.
