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Inverting / Negative LDO: Low-Noise Rails for Precision Bias

Inverting / Negative LDO: Low-Noise Rails for Precision Bias

Introduction & Search Intent

Goal: explain why a negative (inverting) LDO is the simplest way to get a clean −0.5…−15 V rail for op-amp/ADC/sensor bias, and where it beats inverting buck, charge-pump inverter, and rail-splitter.

Why Negative LDO

  • Low noise (µVrms) and high PSRR at audio/IF bands.
  • Simple loop; fast time-to-first-pass for validation.
  • Predictable stability with Cout/ESR window.

Boundaries

  • Efficiency & output current are limited vs switching.
  • Dropout defined in negative domain; watch margin.
  • May need a small minimum load for stability.
Negative LDO Low noise • High PSRR • Simple stability VOUT− = −0.5…−15 V Inverting Buck(-Boost) + High efficiency / current − Switching ripple & loop complexity − Longer debug time Charge-Pump Inverter + Small & simple − Ripple higher, limited current − Needs good output filtering Rail-Splitter (Virtual Ground) + Quick mid-rail reference − Not a real negative supply − Load symmetry constraints Choose Negative LDO when noise/PSRR and quick stability tuning outrank efficiency/current.
Why choose a negative LDO: low-noise, high-PSRR rail vs inverting buck, charge-pump inverter, and rail-splitter.

SEO intents Inverting/negative LDO definition, selection for low-noise bias, PSRR at 10–100 kHz, Cout/ESR stability, minimum load, start-up order, AEC-Q100 options.

Architecture & Principle (Negative Domain + Unified Reference/Error-Amp)

This section clarifies how the negative reference is built, how the error-amp CMVR bounds the feedback divider, how to sample against the correct ground reference, and how protection (OCP/OTP) behaves in the negative domain.

Reference & Error-Amp

  • Reference mirroring / level shift for negative rail.
  • Keep divider node inside error-amp CMVR.
  • Correct polarity for VOUT− sampling; use Kelvin sense.

Stability Window

  • Target phase margin → pick Cout/ESR range.
  • Minimum load may be required at light load.
  • RC compensation as last resort to damp peaking.

Protection & Start-Up

  • OCP/short semantics in negative domain.
  • OTP hysteresis & restart behavior.
  • Clamp/back-drive protection with op-amp inputs.
VIN / GND Input supply & ground reference Negative LDO Core Reference mirror • Error-amp • Pass device Error-amp CMVR — keep divider node inside VOUT− −0.5…−15 V to load Kelvin sense to load return Feedback: divider to CMVR Correct polarity • Sense− to load Stability Pick Cout/ESR for phase margin Minimum load may be required Protection OCP/short semantics in negative domain OTP hysteresis & restart behavior Start-Up Pre-bias loads & back-drive clamp Order vs positive rails & references Measure noise/PSRR with proper bandwidth & probe returns; log VOUT−, IOUT, and temperature for A/B comparisons.
Negative LDO architecture: reference mirroring, error-amp CM range, correct negative feedback polarity, Kelvin sense, and protection semantics.

Design checklist: keep the divider node within CMVR, route Sense− to the load pad, define a Cout/ESR window for target phase margin, validate minimum-load behavior, and verify start-up with pre-bias cases.

Noise & PSRR (Bandwidth & Targets)

Quantify noise in µVrms over the stated bandwidth, and anchor PSRR at 10 kHz and 100 kHz. Use simple prefilters (RC, bead, π) to attenuate upstream ripple without hurting stability.

Metrics

  • Noise: µVrms (10 Hz–100 kHz) + density nV/√Hz.
  • PSRR: dB @10 kHz / @100 kHz (optionally @1 MHz).
  • Ripple (p-p) with probe bandwidth stated.

Measurement

  • Short return path / spring ground tip.
  • Band-limit the scope / analyzer.
  • Log VOUT−, IOUT, and temperature.
VIN / GND Upstream supply RC Pole vs load transients Ferrite bead Z(f), DC I, saturation π filter C–R/L–C; watch resonance Negative LDO Low-noise • High PSRR VOUT− = −0.5…−15 V Measure Noise: µVrms (10 Hz–100 kHz) PSRR: dB @10 kHz / @100 kHz Limit probe bandwidth PSRR markers @10 kHz @100 kHz Place filters close to VIN/GND; verify with A/B logs and identical bandwidth limits.
Noise/PSRR measurement and simple input prefilters (RC, ferrite bead, π) for a negative LDO; include 10/100 kHz PSRR markers.

Stability Tuning (Cout/ESR Window & Load Region)

Pick Cout and ESR to meet phase-margin targets. Diagnose light-load buzz/self-excitation, and route Sense− as Kelvin to the load pad.

Window

  • Stable band on Cout–ESR map.
  • Account for tolerance & temperature.
  • Target ≥45–60° phase margin.

Light-Load Fixes

  • Increase Cout / add small ESR.
  • Enable minimum load (mA).
  • Last resort: RC zero.

Sense− Layout

  • Kelvin to load pad.
  • Short Cout loop; split returns.
  • Avoid high dv/dt zones.
Cout–ESR Stability Window ESR → Cout → Stable ESR too high → ripple/peaking ESR too low → phase deficit Very high ESR → noisy/unstable Cout too small Sense− Routing Good (Kelvin) Load Pad Sense− Power return Bad (shared return) Load Pad Sense− over power path → noise Tune Cout/ESR first → add minimum load if needed → RC zero last. Sense− must Kelvin to the load pad.
Cout–ESR stability window (safe vs risk zones) and Sense− Kelvin routing; prioritize Cout/ESR, then minimum load, RC zero last.

Record step-load response (light → rated), verify overshoot/ringing, sweep ESR and minimum-load settings, then log results for A/B comparisons.

Start-Up & Sequencing (Coordination with Positive Rails / References / PG)

Recommended power-up order: References & positive rails → Negative LDO → PG goes valid → Enable downstream. Control pre-bias and back-drive via series resistors and clamps; ensure power-down avoids reverse conduction.

Order & Timing

  • Refs/positive rails first, then VOUT−.
  • PG gates downstream enables.
  • Soft-start slope within clamp limits.

Pre-Bias & Back-Drive

  • Identify residual charge sources.
  • Series R + diode clamp when needed.
  • Prefer negative rail off first at power-down.

PG Integration

  • Define polarity/threshold clearly.
  • Wire AND/OR logic with EN pins.
  • Test cold/hot, up/down, pre-bias cases.
Refs / Positive Rails Negative LDO (VOUT−) PG (valid → enable downstream) Pre-bias window Power-down order Do not enable loads here Prefer: VOUT− off first (or together) → positive rails → refs Gate downstream with PG; verify cold/hot start and pre-bias; limit dV/dt within clamp tolerance.
Start-up order with PG gating; avoid enabling loads in the pre-bias danger window; plan a safe power-down to prevent back-drive.
Negative LDO VOUT− to load Op-Amp Front-End Input clamps / ESD paths Series R Clamp diode to VOUT− Potential back-drive path Limit dV/dt, use series R and clamp to prevent reverse current during start-up/shutdown and pre-bias events.
Back-drive control: limit dV/dt, add a series resistor and clamp diode referenced to VOUT− near the load.

Layout Checklist (Grounding / Loops / Cross-Domain Noise)

Unify AGND/PGND close to the LDO, keep the negative loop short, Kelvin-route Sense− to the load pad, shield sensitive nodes, and reserve test points for validation.

GND & Returns

  • Single-point or short neck unification.
  • Shortest VOUT−/Cout return loop.
  • Symmetric vias; avoid Sense− over power path.

Sense & Sampling

  • Kelvin Sense− to load pad.
  • Divider close to the LDO pins.
  • Match resistors; minimize parasitics.

Placement & Shield

  • Cout close to VOUT−/GND pins.
  • Prefilter close to VIN/GND.
  • Guard/ground around sensitive nodes.
Good Single-point AGND/PGND Short Cout loop; Sense− Kelvin Don’t Shared return for Sense− Long loop → noise & ringing Test Points TP: VOUT− • Sense− • PG • VIN Reserve A/B footprints for Cout/ESR/series R/clamp diode Keep sensitive nodes short and shielded; route signals away from high dv/dt regions; verify with step-load and ESR sweeps.
Layout checklist: single-point AGND/PGND, short negative loop, Kelvin Sense−, shielding, and test points with A/B footprints.
Do (Kelvin) Load pad Sense− Don’t (shared) Sense− over power return → error/noise Keep Sense− separate from power current; join returns at the LDO; avoid long parallel runs near noisy paths.
Sense− routing: Kelvin to the load (Do) vs shared power return (Don’t) that injects error and noise.

Application Scenarios (Modular, Real-World)

Four focused use cases for a negative LDO. Each card lists design goal, key metrics, layout points, common issues, and procurement fields to keep selection and validation fast.

Precision Sensor Bias (Low Noise First)

Design goalUltra-low noise, high PSRR bias for bridges/strain/chemical/piezo. Key metricsNoise_uVrms_10Hz_100kHz · PSRR_dB_10k/100k · MinLoad_mA · CMVR_fit LayoutSense− Kelvin→load; Cout tight to VOUT−/GND; prefilter near VIN. IssuesLight-load buzz → increase Cout / add small ESR → then min load; false high PSRR → limit bandwidth. ProcureVoutm_set · Iq_uA · Cout_uF · ESR_mOhm_range · Prebias_Safe · AECQ100

Audio Preamp (PSRR/Noise/Ground Loops)

Design goalHigh PSRR and low noise in 20 Hz–20 kHz; avoid ground-loop hum. Key metricsPSRR_dB_1k/10k · Noise_uVrms_20Hz_20kHz · Ripple_pp · Ground_Loop_Risk LayoutAGND/PGND single-point; guard rings; route away from high dv/dt. Issues50/60 Hz hum → check ground loop & zoning; confirm start-up sequencing with PG. ProcureSoftStart_ms · PG_Logic · Clamp_Recommended · Cout_To_Pins_mm

ADC Negative Common-Mode Supply (Stability Window)

Design goalEnsure phase margin inside the VOUT− stability window under sampling transients. Key metricsStable_No_RC · Phase_Margin_Target · ESR_mOhm_range · MinLoad_mA LayoutDivider/comp near LDO; adjust Cout/ESR first; Sense− back to AGND. IssuesSampling injection → add Cout/small ESR → min load → RC zero (last). ProcureTransient_Overshoot_mV · Settling_us · EN_Threshold · Reverse_Conduction_Clamp

Small Instrumentation Op-Amp ± Supply (Sym/Asym −V)

Design goalProvide symmetric or asymmetric −V to match input range and headroom. Key metricsTracking_Error_mV · PowerDown_Order · PG_to_EN_delay_ms · Iq_uA LayoutClose ± loop at the load; PG→EN logic; shut down −V first or together. IssuesBack-drive at power-down → series R + clamp diode near load; use PG hysteresis. ProcureBackdrive_Clamp · Prebias_Safe · SS_Ramp_ms · Temp_Grade

Validation Playbook (Matrix, Curves, Start-Up Snapshots)

Run a matrix across VIN × VOUT− × IOUT × temperature; derive settings for Cout/ESR/min-load. Capture noise/PSRR curves, start-up snapshots, ESR sweeps, and A/B comparisons with single-variable changes.

Config_ID VIN_set VOUTm_set IOUT_case T_case Cout_choice ESR_step MinLoad_on Noise_uVrms_10Hz_100k PSRR_dB_10k PSRR_dB_100k Overshoot_mV Ringing_cycles Startup_Glitch_mV Stable_No_RC Phase_Margin_Est Case_Temp_C Probe_BW_kHz Timestamp
G00+12−5.0light2522µF50mΩN——————Y~55°351002025-10-29
Matrix VIN·VOUT·IOUT·T Cout/ESR step Min load on/off A/B change Outputs Noise_uVrms PSRR_10k/100k Overshoot/Ringing Stable_No_RC · Phase Thermal Change one variable at a time; log bandwidth and temperature; export CSV + curves for review.
Validation matrix: vary VIN/VOUT−/IOUT/temperature; step Cout/ESR and min load; log noise, PSRR, transients, stability, and thermal.
Cold / No Pre-bias Cold / Pre-biased Hot / No Pre-bias Hot / Pre-biased VOUT− & PG Glitch risk Clamp here Capture identical bandwidth and temperature; mark glitch peaks and PG thresholds; keep one-variable A/B changes.
Start-up snapshots: cold/hot × pre-biased/non-pre-biased with PG and negative rail markers; highlight glitch windows and clamp points.

Pass/Fail gates (suggestion): Noise_uVrms ≤ target; PSRR_10k/100k ≥ targets; Overshoot/Ringing below limits; Startup_Glitch bounded in all four quadrants; Stable_No_RC = Y or MinLoad ≤ threshold.

VOUT: −0.5…−15 V Noise (10 Hz–100 kHz): ≤ 60 μVRMS PSRR @10 kHz: ≥ 40–70 dB IOUT: 20–1000 mA (by device) Stable_No_RC: Y preferred AEC-Q100: mark if applicable
Texas Instruments STMicroelectronics Renesas onsemi Microchip NXP Melexis

Texas Instruments

Mature negative LDO portfolio; low-noise & high-PSRR parts for analog/audio rails.

  • TPS7A33 — −1.18…−33 V, 1 A, 16 μVRMS (10 Hz–100 kHz), ~72 dB @10 kHz.
  • TPS7A30 — −1.18…−33 V, 200 mA, ultralow-noise; compact packages.
  • TPS723 — −10…−2.7 V (adj), 200 mA, small-signal negative LDO.

Refs: TI datasheets (TPS7A33/TPS7A30/TPS723).

STMicroelectronics

Negative LDO available in rad-hard line for harsh/space; standard line has negative regulators too.

  • RHFL7913A — adj −9…−1.2 V (family), low dropout, radiation-hard (space).

Refs: ST RHFL7913A product page.

Renesas (Intersil)

Negative adjustable LDO for demanding environments (rad-hard).

  • ISL72991RH — −2.25…−26 V, up to 1 A, adj current limit, shutdown.

Refs: Renesas ISL72991RH page.

onsemi

Has negative linear regulators (classic 79xx family). Note: not LDO; dropout ≈1.7 V @ tens of mA.

  • MC79M05 — −5 V, 0.5 A (negative linear regulator, non-LDO).
  • MC79L05ACPRAG — −5 V, 100 mA (negative linear regulator, non-LDO).

Refs: onsemi MC79M00 overview; Digi-Key MC79L05ACPRAG.

Microchip (Micrel)

Proven μCap negative LDOs for small-signal/audio bias rails.

  • MIC5271-5.0 — −5.0 V, 100 mA, dropout ~0.5–0.7 V @100 mA.
  • MIC5271-3.0 — −3.0 V, 100 mA, ceramic/tantalum stable.

Refs: Microchip MIC5271 product & datasheet.

NXP

No standalone negative-LDO in current catalog; PMICs (PF81xx/82xx) integrate positive LDOs only. For −V rails, use TI/Microchip negative LDO or a buck-invert + post-filter.

  • PMIC examples: PF8100/PF8200 (positive LDOs inside; not negative).

Refs: NXP PF8100/8200 datasheets.

Melexis

No standalone negative-LDO. Melexis focuses on sensors/automotive ICs; use external negative LDO (e.g., TI TPS7A33 / Microchip MIC5271) for −V sensor bias.

Brand PN VOUT Range IOUT (max) Noise (10 Hz–100 kHz) PSRR @10 kHz Notes
Texas Instruments TPS7A33 −1.18…−33 V 1 A ≈16 μVRMS ≈72 dB Low-noise/high-PSRR; ceramic stable. (TI datasheet)
Texas Instruments TPS7A30 −1.18…−33 V 200 mA Low-noise High PSRR Small pkg; CNR/FF pins helpful. (TI datasheet)
Texas Instruments TPS723 Adj −10…−2.7 V 200 mA — — Legacy small-signal negative LDO. (TI product page)
STMicroelectronics RHFL7913A adj −9…−1.2 V (family) — — — Rad-hard negative LDO (space). (ST RHFL7913A)
Renesas (Intersil) ISL72991RH −2.25…−26 V 1 A — — Adj ILIM, SD pin (rad-hard). (Renesas page)
onsemi MC79M05 Fixed −5 V 0.5 A — — Non-LDO; dropout ~1.7 V @40 mA. (onsemi/DK refs)
onsemi MC79L05ACPRAG Fixed −5 V 100 mA — — Non-LDO; classic 79L05 family. (Digi-Key page)
Microchip MIC5271-5.0 Fixed −5.0 V 100 mA — (μCap low noise) — LDO; ceramic stable. (Microchip datasheet)
Microchip MIC5271-3.0 Fixed −3.0 V 100 mA — (μCap low noise) — LDO; zero-current off mode. (Microchip datasheet)
Cross-brand substitution (when out-of-stock):

Audio/preamp rails → prioritize Noise & PSRR(1–10 kHz); Sensor/ADC bias → ensure Stable_No_RC and ESR window; Automotive → require explicit AEC-Q100. If onsemi/NXP/Melexis lack negative LDO, swap to TI TPS7A33/TPS7A30 or Microchip MIC5271 with the same IOUT/dropout envelope and re-verify stability.

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Frequently Asked Questions

Why choose a negative LDO instead of a buck-invert or charge pump for −V rails?

Negative LDOs excel when you need very low noise, high PSRR at audio or measurement bandwidths, simple compensation, and predictable start-up. Buck-invert or charge pumps win on efficiency or extreme VIN spans, but add switching noise and filtering complexity. Start with noise/PSRR targets, then compare BOM and layout. See Introduction and Architecture.

How should I size noise and PSRR targets for sensor bias versus audio preamps?

Precision sensors care about integrated noise in roughly 10 Hz–100 kHz and high PSRR at 10/100 kHz. Audio preamps emphasize 20 Hz–20 kHz, where ripple tones are audible; favor higher PSRR at 1–10 kHz and low broadband noise. Calibrate numbers from end-to-end SNR. See Noise & PSRR and Scenarios.

What’s the correct method to measure PSRR on a negative rail without over-reporting?

Limit analyzer bandwidth, isolate grounds, and inject ripple through a known source impedance. Probe at the load with short returns, then read PSRR at 10 kHz and 100 kHz markers. Avoid saturating clamps or current limits during sweeps. Log the setup with bandwidth and impedance. See Noise & PSRR and Validation.

My −V rail rings at light load. What is the recommended stability-fix order?

Increase Cout first, then introduce a small ESR within the device’s stability window. If ringing persists, add a minimal bleed load to shift the operating point. As a last step, place an RC zero across the divider to restore phase margin. Re-verify across temperature. See Stability Tuning.

How do I select Cout and ESR to remain inside the stability window over temperature?

Choose ceramic or polymer parts whose ESR stays within the device’s allowed window at cold and hot corners. Sweep ESR with 4–6 points and log ringing/overshoot. If cold ESR drops too low, add series resistance or mix capacitors to shape the zero. Document pass/fail thresholds. See Stability Tuning and Validation.

What start-up order avoids back-drive into op-amp input clamps on ± rails?

Enable references and the positive rail, then the negative LDO, then release PG to downstream devices. On power-down, turn off −V first or both together to prevent clamp conduction. Add series resistance and a diode clamp near the load if the op-amp requires it. See Start-Up & Sequencing.

How should PG/EN logic be coordinated between the negative LDO and downstream ADC/amps?

Use PG with hysteresis to gate downstream EN pins, aligning rails before sensitive inputs become active. Verify four quadrants—cold/hot and pre-biased/non-pre-biased—so no spurious PG edges release early. Record delays and tolerances to make A/B swaps repeatable. See Start-Up and Validation.

Where should Sense− and the feedback divider return—AGND or power ground?

Kelvin Sense− to the load and return the divider to AGND at a single-point tie. Keep the sense pair short, tightly coupled, and away from large current loops. Avoid sharing copper with high di/dt paths to minimize common impedance error. See Layout Checklist.

Persistent 50/60 Hz hum—should I suspect layout or sequencing first?

Start with layout: confirm single-point AGND/PGND, guard sensitive nodes, and route away from dv/dt sources. Then verify sequencing so op-amp inputs are never forward-biased during rail ramp. If hum remains, add input pre-filter and check cabling loops. See Scenarios, Layout, and Start-Up.

How do I log noise and transients so A/B device swaps produce fair conclusions?

Fix bandwidth, temperature, load, and probe points; change only one variable per run. Export CSV with noise_uVrms, PSRR at 10/100 kHz, overshoot, ringing cycles, and startup glitch. Keep a Config_ID and identical timebases for overlays. See Validation.

Can I run the negative LDO without an added RC compensation network?

Many parts are stable with ceramic Cout inside a specified ESR window and sometimes a minimum load. Validate with ESR sweeps and corner temperatures. If phase margin is marginal under sampling, introduce a small RC zero across the divider as a controlled last resort. See Stability Tuning and IC Selection.

What is the minimal pre-filter for a noisy positive input feeding the negative LDO?

Start with a small RC to set a corner below the target bandwidth, then add a ferrite bead if switching ripple persists. For harsh EMI, use a π filter but confirm source stability and current limits. Place components close to VIN pins and reference to AGND. See Noise & PSRR and Layout.

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